#ifndef _EXIOCT_H
#define _EXIOCT_H
#ifdef __cplusplus
extern "C" {
#endif
#include <exioctso.h>
#define EXT_VERSION 5
#define EXT_DEF_SIGNATURE_SIZE 8
#define EXT_DEF_WWN_NAME_SIZE 8
#define EXT_DEF_WWP_NAME_SIZE 8
#define EXT_DEF_SERIAL_NUM_SIZE 4
#define EXT_DEF_PORTID_SIZE 4
#define EXT_DEF_PORTID_SIZE_ACTUAL 3
#define EXT_DEF_MAX_STR_SIZE 128
#define EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH 16
#define EXT_DEF_MAC_ADDRESS_SIZE 6
#define EXT_DEF_ADDR_MODE_32 1
#define EXT_DEF_ADDR_MODE_64 2
#define EXT_DEF_MAX_HBA EXT_DEF_MAX_HBA_OS
#define EXT_DEF_MAX_BUS EXT_DEF_MAX_BUS_OS
#define EXT_DEF_MAX_TARGET EXT_DEF_MAX_TARGET_OS
#define EXT_DEF_MAX_LUN EXT_DEF_MAX_LUN_OS
#define EXT_DEF_NON_SCSI3_MAX_LUN EXT_DEF_NON_SCSI3_MAX_LUN_OS
typedef struct {
UINT64 Signature;
UINT64 RequestAdr;
UINT64 ResponseAdr;
UINT64 VendorSpecificData;
UINT32 Status;
UINT32 DetailStatus;
UINT32 Reserved1;
UINT32 RequestLen;
UINT32 ResponseLen;
UINT16 AddrMode;
UINT16 Version;
UINT16 SubCode;
UINT16 Instance;
UINT16 HbaSelect;
UINT16 VendorSpecificStatus[11];
} EXT_IOCTL, *PEXT_IOCTL;
typedef union _ext_signature {
UINT64 Signature;
char bytes[EXT_DEF_SIGNATURE_SIZE];
} ext_sig_t;
#define EXT_ADDR_MODE EXT_ADDR_MODE_OS
#define EXT_STATUS_OK 0
#define EXT_STATUS_ERR 1
#define EXT_STATUS_BUSY 2
#define EXT_STATUS_PENDING 3
#define EXT_STATUS_SUSPENDED 4
#define EXT_STATUS_RETRY_PENDING 5
#define EXT_STATUS_INVALID_PARAM 6
#define EXT_STATUS_DATA_OVERRUN 7
#define EXT_STATUS_DATA_UNDERRUN 8
#define EXT_STATUS_DEV_NOT_FOUND 9
#define EXT_STATUS_COPY_ERR 10
#define EXT_STATUS_MAILBOX 11
#define EXT_STATUS_UNSUPPORTED_SUBCODE 12
#define EXT_STATUS_UNSUPPORTED_VERSION 13
#define EXT_STATUS_MS_NO_RESPONSE 14
#define EXT_STATUS_SCSI_STATUS 15
#define EXT_STATUS_BUFFER_TOO_SMALL 16
#define EXT_STATUS_NO_MEMORY 17
#define EXT_STATUS_UNKNOWN 18
#define EXT_STATUS_UNKNOWN_DSTATUS 19
#define EXT_STATUS_INVALID_REQUEST 20
#define EXT_STATUS_DEVICE_NOT_READY 21
#define EXT_STATUS_DEVICE_OFFLINE 22
#define EXT_STATUS_HBA_NOT_READY 23
#define EXT_STATUS_HBA_QUEUE_FULL 24
#define EXT_STATUS_INVALID_VPINDEX 25
#define EXT_DSTATUS_GOOD 0x00
#define EXT_DSTATUS_CHECK_CONDITION 0x02
#define EXT_DSTATUS_CONDITION_MET 0x04
#define EXT_DSTATUS_BUSY 0x08
#define EXT_DSTATUS_INTERMEDIATE 0x10
#define EXT_DSTATUS_INTERMEDIATE_COND_MET 0x14
#define EXT_DSTATUS_RESERVATION_CONFLICT 0x18
#define EXT_DSTATUS_COMMAND_TERMINATED 0x22
#define EXT_DSTATUS_QUEUE_FULL 0x28
#define EXT_DSTATUS_NOADNL_INFO 0x00
#define EXT_DSTATUS_HBA_INST 0x01
#define EXT_DSTATUS_TARGET 0x02
#define EXT_DSTATUS_LUN 0x03
#define EXT_DSTATUS_REQUEST_LEN 0x04
#define EXT_DSTATUS_PATH_INDEX 0x05
#define EXT_CC_QUERY EXT_CC_QUERY_OS
#define EXT_CC_SEND_FCCT_PASSTHRU EXT_CC_SEND_FCCT_PASSTHRU_OS
#define EXT_CC_REG_AEN EXT_CC_REG_AEN_OS
#define EXT_CC_GET_AEN EXT_CC_GET_AEN_OS
#define EXT_CC_SEND_ELS_RNID EXT_CC_SEND_ELS_RNID_OS
#define EXT_CC_SEND_SCSI_PASSTHRU EXT_CC_SCSI_PASSTHRU_OS
#define EXT_CC_READ_HOST_PARAMS EXT_CC_READ_HOST_PARAMS_OS
#define EXT_CC_READ_RISC_PARAMS EXT_CC_READ_RISC_PARAMS_OS
#define EXT_CC_UPDATE_HOST_PARAMS EXT_CC_UPDATE_HOST_PARAMS_OS
#define EXT_CC_UPDATE_RISC_PARAMS EXT_CC_UPDATE_RISC_PARAMS_OS
#define EXT_CC_READ_NVRAM EXT_CC_READ_NVRAM_OS
#define EXT_CC_UPDATE_NVRAM EXT_CC_UPDATE_NVRAM_OS
#define EXT_CC_HOST_IDX EXT_CC_HOST_IDX_OS
#define EXT_CC_LOOPBACK EXT_CC_LOOPBACK_OS
#define EXT_CC_READ_OPTION_ROM EXT_CC_READ_OPTION_ROM_OS
#define EXT_CC_READ_OPTION_ROM_EX EXT_CC_READ_OPTION_ROM_EX_OS
#define EXT_CC_UPDATE_OPTION_ROM EXT_CC_UPDATE_OPTION_ROM_OS
#define EXT_CC_UPDATE_OPTION_ROM_EX EXT_CC_UPDATE_OPTION_ROM_EX_OS
#define EXT_CC_GET_VPD EXT_CC_GET_VPD_OS
#define EXT_CC_SET_VPD EXT_CC_SET_VPD_OS
#define EXT_CC_GET_FCACHE EXT_CC_GET_FCACHE_OS
#define EXT_CC_GET_FCACHE_EX EXT_CC_GET_FCACHE_EX_OS
#define EXT_CC_HOST_DRVNAME EXT_CC_HOST_DRVNAME_OS
#define EXT_CC_GET_SFP_DATA EXT_CC_GET_SFP_DATA_OS
#define EXT_CC_WWPN_TO_SCSIADDR EXT_CC_WWPN_TO_SCSIADDR_OS
#define EXT_CC_PORT_PARAM EXT_CC_PORT_PARAM_OS
#define EXT_CC_GET_PCI_DATA EXT_CC_GET_PCI_DATA_OS
#define EXT_CC_GET_FWEXTTRACE EXT_CC_GET_FWEXTTRACE_OS
#define EXT_CC_GET_FWFCETRACE EXT_CC_GET_FWFCETRACE_OS
#define EXT_CC_GET_VP_CNT_ID EXT_CC_GET_VP_CNT_ID_OS
#define EXT_CC_VPORT_CMD EXT_CC_VPORT_CMD_OS
#define EXT_CC_ACCESS_FLASH EXT_CC_ACCESS_FLASH_OS
#define EXT_CC_RESET_FW EXT_CC_RESET_FW_OS
#define EXT_CC_I2C_DATA EXT_CC_I2C_DATA_OS
#define EXT_CC_DUMP EXT_CC_DUMP_OS
#define EXT_CC_SERDES_REG_OP EXT_CC_SERDES_REG_OP_OS
#define EXT_CC_VF_STATE EXT_CC_VF_STATE_OS
#define EXT_CC_SERDES_REG_OP_EX EXT_CC_SERDES_REG_OP_EX_OS
#define EXT_CC_SEND_ELS_PASSTHRU EXT_CC_ELS_PASSTHRU_OS
#define EXT_CC_FLASH_UPDATE_CAPS EXT_CC_FLASH_UPDATE_CAPS_OS
#define EXT_CC_GET_BBCR_DATA EXT_CC_GET_BBCR_DATA_OS
#define EXT_CC_GET_DATA EXT_CC_GET_DATA_OS
#define EXT_CC_SET_DATA EXT_CC_SET_DATA_OS
#define EXT_CC_SEND_ELS_RTIN EXT_CC_SEND_ELS_RTIN_OS
#define EXT_SC_QUERY_HBA_NODE 1
#define EXT_SC_QUERY_HBA_PORT 2
#define EXT_SC_QUERY_DISC_PORT 3
#define EXT_SC_QUERY_DISC_TGT 4
#define EXT_SC_QUERY_DISC_LUN 5
#define EXT_SC_QUERY_DRIVER 6
#define EXT_SC_QUERY_FW 7
#define EXT_SC_QUERY_CHIP 8
#define EXT_SC_QUERY_CNA_PORT 9
#define EXT_SC_QUERY_ADAPTER_VERSIONS 10
#define EXT_SC_GET_SCSI_ADDR 1
#define EXT_SC_GET_ERR_DETECTIONS 2
#define EXT_SC_GET_STATISTICS 3
#define EXT_SC_GET_BUS_MODE 4
#define EXT_SC_GET_DR_DUMP_BUF 5
#define EXT_SC_GET_RISC_CODE 6
#define EXT_SC_GET_FLASH_RAM 7
#define EXT_SC_GET_BEACON_STATE 8
#define EXT_SC_GET_DCBX_PARAM 9
#define EXT_SC_GET_FCF_LIST 10
#define EXT_SC_GET_RESOURCE_CNTS 11
#define EXT_SC_GET_PRIV_STATS 12
#define EXT_SC_GET_LINK_STATUS 101
#define EXT_SC_GET_LOOP_ID 102
#define EXT_SC_GET_LUN_BITMASK 103
#define EXT_SC_GET_PORT_DATABASE 104
#define EXT_SC_GET_PORT_DATABASE_MEM 105
#define EXT_SC_GET_PORT_SUMMARY 106
#define EXT_SC_GET_POSITION_MAP 107
#define EXT_SC_GET_RETRY_CNT 108
#define EXT_SC_GET_RNID 109
#define EXT_SC_GET_RTIN 110
#define EXT_SC_GET_FC_LUN_BITMASK 111
#define EXT_SC_GET_FC_STATISTICS 112
#define EXT_SC_GET_FC4_STATISTICS 113
#define EXT_SC_GET_TARGET_ID 114
#define EXT_SC_GET_SEL_TIMEOUT 201
#define EXT_DEF_DCBX_PARAM_BUF_SIZE 4096
#define EXT_SC_RST_STATISTICS 3
#define EXT_SC_SET_BUS_MODE 4
#define EXT_SC_SET_DR_DUMP_BUF 5
#define EXT_SC_SET_RISC_CODE 6
#define EXT_SC_SET_FLASH_RAM 7
#define EXT_SC_SET_BEACON_STATE 8
#define EXT_SC_SET_PARMS 99
#define EXT_SC_SET_LUN_BITMASK 103
#define EXT_SC_SET_RETRY_CNT 108
#define EXT_SC_SET_RNID 109
#define EXT_SC_SET_RTIN 110
#define EXT_SC_SET_FC_LUN_BITMASK 111
#define EXT_SC_ADD_TARGET_DEVICE 112
#define EXT_SC_SWAP_TARGET_DEVICE 113
#define EXT_SC_SET_SEL_TIMEOUT 201
#define EXT_SC_SEND_SCSI_PASSTHRU 0
#define EXT_SC_SEND_FC_SCSI_PASSTHRU 1
#define EXT_SC_NVRAM_HARDWARE 0
#define EXT_SC_NVRAM_DRIVER 1
#define EXT_SC_NVRAM_ALL 2
#define EXT_VF_SC_VPORT_GETINFO 1
#define EXT_VF_SC_VPORT_DELETE 2
#define EXT_VF_SC_VPORT_MODIFY 3
#define EXT_VF_SC_VPORT_CREATE 4
#define EXT_SC_FLASH_READ 0
#define EXT_SC_FLASH_WRITE 1
#define EXT_SC_RESET_FC_FW 1
#define EXT_SC_RESET_MPI_FW 2
#define EXT_SC_GET_BOARD_TEMP 1
#define EXT_SC_DUMP_SIZE 1
#define EXT_SC_DUMP_READ 2
#define EXT_SC_DUMP_TRIGGER 3
#define EXT_SC_READ_SERDES_REG 1
#define EXT_SC_WRITE_SERDES_REG 2
#define EXT_SC_GET_FLASH_UPDATE_CAPS 1
#define EXT_SC_SET_FLASH_UPDATE_CAPS 2
typedef struct _EXT_HBA_NODE {
UINT32 DriverAttr;
UINT32 FWAttr;
UINT16 PortCount;
UINT16 InterfaceType;
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Manufacturer[EXT_DEF_MAX_STR_SIZE];
UINT8 Model[EXT_DEF_MAX_STR_SIZE];
UINT8 SerialNum[EXT_DEF_SERIAL_NUM_SIZE];
UINT8 DriverVersion[EXT_DEF_MAX_STR_SIZE];
UINT8 FWVersion[EXT_DEF_MAX_STR_SIZE];
UINT8 OptRomVersion[EXT_DEF_MAX_STR_SIZE];
UINT8 MpiVersion[4];
UINT8 PepFwVersion[4];
UINT8 Reserved[24];
} EXT_HBA_NODE, *PEXT_HBA_NODE;
#define EXT_DEF_FC_INTF_TYPE 1
#define EXT_DEF_SCSI_INTF_TYPE 2
#define EXT_DEF_VIRTUAL_FC_INTF_TYPE 3
typedef struct _EXT_HBA_PORT {
UINT64 Target;
UINT32 PortSupportedSpeed;
UINT32 PortSpeed;
UINT16 Type;
UINT16 State;
UINT16 Mode;
UINT16 DiscPortCount;
UINT16 DiscPortNameType;
UINT16 DiscTargetCount;
UINT16 Bus;
UINT16 Lun;
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
UINT8 PortSupportedFC4Types;
UINT8 PortActiveFC4Types;
UINT8 FabricName[EXT_DEF_WWN_NAME_SIZE];
UINT16 LinkState2;
UINT16 LinkState3;
UINT16 LinkState1;
UINT16 LinkState6;
UINT8 Reserved[2];
} EXT_HBA_PORT, *PEXT_HBA_PORT;
typedef struct _EXT_HBA_FC4Statistics {
INT64 InputRequests;
INT64 OutputRequests;
INT64 ControlRequests;
INT64 InputMegabytes;
INT64 OutputMegabytes;
UINT64 Reserved[6];
} EXT_HBA_FC4STATISTICS, *PEXT_HBA_FC4STATISTICS;
typedef struct _EXT_LOOPBACK_REQ {
UINT32 TransferCount;
UINT32 IterationCount;
UINT32 BufferAddress;
UINT32 BufferLength;
UINT16 Options;
UINT8 Reserved[18];
} EXT_LOOPBACK_REQ, *PEXT_LOOPBACK_REQ;
typedef struct _EXT_LOOPBACK_RSP {
UINT64 BufferAddress;
UINT32 BufferLength;
UINT32 IterationCountLastError;
UINT16 CompletionStatus;
UINT16 CrcErrorCount;
UINT16 DisparityErrorCount;
UINT16 FrameLengthErrorCount;
UINT8 CommandSent;
UINT8 Reserved[15];
} EXT_LOOPBACK_RSP, *PEXT_LOOPBACK_RSP;
#define INT_DEF_LB_LOOPBACK_CMD 0
#define INT_DEF_LB_ECHO_CMD 1
#define EXT_DEF_LB_COMPLETE 0x4000
#define EXT_DEF_LB_PARAM_ERR 0x4006
#define EXT_DEF_LB_LOOP_DOWN 0x400b
#define EXT_DEF_LB_CMD_ERROR 0x400c
#define EXT_DEF_INITIATOR_DEV 0x1
#define EXT_DEF_TARGET_DEV 0x2
#define EXT_DEF_TAPE_DEV 0x4
#define EXT_DEF_FABRIC_DEV 0x8
#define EXT_DEF_HBA_OK 0
#define EXT_DEF_HBA_SUSPENDED 1
#define EXT_DEF_HBA_LOOP_DOWN 2
#define EXT_DEF_UNKNOWN_MODE 0
#define EXT_DEF_P2P_MODE 1
#define EXT_DEF_LOOP_MODE 2
#define EXT_DEF_FL_MODE 3
#define EXT_DEF_N_MODE 4
#define EXT_DEF_USE_NODE_NAME 1
#define EXT_DEF_USE_PORT_NAME 2
#define EXT_DEF_FC4_TYPE_SCSI 0x1
#define EXT_DEF_FC4_TYPE_IP 0x2
#define EXT_DEF_FC4_TYPE_SCTP 0x4
#define EXT_DEF_FC4_TYPE_VI 0x8
#define IIDMA_RATE_1GB 0x0
#define IIDMA_RATE_2GB 0x1
#define IIDMA_RATE_4GB 0x3
#define IIDMA_RATE_8GB 0x4
#define IIDMA_RATE_10GB 0x13
#define IIDMA_RATE_16GB 0x5
#define IIDMA_RATE_32GB 0x6
#define IIDMA_RATE_UNKNOWN 0xffff
#define IIDMA_MODE_0 0
#define IIDMA_MODE_1 1
#define IIDMA_MODE_2 2
#define IIDMA_MODE_3 3
#define EXT_DEF_PORTSPEED_UNKNOWN 0x0
#define EXT_DEF_PORTSPEED_1GBIT 0x1
#define EXT_DEF_PORTSPEED_2GBIT 0x2
#define EXT_DEF_PORTSPEED_4GBIT 0x4
#define EXT_DEF_PORTSPEED_8GBIT 0x8
#define EXT_DEF_PORTSPEED_10GBIT 0x10
#define EXT_DEF_PORTSPEED_16GBIT 0x20
#define EXT_DEF_PORTSPEED_32GBIT 0x40
#define EXT_PORTSPEED_NOT_NEGOTIATED (1<<15)
typedef struct _EXT_DISC_PORT {
UINT64 TargetId;
UINT16 Type;
UINT16 Status;
UINT16 Bus;
UINT16 LoopID;
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
UINT8 Local;
UINT8 Reserved[27];
} EXT_DISC_PORT, *PEXT_DISC_PORT;
typedef struct _EXT_DISC_TARGET {
UINT64 TargetId;
UINT16 Type;
UINT16 Status;
UINT16 Bus;
UINT16 LunCount;
UINT16 LoopID;
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
UINT8 Local;
UINT8 Reserved[25];
} EXT_DISC_TARGET, *PEXT_DISC_TARGET;
typedef struct _EXT_DISC_LUN {
UINT16 Id;
UINT16 State;
UINT16 IoCount;
UINT8 Reserved[30];
} EXT_DISC_LUN, *PEXT_DISC_LUN;
typedef struct _EXT_SCSI_ADDR {
UINT64 Target;
UINT16 Bus;
UINT16 Lun;
UINT8 Padding[12];
} EXT_SCSI_ADDR, *PEXT_SCSI_ADDR;
typedef struct _EXT_FC_ADDR {
UINT16 Type;
union {
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
} FcAddr;
UINT8 Padding[4];
} EXT_FC_ADDR, *PEXT_FC_ADDR;
#define EXT_DEF_TYPE_WWNN 1
#define EXT_DEF_TYPE_WWPN 2
#define EXT_DEF_TYPE_PORTID 3
#define EXT_DEF_TYPE_FABRIC 4
typedef struct _EXT_DEST_ADDR {
union {
struct {
UINT64 Target;
UINT16 Bus;
UINT8 pad[6];
} ScsiAddr;
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
} DestAddr;
UINT16 DestType;
UINT16 Lun;
UINT8 Padding[4];
} EXT_DEST_ADDR, *PEXT_DEST_ADDR;
#define EXT_DEF_DESTTYPE_WWNN 1
#define EXT_DEF_DESTTYPE_WWPN 2
#define EXT_DEF_DESTTYPE_PORTID 3
#define EXT_DEF_DESTTYPE_FABRIC 4
#define EXT_DEF_DESTTYPE_SCSI 5
typedef struct _EXT_HBA_PORT_STAT {
UINT32 ControllerErrorCount;
UINT32 DeviceErrorCount;
UINT32 IoCount;
UINT32 MBytesCount;
UINT32 LipResetCount;
UINT32 InterruptCount;
UINT32 LinkFailureCount;
UINT32 LossOfSyncCount;
UINT32 LossOfSignalsCount;
UINT32 PrimitiveSeqProtocolErrorCount;
UINT32 InvalidTransmissionWordCount;
UINT32 InvalidCRCCount;
UINT8 Reserved[64];
} EXT_HBA_PORT_STAT, *PEXT_HBA_PORT_STAT;
typedef struct _EXT_DRIVER {
UINT32 MaxTransferLen;
UINT32 MaxDataSegments;
UINT32 Attrib;
UINT32 InternalFlags[4];
UINT16 NumOfBus;
UINT16 TargetsPerBus;
UINT16 LunsPerTarget;
UINT16 DmaBitAddresses;
UINT16 IoMapType;
UINT8 Version[EXT_DEF_MAX_STR_SIZE];
UINT8 Reserved[32];
} EXT_DRIVER, *PEXT_DRIVER;
typedef struct _EXT_FW {
UINT32 Attrib;
UINT8 Version[EXT_DEF_MAX_STR_SIZE];
UINT8 Reserved[66];
} EXT_FW, *PEXT_FW;
typedef struct _EXT_CHIP {
UINT32 IoAddr;
UINT32 IoAddrLen;
UINT32 MemAddr;
UINT32 MemAddrLen;
UINT16 VendorId;
UINT16 DeviceId;
UINT16 SubVendorId;
UINT16 SubSystemId;
UINT16 PciBusNumber;
UINT16 PciSlotNumber;
UINT16 ChipType;
UINT16 InterruptLevel;
UINT16 OutMbx[8];
UINT16 FuncNo;
UINT8 Reserved[29];
UINT8 ChipRevID;
} EXT_CHIP, *PEXT_CHIP;
typedef struct _EXT_CNA_PORT {
UINT16 VLanId;
UINT8 VNPortMACAddress[EXT_DEF_MAC_ADDRESS_SIZE];
UINT16 FabricParam;
UINT16 Reserved0;
UINT32 Reserved[29];
} EXT_CNA_PORT, *PEXT_CNA_PORT;
#define EXT_DEF_MAC_ADDR_MODE_FPMA 0x8000
#define NO_OF_VERSIONS 2
#define FLASH_VERSION 0
#define RUNNING_VERSION 1
#define EXT_OPT_ROM_REGION_MPI_RISC_FW 0x40
#define EXT_OPT_ROM_REGION_EDC_PHY_FW 0x45
typedef struct _EXT_REGIONVERSION {
UINT16 Region;
UINT16 SubRegion;
UINT16 Location;
UINT16 VersionLength;
UINT8 Version[8];
UINT8 Reserved[8];
} EXT_REGIONVERSION, *PEXT_REGIONVERSION;
typedef struct _EXT_ADAPTERREGIONVERSION {
UINT32 Length;
UINT32 Reserved;
EXT_REGIONVERSION RegionVersion[1];
} EXT_ADAPTERREGIONVERSION, *PEXT_ADAPTERREGIONVERSION;
typedef struct _EXT_RNID_REQ {
EXT_FC_ADDR Addr;
UINT8 DataFormat;
UINT8 Pad;
UINT8 OptWWN[EXT_DEF_WWN_NAME_SIZE];
UINT8 OptPortId[EXT_DEF_PORTID_SIZE];
UINT8 Reserved[51];
} EXT_RNID_REQ, *PEXT_RNID_REQ;
#define EXT_DEF_RNID_DFORMAT_NONE 0
#define EXT_DEF_RNID_DFORMAT_TOPO_DISC 0xDF
typedef struct _EXT_SET_RNID_REQ {
UINT8 IPVersion[2];
UINT8 UDPPortNumber[2];
UINT8 IPAddress[16];
UINT8 Reserved[64];
} EXT_SET_RNID_REQ, *PEXT_SET_RNID_REQ;
#define SEND_RNID_RSP_SIZE 72
typedef struct _RNID_DATA
{
UINT32 UnitType;
UINT32 NumOfAttachedNodes;
UINT16 TopoDiscFlags;
UINT16 Reserved;
UINT8 WWN[16];
UINT8 PortId[4];
UINT8 IPVersion[2];
UINT8 UDPPortNumber[2];
UINT8 IPAddress[16];
} EXT_RNID_DATA, *PEXT_RNID_DATA;
typedef struct _EXT_SCSI_PASSTHRU {
EXT_SCSI_ADDR TargetAddr;
UINT8 Direction;
UINT8 CdbLength;
UINT8 Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH];
UINT8 Reserved[62];
UINT8 SenseData[256];
} EXT_SCSI_PASSTHRU, *PEXT_SCSI_PASSTHRU;
typedef struct _EXT_FC_SCSI_PASSTHRU {
EXT_DEST_ADDR FCScsiAddr;
UINT8 Direction;
UINT8 CdbLength;
UINT8 Cdb[EXT_DEF_SCSI_PASSTHRU_CDB_LENGTH];
UINT8 Reserved[60];
UINT8 SenseData[256];
} EXT_FC_SCSI_PASSTHRU, *PEXT_FC_SCSI_PASSTHRU;
#define EXT_DEF_SCSI_PASSTHRU_DATA_IN 1
#define EXT_DEF_SCSI_PASSTHRU_DATA_OUT 2
typedef struct _EXT_REG_AEN {
UINT32 Enable;
UINT8 Reserved[4];
} EXT_REG_AEN, *PEXT_REG_AEN;
typedef struct _EXT_ASYNC_EVENT {
UINT32 AsyncEventCode;
union {
struct {
UINT8 RSCNInfo[EXT_DEF_PORTID_SIZE_ACTUAL];
UINT8 AddrFormat;
UINT8 Rsvd_1[8];
} RSCN;
UINT8 Reserved[12];
} Payload;
} EXT_ASYNC_EVENT, *PEXT_ASYNC_EVENT;
#define EXT_DEF_LIP_OCCURRED 0x8010
#define EXT_DEF_LINK_UP 0x8011
#define EXT_DEF_LINK_DOWN 0x8012
#define EXT_DEF_LIP_RESET 0x8013
#define EXT_DEF_RSCN 0x8015
#define EXT_DEF_DEVICE_UPDATE 0x8014
#define EXT_DEF_DPORT_DIAGS 0x8080
#define EXT_DEF_GRN_BLINK_OFF 0x00
#define EXT_DEF_GRN_BLINK_ON 0x01
typedef struct _EXT_BEACON_CONTROL {
UINT32 State;
UINT8 Reserved[12];
} EXT_BEACON_CONTROL, *PEXT_BEACON_CONTROL;
#define EXT_DEF_MAX_AEN_QUEUE EXT_DEF_MAX_AEN_QUEUE_OS
typedef struct _EXT_LUN_BIT_MASK {
#if ((EXT_DEF_NON_SCSI3_MAX_LUN & 0x7) == 0)
UINT8 mask[EXT_DEF_NON_SCSI3_MAX_LUN >> 3];
#else
UINT8 mask[(EXT_DEF_NON_SCSI3_MAX_LUN + 8) >> 3 ];
#endif
} EXT_LUN_BIT_MASK, *PEXT_LUN_BIT_MASK;
#define EXT_DEF_GET_KNOWN_DEVICE 0x1
#define EXT_DEF_GET_VISIBLE_DEVICE 0x2
#define EXT_DEF_GET_HIDDEN_DEVICE 0x4
#define EXT_DEF_GET_FABRIC_DEVICE 0x8
#define EXT_DEF_GET_LOOP_DEVICE 0x10
typedef struct _EXT_DEVICEDATAENTRY
{
EXT_SCSI_ADDR TargetAddress;
UINT32 DeviceFlags;
UINT16 LoopID;
UINT16 BaseLunNumber;
UINT8 NodeWWN[8];
UINT8 PortWWN[8];
UINT8 PortID[3];
UINT8 ControlFlags;
UINT8 Reserved[132];
} EXT_DEVICEDATAENTRY, *PEXT_DEVICEDATAENTRY;
#define EXT_DEF_EXTERNAL_LUN_COUNT 2048
#define EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES (EXT_DEF_EXTERNAL_LUN_COUNT / 8)
typedef struct _EXT_EXTERNAL_LUN_BITMASK_ENTRY
{
UINT8 NodeName[EXT_DEF_WWN_NAME_SIZE];
UINT8 PortName[EXT_DEF_WWN_NAME_SIZE];
UINT8 Reserved1[16];
UINT8 Bitmask[EXT_DEF_EXTERNAL_LUN_BITMASK_BYTES];
} EXT_EXTERNAL_LUN_BITMASK_ENTRY, *PEXT_EXTERNAL_LUN_BITMASK_ENTRY;
typedef struct _LUN_BITMASK_LIST
{
UINT16 Version;
UINT16 EntryCount;
UINT8 Reserved[28];
EXT_EXTERNAL_LUN_BITMASK_ENTRY
BitmaskEntry[1];
} EXT_LUN_BITMASK_LIST, *PEXT_LUN_BITMASK_LIST;
typedef struct _EXT_DEVICEDATA
{
UINT32 TotalDevices;
UINT32 ReturnListEntryCount;
EXT_DEVICEDATAENTRY EntryList[1];
} EXT_DEVICEDATA, *PEXT_DEVICEDATA;
typedef struct _EXT_SWAPTARGETDEVICE
{
EXT_DEVICEDATAENTRY CurrentExistDevice;
EXT_DEVICEDATAENTRY NewDevice;
} EXT_SWAPTARGETDEVICE, *PEXT_SWAPTARGETDEVICE;
#define EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES 1
#define EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES 256
#ifdef _WIN64
#define EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE 32
#else
#define EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE \
offsetof(LUN_BITMASK_LIST_BUFFER, asBitmaskEntry)
#endif
#define EXT_DEF_LUN_BITMASK_LIST_MIN_SIZE \
(EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE + \
(sizeof (EXT_EXTERNAL_LUN_BITMASK_ENTRY) * \
EXT_DEF_LUN_BITMASK_LIST_MIN_ENTRIES))
#define EXT_DEF_LUN_BITMASK_LIST_MAX_SIZE \
(EXT_DEF_LUN_BITMASK_LIST_HEADER_SIZE + \
(sizeof (EXT_EXTERNAL_LUN_BITMASK_ENTRY) * \
EXT_DEF_LUN_BITMASK_LIST_MAX_ENTRIES))
#define EXT_IS_LUN_BIT_SET(P, L) \
(((P)->mask[L / 8] & (0x80 >> (L % 8))) ? 1 : 0)
#define EXT_SET_LUN_BIT(P, L) \
((P)->mask[L / 8] |= (0x80 >> (L % 8)))
#define EXT_CLR_LUN_BIT(P, L) \
((P)->mask[L / 8] &= ~(0x80 >> (L % 8)))
typedef struct _EXT_PORT_PARAM {
EXT_DEST_ADDR FCScsiAddr;
UINT16 Mode;
UINT16 Speed;
} EXT_PORT_PARAM, *PEXT_PORT_PARAM;
#define EXT_IIDMA_MODE_GET 0
#define EXT_IIDMA_MODE_SET 1
typedef struct _PCI_HEADER_T {
UINT8 signature[2];
UINT8 reserved[0x16];
UINT8 dataoffset[2];
UINT8 pad[6];
} PCI_HEADER_T, *PPCI_HEADER_T;
typedef struct _PCI_DATA_T {
UINT8 signature[4];
UINT8 vid[2];
UINT8 did[2];
UINT8 reserved0[2];
UINT8 pcidatalen[2];
UINT8 pcidatarev;
UINT8 classcode[3];
UINT8 imagelength[2];
UINT8 revisionlevel[2];
UINT8 codetype;
UINT8 indicator;
UINT8 reserved1[2];
UINT8 pad[8];
} PCI_DATA_T, *PPCI_DATA_T;
#define MENLO_RESET_FLAG_ENABLE_DIAG_FW 1
typedef struct _EXT_MENLO_RESET {
UINT16 Flags;
UINT16 Reserved;
} EXT_MENLO_RESET, *PEXT_MENLO_RESET;
typedef struct _EXT_MENLO_GET_FW_VERSION {
UINT32 FwVersion;
} EXT_MENLO_GET_FW_VERSION, *PEXT_MENLO_GET_FW_VERSION;
#define MENLO_UPDATE_FW_FLAG_DIAG_FW 0x0008
typedef struct _EXT_MENLO_UPDATE_FW {
UINT64 pFwDataBytes;
UINT32 TotalByteCount;
UINT16 Flags;
UINT16 Reserved;
} EXT_MENLO_UPDATE_FW, *PEXT_MENLO_UPDATE_FW;
#define CONFIG_PARAM_ID_RESERVED 1
#define CONFIG_PARAM_ID_UIF 2
#define CONFIG_PARAM_ID_FCOE_COS 3
#define CONFIG_PARAM_ID_PAUSE_TYPE 4
#define CONFIG_PARAM_ID_TIMEOUTS 5
#define INFO_DATA_TYPE_CONFIG_LOG_DATA 1
#define INFO_DATA_TYPE_LOG_DATA 2
#define INFO_DATA_TYPE_PORT_STATISTICS 3
#define INFO_DATA_TYPE_LIF_STATISTICS 4
#define INFO_DATA_TYPE_ASIC_STATISTICS 5
#define INFO_DATA_TYPE_CONFIG_PARAMETERS 6
#define INFO_DATA_TYPE_PANIC_LOG 7
#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
typedef struct _EXT_MENLO_ACCESS_PARAMETERS {
union {
struct {
UINT32 StartingAddr;
UINT32 Reserved2;
UINT32 Reserved3;
} MenloMemory;
struct {
UINT32 ConfigParamID;
UINT32 ConfigParamData0;
UINT32 ConfigParamData1;
} MenloConfig;
struct {
UINT32 InfoDataType;
UINT32 InfoContext;
UINT32 Reserved;
} MenloInfo;
} ap;
} EXT_MENLO_ACCESS_PARAMETERS, *PEXT_MENLO_ACCESS_PARAMETERS;
#define INFO_DATA_TYPE_LOG_CONFIG_TBC ((10 * 7) + 1) * 4
#define INFO_DATA_TYPE_PORT_STAT_ETH_TBC 0x194
#define INFO_DATA_TYPE_PORT_STAT_FC_TBC 0xC0
#define INFO_DATA_TYPE_LIF_STAT_TBC 0x40
#define INFO_DATA_TYPE_ASIC_STAT_TBC 0x5F8
#define INFO_DATA_TYPE_CONFIG_TBC 0x140
#define MENLO_OP_READ_MEM 0
#define MENLO_OP_WRITE_MEM 1
#define MENLO_OP_CHANGE_CONFIG 2
#define MENLO_OP_GET_INFO 3
typedef struct _EXT_MENLO_MANAGE_INFO {
UINT64 pDataBytes;
EXT_MENLO_ACCESS_PARAMETERS Parameters;
UINT32 TotalByteCount;
UINT16 Operation;
UINT16 Reserved;
} EXT_MENLO_MANAGE_INFO, *PEXT_MENLO_MANAGE_INFO;
#define MENLO_FC_CHECKSUM_FAILURE 0x01
#define MENLO_FC_INVALID_LENGTH 0x02
#define MENLO_FC_INVALID_ADDRESS 0x04
#define MENLO_FC_INVALID_CONFIG_ID_TYPE 0x05
#define MENLO_FC_INVALID_CONFIG_DATA 0x06
#define MENLO_FC_INVALID_INFO_CONTEXT 0x07
typedef struct _EXT_MENLO_MGT {
union {
EXT_MENLO_RESET MenloReset;
EXT_MENLO_GET_FW_VERSION MenloGetFwVer;
EXT_MENLO_UPDATE_FW MenloUpdateFw;
EXT_MENLO_MANAGE_INFO MenloManageInfo;
} sp;
} EXT_MENLO_MGT, *PEXT_MENLO_MGT;
typedef enum vport_options {
EXT_VPO_LOGIN_RETRY_ENABLE = 0,
EXT_VPO_PERSISTENT = 1,
EXT_VPO_QOS_BW = 2,
EXT_VPO_VFABRIC_ENABLE = 3
} vport_options_t;
#define MAX_DEV_PATH 256
#define MAX_VP_ID 256
#define EXT_OLD_VPORT_ID_CNT_SIZE 260
typedef struct _EXT_VPORT_ID_CNT {
UINT32 VpCnt;
UINT8 VpId[MAX_VP_ID];
UINT8 vp_path[MAX_VP_ID][MAX_DEV_PATH];
INT32 VpDrvInst[MAX_VP_ID];
} EXT_VPORT_ID_CNT, *PEXT_VPORT_ID_CNT;
typedef struct _EXT_VPORT_PARAMS {
UINT32 vp_id;
vport_options_t options;
UINT8 wwpn[EXT_DEF_WWN_NAME_SIZE];
UINT8 wwnn[EXT_DEF_WWN_NAME_SIZE];
} EXT_VPORT_PARAMS, *PEXT_VPORT_PARAMS;
typedef struct _EXT_VPORT_INFO {
UINT32 free;
UINT32 used;
UINT32 id;
UINT32 state;
UINT32 bound;
UINT8 wwnn[EXT_DEF_WWN_NAME_SIZE];
UINT8 wwpn[EXT_DEF_WWN_NAME_SIZE];
UINT8 reserved[220];
} EXT_VPORT_INFO, *PEXT_VPORT_INFO;
typedef struct _EXT_BOARD_TEMP {
UINT16 IntTemp;
UINT16 FracTemp;
UINT8 Reserved[60];
} EXT_BOARD_TEMP, *PEXT_BOARD_TEMP;
#define EXT_DEF_ASIC_TEMP_COMMAND_COMPLETE 0x4000
#define EXT_DEF_ASIC_TEMP_HOST_INT_ERR 0x4002
#define EXT_DEF_ASIC_TEMP_COMMAND_ERR 0x4005
#define EXT_DEF_ASIC_TEMP_COMMAND_PARAM_ERR 0x4006
typedef struct _EXT_SERDES_REG {
UINT16 addr;
UINT16 val;
} EXT_SERDES_REG, *PEXT_SERDES_REG;
typedef struct _EXT_VF_STATE {
UINT32 NoOfVFConfigured;
UINT32 NoOfVFActive;
} EXT_VF_STATE, *PEXT_VF_STATE;
typedef struct _EXT_SERDES_REG_EX {
UINT32 addr;
UINT32 val;
} EXT_SERDES_REG_EX, *PEXT_SERDES_REG_EX;
#define EXT_DEF_FCF_LIST_SIZE 4096
#define FCF_INFO_RETURN_ALL 0
#define FCF_INFO_RETURN_ONE 1
typedef struct _EXT_FCF_INFO {
UINT16 CntrlFlags;
UINT16 FcfId;
UINT16 VlanId;
UINT16 FcfFlags;
UINT16 FcfAdvertPri;
UINT16 FcfMacAddr1;
UINT16 FcfMacAddr2;
UINT16 FcfMacAddr3;
UINT16 FcfMapHi;
UINT16 FcfMapLow;
UINT8 SwitchName[8];
UINT8 FabricName[8];
UINT8 Reserved1[8];
UINT16 CommFeatures;
UINT16 Reserved2;
UINT32 RATovVal;
UINT32 EDTovVal;
UINT8 Reserved3[8];
} EXT_FCF_INFO, *PEXT_FCF_INFO;
typedef struct _EXT_FCF_LIST {
UINT32 Options;
UINT32 FcfIndex;
UINT32 BufSize;
EXT_FCF_INFO pFcfInfo[1];
} EXT_FCF_LIST, *PEXT_FCF_LIST;
typedef struct _EXT_RESOURCE_CNTS {
UINT32 OrgTgtXchgCtrlCnt;
UINT32 CurTgtXchgCtrlCnt;
UINT32 CurXchgCtrlCnt;
UINT32 OrgXchgCtrlCnt;
UINT32 CurIocbBufCnt;
UINT32 OrgIocbBufCnt;
UINT32 NoOfSupVPs;
UINT32 NoOfSupFCFs;
} EXT_RESOURCE_CNTS, *PEXT_RESOURCE_CNTS;
#define FW_FCE_SIZE (0x4000 * 4)
typedef struct _EXT_FW_FCE_TRACE {
UINT16 Registers[32];
UINT8 TraceData[FW_FCE_SIZE];
} EXT_FW_FCE_TRACE, *PEXT_FW_FCE_TRACE;
#define EXT_DEF_WWPN_VALID 1
#define EXT_DEF_WWNN_VALID 2
#define EXT_DEF_PID_VALID 4
typedef struct _EXT_ELS_PT_REQ {
UINT16 ValidMask;
UINT8 WWNN[EXT_DEF_WWN_NAME_SIZE];
UINT8 WWPN[EXT_DEF_WWN_NAME_SIZE];
UINT8 Id[EXT_DEF_PORTID_SIZE];
UINT8 Reserved[10];
} EXT_ELS_PT_REQ, *PEXT_ELS_PT_REQ;
typedef struct _EXT_FLASH_UPDATE_CAPS {
UINT64 Capabilities;
UINT32 OutageDuration;
UINT8 Reserved[20];
} EXT_FLASH_UPDATE_CAPS, *PEXT_FLASH_UPDATE_CAPS;
#define EXT_DEF_BBCR_STATUS_DISABLED 0
#define EXT_DEF_BBCR_STATUS_ENABLED 1
#define EXT_DEF_BBCR_STATUS_UNKNOWN 2
#define EXT_DEF_BBCR_STATE_OFFLINE 0
#define EXT_DEF_BBCR_STATE_ONLINE 1
#define EXT_DEF_BBCR_REASON_PORT_SPEED 1
#define EXT_DEF_BBCR_REASON_PEER_PORT 2
#define EXT_DEF_BBCR_REASON_SWITCH 3
#define EXT_DEF_BBCR_REASON_LOGIN_REJECT 4
typedef struct _EXT_BBCR_DATA {
UINT8 Status;
UINT8 State;
UINT8 ConfiguredBBSCN;
UINT8 NegotiatedBBSCN;
UINT8 OfflineReasonCode;
UINT16 mbx1;
UINT8 Reserved[9];
} EXT_BBCR_DATA, *PEXT_BBCR_DATA;
#ifdef __cplusplus
}
#endif
#endif