#ifndef _SYS_NVME_WDC_SN840_H
#define _SYS_NVME_WDC_SN840_H
#include <sys/debug.h>
#include <sys/stdint.h>
#include <sys/debug.h>
#ifdef __cplusplus
extern "C" {
#endif
#define WDC_SN840_DID 0x2500
typedef enum {
WDC_SN840_LOG_EOL = 0xc0,
WDC_SN840_LOG_DEV_MANAGE = 0xc2,
WDC_SN840_LOG_PCIE_SI = 0xc4,
WDC_SN840_LOG_POWER = 0xc5,
WDC_SN840_LOG_TEMP = 0xc6,
WDC_SN840_LOG_FW_ACT = 0xcb,
WDC_SN840_LOG_CCDS = 0xfa
} wdc_sn840_vul_t;
#pragma pack(1)
typedef struct {
uint8_t eol_rsvd0[76];
uint32_t eol_rbc;
uint8_t eol_rsvd1[4];
uint32_t eol_waf;
uint32_t eol_plr;
uint8_t eol_rsvd2[4];
uint32_t eol_pfc;
uint32_t eol_efc;
uint8_t eol_rss3[4];
uint32_t eol_vendor;
uint16_t eol_cust_sts;
uint16_t eol_sys_sts;
uint8_t eol_cust_state;
uint8_t eol_sys_state;
} wdc_vul_sn840_eol_t;
#ifndef __CHECKER__
CTASSERT(sizeof (wdc_vul_sn840_eol_t) == 118);
#endif
typedef enum {
WDC_SN840_VSD_ID = 0x01,
WDC_SN840_VSD_UEFI_VER = 0x02,
WDC_SN840_VSD_SBL_VER = 0x03,
WDC_SN840_VSD_DEF_USER_CAP = 0x04,
WDC_SN840_VSD_MAX_USER_CAP = 0x05,
WDC_SN840_VSD_MIN_USER_CAP = 0x06,
WDC_SN840_VSD_NAME = 0x07,
WDC_SN840_VSD_LOG_SUP = 0x08,
WDC_SN840_VSD_FEAT_SUP = 0x09,
WDC_SN840_VSD_FORM_FACTOR = 0x0a,
WDC_SN840_VSD_RESIZE_GRAN = 0x0b,
WDC_SN840_VSD_NS_ALLOC_SIZE = 0x0c,
WDC_SN840_VSD_NS_REG_AVAIL = 0x0d,
WDC_SN840_VSD_RAW_NVM = 0x0e,
WDC_SN840_VSD_PORT_CFG_STS = 0x0f,
WDC_SN840_VSD_MPN = 0x10,
WDC_SN840_VSD_SN = 0x11,
WDC_SN840_VSD_DEF_NS_ATTRS = 0x12,
WDC_SN840_VSD_GIT_DESCR = 0x13,
WDC_SN840_VSD_SMB_BL = 0x14,
WDC_SN840_VSD_CUST_ID = 0x15,
WDC_SN840_VSD_PROD_DESC = 0x16,
WDC_SN840_VSD_TMM_VER = 0x17,
WDC_SN840_VSD_THERM_THROT_STS = 0x18,
WDC_SN840_VSD_ASSERT_DUMP = 0x19,
WDC_SN840_VSD_CUST_EOL_STS = 0x1a,
WDC_SN840_VSD_IFS_EOL_STS = 0x1b,
WDC_SN840_VSD_CUST_EOL_STATE = 0x1c,
WDC_SN840_VSD_IFS_EOL_STATE = 0x1d,
WDC_SN840_VSD_FCR = 0x1e,
WDC_SN840_VSD_VCA_BPC_REV = 0x1f,
WDC_SN840_VSD_VCA_BPC_MIN_REV = 0x20,
WDC_SN840_VSD_VCA_BPC_RST_SEQ = 0x21,
WDC_SN840_VSD_VCA_TPC_RST_SEQ = 0x22,
WDC_SN840_VSD_VCA_TPC_FSS_SEQ = 0x23
} wdc_sn840_vsd_id_t;
typedef enum {
WDC_SN840_VSD_NS_LIDS = 0x08,
WDC_SN840_VSD_NS_FIDS = 0x09
} wdc_sn840_vsd_ns_id_t;
typedef enum {
WDC_SN840_TEMP_NAND = 0,
WDC_SN840_TEMP_BOARD,
WDC_SN840_TEMP_FE,
WDC_SN840_TEMP_FM0,
WDC_SN840_TEMP_FM1,
WDC_SN840_TEMP_AVG_NAND,
WDC_SN840_TEMP_AVG_FE,
WDC_SN840_TEMP_MAX_ASIC,
WDC_SN840_TEMP_TOUCH,
WDC_SN840_TEMP_COMP,
WDC_SN840_TEMP_NSMAPLES
} wdc_sn840_temp_sample_t;
typedef struct {
uint32_t fah_ent_no;
uint32_t fah_pow_cyc;
uint64_t fah_pow_sec;
uint64_t fah_cur_fw_ver;
uint64_t fah_new_fw_ver;
uint8_t fah_slot_no;
uint8_t fah_commit_type;
uint16_t fah_result;
uint8_t fah_rsvd[12];
} wdc_vul_sn840_fw_act_ent_t;
CTASSERT(sizeof (wdc_vul_sn840_fw_act_ent_t) == 48);
typedef struct {
uint8_t fah_hdr[4];
uint8_t fah_vers;
uint8_t fah_rsvd0;
uint8_t fah_nent;
uint8_t fah_rsvd1;
uint32_t fah_entlen;
uint32_t fah_rsvd;
} wdc_vul_sn840_fw_act_hdr_t;
CTASSERT(sizeof (wdc_vul_sn840_fw_act_hdr_t) == 16);
typedef struct {
uint8_t cbi_hdr[8];
uint32_t cbi_cust_id;
uint16_t cbi_vers_id;
uint16_t cbi_rev_id;
uint32_t cbi_build_id;
uint8_t cbi_nand_head[8];
uint32_t cbi_cust_nand_id;
uint16_t cbi_nand_vers_id;
uint16_t cbi_nand_rev_id;
} wdc_vul_sn840_ccds_info_t;
CTASSERT(sizeof (wdc_vul_sn840_ccds_info_t) == 36);
#pragma pack()
#ifdef __cplusplus
}
#endif
#endif