#ifndef _LD_PD_MAP
#define _LD_PD_MAP
#include <sys/scsi/scsi.h>
#include "fusion.h"
struct mrsas_instance;
#define WRITE_THROUGH 0
#define WRITE_BACK 1
#define READ_6 0x08
#define READ_16 0x88
#define READ_10 0x28
#define READ_12 0xA8
#define WRITE_16 0x8A
#define WRITE_10 0x2A
#define MAX_ROW_SIZE 32
#define MAX_SPAN_DEPTH 8
#define MEGASAS_LOAD_BALANCE_FLAG 0x1
#define MR_DEFAULT_IO_TIMEOUT 20
union desc_value {
U64 word;
struct {
U32 low;
U32 high;
} u1;
};
typedef struct _LD_LOAD_BALANCE_INFO
{
U8 loadBalanceFlag;
U8 reserved1;
U16 raid1DevHandle[2];
U16 scsi_pending_cmds[2];
U64 last_accessed_block[2];
} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
#pragma pack(1)
typedef struct _MR_FW_RAID_MAP_ALL {
MR_FW_RAID_MAP raidMap;
MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
} MR_FW_RAID_MAP_ALL;
typedef struct _MPI2_SCSI_IO_VENDOR_UNIQUE {
U8 nsegType;
U8 resvd0;
U16 timeoutValue;
U8 regLockFlags;
U8 reservedForHw1;
U16 ldTargetId;
U64 regLockRowLBA;
U32 regLockLength;
U16 nextLMId;
U8 extStatus;
U8 status;
U8 RAIDFlags;
U8 numSGE;
U16 configSeqNum;
U8 spanArm;
U8 resvd2[3];
} MPI2_SCSI_IO_VENDOR_UNIQUE, MPI25_SCSI_IO_VENDOR_UNIQUE;
#define RAID_CTX_SPANARM_ARM_SHIFT (0)
#define RAID_CTX_SPANARM_ARM_MASK (0x1f)
#define RAID_CTX_SPANARM_SPAN_SHIFT (5)
#define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
typedef struct _MPI2_RAID_SCSI_IO_REQUEST
{
uint16_t DevHandle;
uint8_t ChainOffset;
uint8_t Function;
uint16_t Reserved1;
uint8_t Reserved2;
uint8_t MsgFlags;
uint8_t VP_ID;
uint8_t VF_ID;
uint16_t Reserved3;
uint32_t SenseBufferLowAddress;
uint16_t SGLFlags;
uint8_t SenseBufferLength;
uint8_t Reserved4;
uint8_t SGLOffset0;
uint8_t SGLOffset1;
uint8_t SGLOffset2;
uint8_t SGLOffset3;
uint32_t SkipCount;
uint32_t DataLength;
uint32_t BidirectionalDataLength;
uint16_t IoFlags;
uint16_t EEDPFlags;
uint32_t EEDPBlockSize;
uint32_t SecondaryReferenceTag;
uint16_t SecondaryApplicationTag;
uint16_t ApplicationTagTranslationMask;
uint8_t LUN[8];
uint32_t Control;
Mpi2ScsiIoCdb_t CDB;
MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext;
Mpi2SGEIOUnion_t SGL;
} MPI2_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MPI2_RAID_SCSI_IO_REQUEST,
Mpi2RaidSCSIIORequest_t, MPI2_POINTER pMpi2RaidSCSIIORequest_t;
typedef enum _REGION_TYPE {
REGION_TYPE_UNUSED = 0,
REGION_TYPE_SHARED_READ = 1,
REGION_TYPE_SHARED_WRITE = 2,
REGION_TYPE_EXCLUSIVE = 3
} REGION_TYPE;
#define DM_PATH_MAXPATH 2
#define DM_PATH_FIRSTPATH 0
#define DM_PATH_SECONDPATH 1
typedef enum _REGION_LOCK {
REGION_LOCK_BYPASS = 0,
REGION_LOCK_UNCOND_SHARED_READ = 1,
REGION_LOCK_UNCOND_SHARED_WRITE = 2,
REGION_LOCK_UNCOND_SHARED_OTHER = 3,
REGION_LOCK_UNCOND_SHARED_EXCLUSIVE = 0xFF
} REGION_LOCK;
struct mrsas_init_frame2 {
uint8_t cmd;
uint8_t reserved_0;
uint8_t cmd_status;
uint8_t reserved_1;
uint32_t reserved_2;
uint32_t context;
uint32_t pad_0;
uint16_t flags;
uint16_t reserved_3;
uint32_t data_xfer_len;
uint32_t queue_info_new_phys_addr_lo;
uint32_t queue_info_new_phys_addr_hi;
uint32_t queue_info_old_phys_addr_lo;
uint32_t queue_info_old_phys_addr_hi;
uint64_t driverversion;
uint32_t reserved_4[4];
};
#define MPI2_REQ_DESCRIPT_FLAGS_LD_IO 0x7
#define MPI2_REQ_DESCRIPT_FLAGS_MFA 0x1
#define MPI2_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
typedef struct _MR_RAID_MFA_IO_DESCRIPTOR {
uint32_t RequestFlags : 8;
uint32_t MessageAddress1 : 24;
uint32_t MessageAddress2;
} MR_RAID_MFA_IO_REQUEST_DESCRIPTOR,
*PMR_RAID_MFA_IO_REQUEST_DESCRIPTOR;
typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION
{
MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
MR_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
U64 Words;
} MRSAS_REQUEST_DESCRIPTOR_UNION;
#pragma pack()
enum {
MRSAS_SCSI_VARIABLE_LENGTH_CMD = 0x7F,
MRSAS_SCSI_SERVICE_ACTION_READ32 = 0x9,
MRSAS_SCSI_SERVICE_ACTION_WRITE32 = 0xB,
MRSAS_SCSI_ADDL_CDB_LEN = 0x18,
MRSAS_RD_WR_PROTECT = 0x20,
MRSAS_EEDPBLOCKSIZE = 512
};
#define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
#define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
U8 MR_ValidateMapInfo(MR_FW_RAID_MAP_ALL *map, PLD_LOAD_BALANCE_INFO lbInfo);
U16 MR_CheckDIF(U32, MR_FW_RAID_MAP_ALL *);
U8 MR_BuildRaidContext(struct mrsas_instance *, struct IO_REQUEST_INFO *,
MPI2_SCSI_IO_VENDOR_UNIQUE *, MR_FW_RAID_MAP_ALL *);
#endif