INB
atgep->atge_ether_addr[5] = INB(atgep, ATGE_PAR0 + 0);
atgep->atge_ether_addr[4] = INB(atgep, ATGE_PAR0 + 1);
atgep->atge_ether_addr[3] = INB(atgep, ATGE_PAR0 + 2);
atgep->atge_ether_addr[2] = INB(atgep, ATGE_PAR0 + 3);
atgep->atge_ether_addr[1] = INB(atgep, ATGE_PAR1 + 0);
atgep->atge_ether_addr[0] = INB(atgep, ATGE_PAR1 + 1);
OUTB(devc, INB(devc, FUNCTION) | 0x40, FUNCTION);
OUTB(devc, (INB(devc, FUNCTION) & ~0x40) | 0x80, FUNCTION);
OUTB(devc, (INB(devc, FUNCTION) & ~0x40) | 0x80, FUNCTION);
OUTB(devc, (INB(devc, FUNCTION) & ~0x40) | 0x80, FUNCTION);
OUTB(devc, (INB(devc, FUNCTION) & ~0x40) | 0x80, FUNCTION);
OUTB(devc, INB(devc, REC_MONITOR) | 0xF, REC_MONITOR);
OUTB(devc, INB(devc, REC_MONITOR) & ~0xF, REC_MONITOR);
while ((INB(devc, SPI_CONTROL) & 0x1) && count-- > 0) {
tmp = (INB(devc, SPI_CONTROL) & ~0x7E) | latch | 0x1;
OUTB(devc, INB(devc, CHAN_RESET)|0x10, CHAN_RESET);
OUTB(devc, INB(devc, CHAN_RESET) & ~0x10, CHAN_RESET);
OUTB(devc, (INB(devc, MULTICH_MODE) & ~0x3) | channels,
OUTB(devc, (INB(devc, PLAY_FORMAT) & ~0xC) | 0x0, PLAY_FORMAT);
OUTB(devc, INB(devc, CHAN_RESET) | (1 << devc->rec_eng.chan),
OUTB(devc, INB(devc, CHAN_RESET) & ~(1 << devc->rec_eng.chan),
OUTB(devc, (INB(devc, REC_MODE) & ~0x3) | channels, REC_MODE);
OUTB(devc, (INB(devc, REC_FORMAT) & ~0x3) | 0x0, REC_FORMAT);
bVal = INB(devc, MISC_REG);
bVal = INB(devc, FUNCTION);
if (INB(devc, devc->regs + 0x1e) & 0x80)
if (INB(devc, devc->regs + 0x1e) & 0x80)
if (INB(dev, AC97A) & 0x80)
if (INB(dev, AC97A) & 0x80)
if (INB(dev, AC97A) & 0x80)
if (INB(dev, AC97A) & 0x80)
INB(bfe, BFE_EEPROM_BASE + 79);
INB(bfe, BFE_EEPROM_BASE + 78);
INB(bfe, BFE_EEPROM_BASE + 81);
INB(bfe, BFE_EEPROM_BASE + 80);
INB(bfe, BFE_EEPROM_BASE + 83);
INB(bfe, BFE_EEPROM_BASE + 82);
INB(dp, EC1, &val, &err, usberr);
INB(dp, EC2, &lp->ec[2], &err, usberr);
INB(dp, EC0, ®0, &err, usberr);
INB(dp, EC1, ®1, &err, usberr);
INB(dp, EC2, ®2, &err, usberr);
INB(dp, PHYAC, &phyctrl, errp, usberr);
INB(dp, PHYAC, &phyctrl, errp, usberr);
INB(dp, IPHYC, &val, &err, usberr);
INB(dp, IPHYC, &val, &err, usberr);
INB(dp, 0x83, &val, &err, usberr);
INB(dp, EECTRL, &eectrl, errp, usberr);
(void) INB(sc, KCS_DATA);
data = INB(sc, KCS_DATA);
data = INB(sc, KCS_DATA);
*data = INB(sc, KCS_DATA);
(void) INB(sc, KCS_DATA);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
status = INB(sc, KCS_CTL_STS);
mcr = INB(MCR);
(INB(MSR) & DCD))
lcr = INB(LCR);
OUTB(MCR, INB(MCR) & ~ ASY_LOOP);
icr = INB(ICR);
((INB(LSR) & XSRE) == 0));
(void) INB(DAT);
(void) INB(ISR);
(void) INB(LSR);
(void) INB(MSR);
lcr = INB(LCR);
while ((INB(LSR) & XHRE) == 0) {
return ((INB(LSR) & RCA) != 0);
return (INB(DAT));
asy->polled_icr = INB(ICR);
interrupt_id = INB(ISR) & 0x0F;
lsr = INB(LSR);
(void) INB(LSR);
(void) INB(DAT);
(void) INB(MSR);
lsr = INB(LSR);
lsr = INB(LSR);
(void) (INB(DAT) & 0xff);
c = INB(DAT) & 0xff;
lsr = INB(LSR);
msr = INB(MSR); /* this resets the interrupt */
if (INB(ICR) & MIEN)
val = INB(MSR) & 0xFF;
val = INB(MCR);
lcr = INB(LCR);
val = INB(LCR);
if (INB(LSR) & XHRE) {
if (INB(LSR) & XHRE) {
while ((INB(LSR) & XSRE) == 0) {
val = INB(LCR);
val = INB(LCR);
val = INB(LCR);
val = INB(MCR);
icr = INB(ICR);
mcr_r = INB(MCR);
if (INB(ICR) & MIEN)
msr_r = INB(MSR);
mcr = INB(MCR);
if ((ss = async->async_flowc) != '\0' && (INB(LSR) & XHRE)) {
if (INB(ISR) & 0x20) { /* 82510 chip is present */
if ((INB(ISR) & 0xc0) == 0xc0)