Symbol: GRCBASE_MISC
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13989
REG_WR(cb, GRCBASE_MISC +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13993
REG_WR(cb, GRCBASE_MISC +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14303
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1675
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1678
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1751
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1755
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1866
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1870
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1896
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1900
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2016
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2166
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2664
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2669
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3631
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3633
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3670
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3672
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7317
REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
189
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
192
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
195
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
197
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2564
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,reset_reg_1_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2566
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_2_SET,reset_reg_2_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3856
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x3);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3858
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x3);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3933
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x03);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3935
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x03);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4229
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x80000000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4230
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x80000000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
632
REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
746
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
756
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, reg_2_clear);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
762
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_SET, MISC_REGISTERS_RESET_REG_1_RST_NIG);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
246
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/grc_addr.h
59
#define GRCBASE_MISC_AEU GRCBASE_MISC // just for driver init