usr/src/cmd/bhyve/common/pci_e82545.c

1833

uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >>

usr/src/cmd/bhyve/common/pci_e82545.c

1846

sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr);

usr/src/cmd/bhyve/common/pci_e82545.c

1849

e82545_write_mdi(sc, reg_addr, phy_addr,

usr/src/cmd/bhyve/common/pci_e82545.c

407

e82545_write_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,

usr/src/cmd/bhyve/common/pci_e82545.c

410

DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data);

usr/src/cmd/bhyve/common/pci_e82545.c

414

e82545_read_mdi(struct e82545_softc *sc __unused, uint8_t reg_addr,

usr/src/cmd/bhyve/common/pci_e82545.c

418

switch (reg_addr) {

usr/src/cmd/bhyve/common/pci_e82545.c

434

DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr);

usr/src/cmd/cxgbetool/cudbg_view.c

4555

print_t6_sge_reg_value(u32 reg_addr, u32 reg_data, u32 data_value,

usr/src/cmd/cxgbetool/cudbg_view.c

4562

reg_addr, reg_data, reg_array->name, data_value,

usr/src/cmd/cxgbetool/cudbg_view.c

4609

print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[0],

usr/src/cmd/cxgbetool/cudbg_view.c

4612

print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[1],

usr/src/cmd/cxgbetool/cudbg_view.c

4615

print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[2],

usr/src/cmd/cxgbetool/cudbg_view.c

4618

print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[3],

usr/src/grub/grub-0.97/netboot/e1000.c

110

static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);

usr/src/grub/grub-0.97/netboot/e1000.c

111

static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);

usr/src/grub/grub-0.97/netboot/e1000.c

112

static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);

usr/src/grub/grub-0.97/netboot/e1000.c

113

static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);

usr/src/grub/grub-0.97/netboot/e1000.c

2814

uint32_t reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2822

(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {

usr/src/grub/grub-0.97/netboot/e1000.c

2824

(uint16_t)reg_addr)))

usr/src/grub/grub-0.97/netboot/e1000.c

2828

ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2836

uint32_t reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2845

if(reg_addr > MAX_PHY_REG_ADDRESS) {

usr/src/grub/grub-0.97/netboot/e1000.c

2846

DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);

usr/src/grub/grub-0.97/netboot/e1000.c

2855

mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |

usr/src/grub/grub-0.97/netboot/e1000.c

2894

mdic = ((reg_addr) | (phy_addr << 5) |

usr/src/grub/grub-0.97/netboot/e1000.c

2917

uint32_t reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2925

(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {

usr/src/grub/grub-0.97/netboot/e1000.c

2927

(uint16_t)reg_addr)))

usr/src/grub/grub-0.97/netboot/e1000.c

2931

ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2939

uint32_t reg_addr,

usr/src/grub/grub-0.97/netboot/e1000.c

2948

if(reg_addr > MAX_PHY_REG_ADDRESS) {

usr/src/grub/grub-0.97/netboot/e1000.c

2949

DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);

usr/src/grub/grub-0.97/netboot/e1000.c

2959

(reg_addr << E1000_MDIC_REG_SHIFT) |

usr/src/grub/grub-0.97/netboot/e1000.c

2989

mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |

usr/src/lib/udapl/libdat/include/dat/udat_redirection.h

57

lmr, lmr_context, rmr_context, reg_len, reg_addr) \

usr/src/lib/udapl/libdat/include/dat/udat_redirection.h

69

(reg_addr))

usr/src/uts/common/io/audio/drv/audiots/audiots.c

1151

uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg;

usr/src/uts/common/io/audio/drv/audiots/audiots.c

1170

if (!(ddi_get16(handle, reg_addr) &

usr/src/uts/common/io/audio/drv/audiots/audiots.c

1173

ddi_put16(handle, reg_addr, reg);

usr/src/uts/common/io/audio/drv/audiots/audiots.c

1187

if (!(ddi_get16(handle, reg_addr) &

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c

75

u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr )

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c

77

return REG_RD(cb, reg_addr);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c

80

void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val )

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c

82

REG_WR(cb, reg_addr, val);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

48

u32_t reg_addr, reg_bit_map, vnic;

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

69

reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

70

reg_bit_map = REG_RD(pdev, reg_addr);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

71

REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map));

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

74

reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

75

reg_bit_map = REG_RD(pdev, reg_addr);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

76

REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

81

reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

82

reg_bit_map = REG_RD(pdev, reg_addr);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c

87

REG_WR(pdev, reg_addr, reg_bit_map);

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h

24

extern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr);

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h

25

extern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val);

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

1340

static const struct reg_addr idle_addrs[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

1612

static const struct reg_addr split_reg_addrs[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

264

static const struct reg_addr reg_addrs[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

8179

static const struct reg_addr page_read_regs_e1[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

8194

static const struct reg_addr page_read_regs_e1h[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

8210

static const struct reg_addr page_read_regs_e2[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/hw_dump.h

8225

static const struct reg_addr page_read_regs_e3[] = {

usr/src/uts/common/io/bnxe/577xx/hsi/mcp/nvm_map.h

621

u32_t reg_addr;

usr/src/uts/common/io/chxge/com/ch_subr.c

275

int reg_addr, unsigned int *val)

usr/src/uts/common/io/chxge/com/ch_subr.c

287

V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));

usr/src/uts/common/io/chxge/com/ch_subr.c

294

int reg_addr, unsigned int val)

usr/src/uts/common/io/chxge/com/ch_subr.c

306

V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr));

usr/src/uts/common/io/chxge/com/ch_subr.c

358

int reg_addr, unsigned int *valp)

usr/src/uts/common/io/chxge/com/ch_subr.c

360

u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);

usr/src/uts/common/io/chxge/com/ch_subr.c

376

int reg_addr, unsigned int val)

usr/src/uts/common/io/chxge/com/ch_subr.c

378

u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);

usr/src/uts/common/io/chxge/com/ch_subr.c

405

int reg_addr, unsigned int *valp)

usr/src/uts/common/io/chxge/com/ch_subr.c

413

(void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);

usr/src/uts/common/io/chxge/com/ch_subr.c

431

int reg_addr, unsigned int *valp)

usr/src/uts/common/io/chxge/com/ch_subr.c

439

(void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);

usr/src/uts/common/io/chxge/com/ch_subr.c

456

int reg_addr, unsigned int val)

usr/src/uts/common/io/chxge/com/ch_subr.c

464

(void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);

usr/src/uts/common/io/chxge/com/cphy.h

34

int reg_addr, unsigned int *val);

usr/src/uts/common/io/chxge/com/cphy.h

36

int reg_addr, unsigned int val);

usr/src/uts/common/io/chxge/com/cphy.h

91

int reg_addr, unsigned int *val);

usr/src/uts/common/io/chxge/com/cphy.h

93

int reg_addr, unsigned int val);

usr/src/uts/common/io/cxgbe/common/t4_hw.c

5771

static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,

usr/src/uts/common/io/cxgbe/common/t4_hw.c

5778

switch (reg_addr) {

usr/src/uts/common/io/cxgbe/common/t4_hw.c

5800

t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,

usr/src/uts/common/io/cxgbe/common/t4_hw.c

5803

t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,

usr/src/uts/common/io/cxgbe/common/t4_regs.h

102

#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

105

#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

108

#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

114

#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

117

#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

120

#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

123

#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

20

#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

23

#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

237

#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

246

#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

249

#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

253

#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

256

#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

259

#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

26

#define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

262

#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

265

#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

274

#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

277

#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

283

#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

286

#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

289

#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

29

#define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

292

#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

295

#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

32

#define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

331

#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

334

#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

337

#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

340

#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

343

#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

346

#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

349

#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

35

#define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

352

#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

355

#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

370

#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

373

#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

376

#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

38

#define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

41

#define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

44

#define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

469

#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

472

#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

475

#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

51

#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

54

#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

57

#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

60

#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

63

#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

66

#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

69

#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

72

#define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

75

#define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

78

#define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))

usr/src/uts/common/io/cxgbe/common/t4_regs.h

90

#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

93

#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

96

#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/common/t4_regs.h

99

#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

usr/src/uts/common/io/cxgbe/t4nex/cudbg_entity.h

816

u32 reg_addr;

usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c

4235

u32 reg_addr, reg_data, reg_local_offset, reg_offset_range;

usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c

4296

reg_addr = t5_pcie_cdbg_array[0][0];

usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c

4301

t4_read_indirect(padap, reg_addr, reg_data, sp, reg_offset_range,

usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c

4308

reg_addr = t5_pcie_cdbg_array[0][0];

usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c

4313

t4_read_indirect(padap, reg_addr, reg_data, sp,

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2302

u16 word_addr, reg_data, reg_addr, phy_page = 0;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2398

1, &reg_addr);

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2403

if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2408

reg_addr &= PHY_REG_MASK;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2409

reg_addr |= phy_page;

usr/src/uts/common/io/e1000api/e1000_ich8lan.c

2411

ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,

usr/src/uts/common/io/i40e/core/i40e_common.c

3421

u32 reg_addr, u64 *reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

3434

cmd_resp->address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

3456

u32 reg_addr, u64 reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

3466

cmd->address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

7159

u32 reg_addr, u32 *reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

7172

cmd_resp->address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

7187

u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)

usr/src/uts/common/io/i40e/core/i40e_common.c

7199

status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);

usr/src/uts/common/io/i40e/core/i40e_common.c

7209

val = rd32(hw, reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

7225

u32 reg_addr, u32 reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

7235

cmd->address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

7249

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)

usr/src/uts/common/io/i40e/core/i40e_common.c

7260

status = i40e_aq_rx_ctl_write_register(hw, reg_addr,

usr/src/uts/common/io/i40e/core/i40e_common.c

7271

wr32(hw, reg_addr, reg_val);

usr/src/uts/common/io/i40e/core/i40e_common.c

7318

u32 reg_addr, u32 reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

7331

cmd->reg_address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_common.c

7364

u32 reg_addr, u32 *reg_val,

usr/src/uts/common/io/i40e/core/i40e_common.c

7377

cmd->reg_address = CPU_TO_LE32(reg_addr);

usr/src/uts/common/io/i40e/core/i40e_prototype.h

126

u32 reg_addr, u64 reg_val,

usr/src/uts/common/io/i40e/core/i40e_prototype.h

129

u32 reg_addr, u64 *reg_val,

usr/src/uts/common/io/i40e/core/i40e_prototype.h

569

u32 reg_addr, u32 *reg_val,

usr/src/uts/common/io/i40e/core/i40e_prototype.h

571

u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);

usr/src/uts/common/io/i40e/core/i40e_prototype.h

573

u32 reg_addr, u32 reg_val,

usr/src/uts/common/io/i40e/core/i40e_prototype.h

575

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);

usr/src/uts/common/io/i40e/core/i40e_prototype.h

580

u32 reg_addr, u32 reg_val,

usr/src/uts/common/io/i40e/core/i40e_prototype.h

586

u32 reg_addr, u32 *reg_val,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

1321

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

1324

return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

1337

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

1340

return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

575

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

581

return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

594

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.c

600

return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.h

215

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.h

217

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.h

71

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_api.h

73

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

597

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

603

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

634

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

679

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

690

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

705

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

714

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

743

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

779

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.c

788

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h

166

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h

168

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h

170

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h

172

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

1130

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

1145

command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

1176

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

1191

command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

4318

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

4329

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

4346

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

4355

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

520

static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

523

UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

527

static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c

530

UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.h

100

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.h

102

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.h

64

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ixgbe/core/ixgbe_x550.h

66

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

usr/src/uts/common/io/ntxn/niu.c

134

address.reg_addr = (unm_crbword_t)reg;

usr/src/uts/common/io/ntxn/unm_inc.h

984

reg_addr:5, /* which mgmt register we want to talk to */

usr/src/uts/common/io/nxge/npi/npi_mac.c

3417

mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */

usr/src/uts/common/io/nxge/npi/npi_mac.c

3457

mif_cfg.bits.w0.reg_addr = device; /* Register address */

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2453

u32 line, reg_addr, i, offset = 0;

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2458

for (line = start_line, reg_addr = DBG_REG_INTR_BUFFER + DWORDS_TO_BYTES(start_line * INT_BUF_LINE_SIZE_IN_DWORDS);

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2461

for (i = 0; i < INT_BUF_LINE_SIZE_IN_DWORDS; i++, reg_addr += BYTES_IN_DWORD)

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2462

dump_buf[offset + INT_BUF_LINE_SIZE_IN_DWORDS - 1 - i] = ecore_rd(p_hwfn, p_ptt, reg_addr);

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2806

u32 reg_addr;

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2813

reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + SEM_FAST_REG_STALL_0_BB_K2;

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dbg_fw_funcs.c

2814

ecore_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0);

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c

323

u32 OSAL_IOMEM *reg_addr;

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c

338

reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c

342

DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);

usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c

346

reg_addr++);

usr/src/uts/common/io/qede/579xx/hsi/mcp/nvm_map.h

286

u32 reg_addr;

usr/src/uts/common/io/qede/qede_gld.c

1423

uint32_t *reg_addr;

usr/src/uts/common/sys/nxge/nxge_mac_hw.h

1323

uint32_t reg_addr : 5;

usr/src/uts/common/sys/nxge/nxge_mac_hw.h

1333

uint32_t reg_addr : 5;

usr/src/uts/sun4u/io/i2c/nexus/smbus.c

737

uint8_t *reg_addr = smbus->smbus_regaddr;

usr/src/uts/sun4u/io/i2c/nexus/smbus.c

741

ddi_put8(hp, &reg_addr[reg], data);

usr/src/uts/sun4u/io/i2c/nexus/smbus.c

744

&reg_addr[reg], data));

usr/src/uts/sun4u/io/iocache.c

185

volatile uint64_t *reg_addr;

usr/src/uts/sun4u/io/iocache.c

191

for (i = 0, reg_addr = softsp->str_buf_pg_tag_diag;

usr/src/uts/sun4u/io/iocache.c

192

i < STREAM_CACHE_LINES; i++, reg_addr++) {

usr/src/uts/sun4u/io/iocache.c

195

reg = *reg_addr;

usr/src/uts/sun4u/io/iocache.c

204

(void *)reg_addr, hi, lo));

usr/src/uts/sun4u/io/pci/pcisch.c

1071

volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx;

usr/src/uts/sun4u/io/pci/pcisch.c

1074

if (!*reg_addr) {

usr/src/uts/sun4u/io/pci/pcisch.c

1080

matchreg = *reg_addr; /* re-fetch after 1st flush */

usr/src/uts/sun4u/io/pci/pcisch.c

1091

if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */

usr/src/uts/sun4u/io/pmubus.c

598

addr = regp->reg_addr & ~MAPPING_SHARED_BITS_MASK;

usr/src/uts/sun4u/io/pmubus.c

623

if (regp->reg_addr & MAPPING_SHARED_BITS_MASK)

usr/src/uts/sun4u/io/pmubus.c

709

pmubus_rp.reg_addr = ((uint64_t)

usr/src/uts/sun4u/io/pmubus.c

744

if ((pmubus_rp.reg_addr + off) >

usr/src/uts/sun4u/io/pmubus.c

745

(pmubus_rp.reg_addr + pmubus_rp.reg_size)) {

usr/src/uts/sun4u/io/pmubus.c

750

pmubus_rp.reg_addr += off;

usr/src/uts/sun4u/io/pmubus.c

776

pmubus_mapreqp->mapreq_addr = pmubus_rp.reg_addr;

usr/src/uts/sun4u/sys/pmubus.h

47

uint64_t reg_addr;