readl
readl((a)->hw_addr + E1000_##reg) : \
readl((a)->hw_addr + E1000_82542_##reg))
readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
readl(base);
} while ((readl(base + offset) & mask) != target);
reg = readl(base + NvRegAdapterControl);
reg = readl(base + NvRegMIIControl);
} else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
retval = readl(base + NvRegMIIData);
reg = readl(base + NvRegAdapterControl);
if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
writel(readl(base + NvRegTransmitterStatus),
writel(readl(base + NvRegReceiverStatus),
i = readl(base + NvRegPowerState);
writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID,
np->orig_mac[0] = readl(base + NvRegMacAddrA);
np->orig_mac[1] = readl(base + NvRegMacAddrB);
cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY;
tbisr = readl(ns->base + TBISR);
tanar = readl(ns->base + TANAR);
tanlpar = readl(ns->base + TANLPAR);
writel(readl(ns->base + TXCFG)
writel(readl(ns->base + RXCFG) | RXCFG_RX_FD,
writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT,
writel((readl(ns->base + TXCFG)
writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD,
writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT,
} while (readl(ns->base + CR) & which);
data = readl(ns->base + RFDR);
val = (readl(rfcr) & and_mask) | or_mask;
status = readl(ns->base + PTSCR);
u32 isr = readl(ns->base + ISR);
u32 isr = readl(ns->base + ISR);
readl(ns->base + IER);
readl(ns->base + IMR);
readl(ns->base + IER);
ns->CFG_cache = readl(ns->base + CFG);
writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR);
writel(readl(ns->base + TANAR)
if (readl(dev->base + SRR))
writel(readl(dev->base + 0x20c) | 0xfe00,
(unsigned) readl(ns->base + SRR) >> 8,
(unsigned) readl(ns->base + SRR) & 0xff,
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
#define tr32(reg) readl(tg3.regs + (reg))
u32 intr_status = readl(ioaddr + IntrStatus);
#define eeprom_delay(ee_addr) readl(ee_addr)
retval = (retval << 1) | ((readl(ee_addr) & EE_DataIn) ? 1 : 0);
#define mdio_delay(mdio_addr) readl(mdio_addr)
retval = (retval << 1) | ((readl(mdio_addr) & MDIO_DataIn) ? 1 : 0);
STATE(readl);
if (get_state_expr(my_id, expr) == &readl)
set_state_expr(my_id, expr->left, &readl);