lane
void *arg, phyeye_lane_iter_cb_f func, uint8_t lane, uint8_t eye)
if (lane != UINT8_MAX && desc->eld_ln != lane)
"invalid PCIe lane %u: must be between 0-3", lane));
!nvme_vuc_req_set_cdw13(req, lane) ||
nvme_sndk_pci_eye(nvme_ctrl_t *ctrl, uint8_t lane, void *buf, size_t len)
if (lane >= 4) {
u16 base_page, next_page, not_kr2_device, lane;
lane = elink_get_warpcore_lane(phy, params);
MDIO_AER_BLOCK_AER_REG, lane);
u8 lane = elink_get_warpcore_lane(phy, params);
val &= ~(0x11 << lane);
val |= (0x11 << lane);
u8 lane = 0;
lane = (port<<1) + path;
lane = path << 1 ;
return lane;
u8 lane = elink_get_warpcore_lane(phy, params);
lane;
u16 lane = elink_get_warpcore_lane(phy, params);
MDIO_AER_BLOCK_AER_REG, lane);
u16 lane, i, cl72_ctrl, an_adv = 0, val;
lane = elink_get_warpcore_lane(phy, params);
MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
MDIO_AER_BLOCK_AER_REG, lane);
MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
(SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
u16 val16, i, lane;
lane = elink_get_warpcore_lane(phy, params);
val16 &= ~(0x0011 << lane);
val16 |= (0x0303 << (lane << 1));
u16 misc1_val, tap_val, tx_driver_val, lane, val;
lane = elink_get_warpcore_lane(phy, params);
MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
u16 lane)
MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
u16 lane)
lane = elink_get_warpcore_lane(phy, params);
MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
u16 gp2_status_reg0, lane;
lane = elink_get_warpcore_lane(phy, params);
return (gp2_status_reg0 >> (8+lane)) & 0x1;
u16 lane = elink_get_warpcore_lane(phy, params);
lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
u16 lane = elink_get_warpcore_lane(phy, params);
elink_warpcore_clear_regs(phy, params, lane);
u16 lane = elink_get_warpcore_lane(phy, params);
elink_warpcore_clear_regs(phy, params, lane);
elink_warpcore_clear_regs(phy, params, lane);
elink_warpcore_set_20G_DXGXS(cb, phy, lane);
u16 val16, lane;
lane = elink_get_warpcore_lane(phy, params);
val16 |= (0x11 << lane);
val16 |= (0x22 << lane);
val16 &= ~(0x0303 << (lane << 1));
val16 |= (0x0101 << (lane << 1));
val16 &= ~(0x0c0c << (lane << 1));
val16 |= (0x0404 << (lane << 1));
u32 lane;
lane = elink_get_warpcore_lane(phy, params);
val16 |= (1<<lane);
val16 |= (2<<lane);
u16 lane, val;
for (lane = 0; lane < WC_LANE_MAX; lane++) {
MDIO_AER_BLOCK_AER_REG, lane);
u16 lane, val;
for (lane = 0; lane < WC_LANE_MAX; lane++) {
MDIO_AER_BLOCK_AER_REG, lane);
for (lane = 0x200; lane <= 0x201; lane++) {
MDIO_AER_BLOCK_AER_REG, lane);
elink_warpcore_set_20G_DXGXS(cb, phy, lane);
u8 lane;
lane = elink_get_warpcore_lane(phy, params);
(1 << lane);
if (gp_status4 & ((1<<12)<<lane))
if (lane < 2) {
ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed);
if ((lane & 1) == 0)
u8 lane = elink_get_warpcore_lane(int_phy, params);
link_up = gp_status & (1 << lane);
u8 lane = elink_get_warpcore_lane(phy, params);
val &= ~(0xf << (lane << 2));
val |= (mode << (lane << 2));
u32 port, u32 lane, u32 addr, u32 data_lo,
if (lane > 6) {
rc = ecore_phy_write(p_hwfn,p_ptt, port, lane, addr, data_lo,
u32 port, u32 lane, u32 addr, char *p_phy_result_buf)
if (lane > 6) {
rc = ecore_phy_read(p_hwfn,p_ptt, port, lane, addr, ECORE_PHY_RAW_READ,
struct ecore_ptt *p_ptt, u32 port, u32 lane,
addr | (lane << 16) | (1<<29) | (port << 30), buf, 8);
u32 lane, u32 addr, u32 data_lo,
addr | (lane << 16) | (1<<29) | (port << 30),
u32 port, u32 lane, u32 addr, u32 cmd, u8 *buf);
u32 port, u32 lane, u32 addr, u32 data_lo,
u32 port, u32 lane, u32 addr, char *p_phy_result_buf);
u32 port, u32 lane, u32 addr, u32 data_lo,
uint32_t port, lane;