inl
u_int inl(u_int port);
u_int inl(u_int port);
vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG)
j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
phy_data=(inl(ee_addr)>>19) & 0x1;
retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
(volatile unsigned long)inl(ioaddr + CSR8);
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
(volatile unsigned long)inl(ioaddr + CSR8);
#define eeprom_delay() inl(ee_addr)
return inl(port);
val = inl(ioaddr + SCBCtrlMDI);
val = inl(ioaddr + SCBCtrlMDI);
retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
if ((inl(mmctl) & MII_READOP) == 0)
u32 chip_config = inl(ioaddr + ChipConfig);
nic_name, (int)inl(ioaddr + 0x84), advertising);
SavedClkRun = inl(ioaddr + ClkRun);
#define eeprom_delay(ee_addr) inl(ee_addr)
retval |= (inl(ee_addr) & EE_DataOut) ? 1 << i : 0;
return inl(ioaddr + 0x80 + (location<<2)) & 0xffff;
if (inl(ioaddr + ChipConfig) & 0x20000000) { /* Full duplex */
if (inl(ioaddr + SiliconRev) == 0x302) {
inl(ioaddr + TxRingPtr));
inl(ioaddr + RxRingPtr));
int duplex = inl(ioaddr + ChipConfig) & 0x20000000 ? 1 : 0;
inl(ioaddr + TxRingPtr));
*value = inl(0xCFC);
return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
inl(addr + PCNET32_DWIO_RESET);
return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
#define eeprom_delay() inl(ee_addr)
txstatus = inl(nic->ioaddr+ TxStatus0 + cur_tx*4);
outl(TxDIS | inl(ioaddr + cr), ioaddr + cr);
inl(ioaddr + txdp));
outl(TxENA | inl(ioaddr + cr), ioaddr + cr);
outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
if(inl(ee_addr) & EEGNT) {
rfcrSave = inl(rfcr + ioaddr);
outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
#define eeprom_delay() inl(ee_addr)
retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
#define sis900_mdio_delay() inl(mdio_addr)
retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
outl(RxENA| inl(ioaddr + cr), ioaddr + cr);
outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr);
status ^= (inl(isr + ioaddr) & status);
rfcrSave = inl(rfcr + ioaddr);
i, inl(ioaddr + rfdr));
inl(ioaddr + txdp));
inl(ioaddr + rxdp));
if( inl(ioaddr + cfg) & EDB_MASTER_EN ) {
outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl);
sdc->nic_name, (int) inl(BASE + RxStatus),
(int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0),
if (inl(BASE + ASICCtrl) & 0x80) {
dprintf(("ASIC Control is %x.\n", inl(BASE + ASICCtrl)));
dprintf(("ASIC Control is now %x.\n", inl(BASE + ASICCtrl)));
data = inl(BASE + TLAN_HOST_CMD);
data = inl(BASE + TLAN_HOST_CMD);
data = inl(BASE + TLAN_HOST_CMD);
return (inl(base_addr + TLAN_DIO_DATA));
u32 csr6 = inl(ioaddr + CSR6);
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
(volatile unsigned long)inl(ioaddr + CSR8);
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
(volatile unsigned long)inl(ioaddr + CSR8);
if (inl(ioaddr + CSR5) == 0xFFFFFFFF) {
if (chip_idx == DC21041 && inl(ioaddr + CSR9) & 0x8000) {
value = inl(ioaddr + CSR9);
value = inl(ioaddr + CSR9);
put_unaligned(inl(ioaddr + 0xA4), (u32 *)nic->node_addr);
put_unaligned(inl(ioaddr + 0xA8), (u16 *)(nic->node_addr + 4));
outl(inl(ioaddr + CSR6) | 0x0200, ioaddr + CSR6);
} else if (inl(ioaddr + CSR5) & TPLnkPass)
u32 phy_reg = inl(ioaddr + 0xB8);
inl(ioaddr + CSR12) & 0xff);
inl(ioaddr + CSR12));
tp->nic_name, inl(ioaddr + 0xB8), medianame[tp->if_port]);
int csr12 = inl(ioaddr + CSR12);
inl(ioaddr + CSR12));
#define eeprom_delay() inl(ee_addr)
#define mdio_delay() inl(mdio_addr)
inl(ioaddr + 0xA0);
inl(ioaddr + 0xA0);
if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
return inl(ioaddr + 0xB4 + (location<<2));
return inl(ioaddr + 0xD0);
return inl(ioaddr + 0xD4 + ((location-29)<<2));
retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
if ( ! (inl(ioaddr + 0xA0) & 0x80000000))
retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
int csr6 = inl(ioaddr + CSR6) & ~0x00D5;
outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
#define readl inl
unsigned char *in, int inl)
if (inl == 0)
if ((ctx->num+inl) < ctx->length) {
(void) memcpy(&(ctx->enc_data[ctx->num]), in, inl);
ctx->num += inl;
inl -= i;
while (inl >= ctx->length) {
inl -= ctx->length;
if (inl != 0)
(void) memcpy(&(ctx->enc_data[0]), in, inl);
ctx->num = inl;
unsigned char *in, int inl)
if ((inl == 0) || ((n == 0) && (conv_ascii2bin(in[0]) == B64_EOF))) {
for (i = 0; i < inl; i++) {
if (((i+1) == inl) && (((n&3) == 0) || eof)) {
uint32_t inl(uint16_t);
uint32_t period = inl(IOP_TEST_VALUE);
divisor = inl(IOP_TEST_PARAM);
start = inl(IOP_PMTMR);
end = inl(IOP_PMTMR);
const uint32_t count = inl(IOP_TEST_PARAM0);
inl(s)->fun();
s += sizeof &inl;
s += sizeof inl;
s += sizeof *inl;
struct nlist *inl;
for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nreq++)
struct nlist *p, *inl;
for (inl = list, nreq = 0; inl->n_name && inl->n_name[0]; ++inl, nreq++)
return (inl(nvc->nvc_sgp_csr));
extern uint32_t inl(int port);
local_data = inl(port);
inl(PCI_CONFDATA);
inl(PCI_CONFDATA);
dev_vendor = inl(PCI_CONFDATA);
val = inl(PCI_CONFDATA);
val = inl(PCI_CONFDATA);
val = inl(PCI_CADDR2(device, reg));
if (inl(PCI_CONFDATA) != ((0x04a3 << 16) | 0x8086)) {
if ((inl(PCI_CADDR2(0, PCI_CONF_VENID)) != 0x04a38086) ||
tmp = inl(PCI_CONFADD);
*Value = inl(Address);
val = inl((uintptr_t)addr);
val = ddi_swap32(inl((uintptr_t)addr));
if ((*h++ = inl(port)) == 0xffffffff)
if ((*h++ = inl(port)) == 0xffffffff)
if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
if ((*h++ = ddi_swap32(inl(port))) == 0xffffffff)
return (ddi_swap32(inl((uintptr_t)addr)));
*h++ = ddi_swap32(inl(port));
*h++ = ddi_swap32(inl(port));
extern uint32_t inl(int port);