Symbol: immu
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
109
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
111
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
121
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
144
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
146
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
153
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
176
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
178
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
185
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
201
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
203
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
210
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
258
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
262
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
269
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
41
static ihandle_t immu;
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
43
if (immu != (ihandle_t)0)
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
44
return (immu);
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
47
return (immu = (ihandle_t)-1);
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
49
(void) prom_getprop(prom_chosennode(), "mmu", (caddr_t)(&immu));
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
50
return (immu);
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
68
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
70
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4/prom_mmu.c
77
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
42
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
44
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
51
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
72
ihandle_t immu = prom_mmu_ihandle();
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
74
if ((immu == (ihandle_t)-1))
usr/src/psm/promif/ieee1275/sun4u/prom_tlb.c
81
ci[4] = p1275_ihandle2cell(immu); /* Arg2: mmu ihandle */
usr/src/psm/stand/cpr/sparcv9/sun4u/util.c
242
ihandle_t immu;
usr/src/psm/stand/cpr/sparcv9/sun4u/util.c
246
immu = prom_mmu_ihandle();
usr/src/psm/stand/cpr/sparcv9/sun4u/util.c
247
if (immu == (ihandle_t)-1)
usr/src/psm/stand/cpr/sparcv9/sun4u/util.c
254
ci[4] = p1275_ihandle2cell(immu); /* Arg2: memory ihandle */
usr/src/uts/i86pc/io/immu.c
1219
immu_t *immu;
usr/src/uts/i86pc/io/immu.c
1229
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu.c
1230
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu.c
1233
if (immu->immu_regs_running == B_FALSE)
usr/src/uts/i86pc/io/immu.c
1237
rw_enter(&(immu->immu_ctx_rwlock), RW_WRITER);
usr/src/uts/i86pc/io/immu.c
1238
immu_flush_context_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu.c
1239
immu_flush_iotlb_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu.c
1240
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu.c
1241
immu_regs_wbf_flush(immu);
usr/src/uts/i86pc/io/immu.c
1243
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
1249
immu_regs_shutdown(immu);
usr/src/uts/i86pc/io/immu.c
1250
immu_regs_suspend(immu);
usr/src/uts/i86pc/io/immu.c
1253
if (immu->immu_regs_running == B_TRUE)
usr/src/uts/i86pc/io/immu.c
1256
immu->immu_regs_quiesced = B_TRUE;
usr/src/uts/i86pc/io/immu.c
1258
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
1277
immu_t *immu;
usr/src/uts/i86pc/io/immu.c
1287
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu.c
1288
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu.c
1290
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
1293
if (immu->immu_regs_quiesced == B_FALSE) {
usr/src/uts/i86pc/io/immu.c
1294
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
1298
if (immu_regs_resume(immu) != DDI_SUCCESS) {
usr/src/uts/i86pc/io/immu.c
1300
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
1305
rw_enter(&(immu->immu_ctx_rwlock), RW_WRITER);
usr/src/uts/i86pc/io/immu.c
1306
immu_flush_context_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu.c
1307
immu_flush_iotlb_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu.c
1308
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu.c
1317
immu_regs_startup(immu);
usr/src/uts/i86pc/io/immu.c
1319
if (immu->immu_regs_running == B_FALSE) {
usr/src/uts/i86pc/io/immu.c
1324
immu->immu_regs_quiesced = B_FALSE;
usr/src/uts/i86pc/io/immu.c
1327
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
802
immu_t *immu;
usr/src/uts/i86pc/io/immu.c
812
immu = kmem_zalloc(sizeof (immu_t), KM_SLEEP);
usr/src/uts/i86pc/io/immu.c
814
mutex_init(&(immu->immu_lock), NULL, MUTEX_DRIVER, NULL);
usr/src/uts/i86pc/io/immu.c
816
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
818
immu->immu_dmar_unit = dmar_unit;
usr/src/uts/i86pc/io/immu.c
819
immu->immu_dip = immu_dmar_unit_dip(dmar_unit);
usr/src/uts/i86pc/io/immu.c
821
nodename = ddi_node_name(immu->immu_dip);
usr/src/uts/i86pc/io/immu.c
822
instance = ddi_get_instance(immu->immu_dip);
usr/src/uts/i86pc/io/immu.c
824
immu->immu_name = immu_alloc_name(nodename, instance);
usr/src/uts/i86pc/io/immu.c
825
if (immu->immu_name == NULL)
usr/src/uts/i86pc/io/immu.c
833
mutex_init(&(immu->immu_intr_lock), NULL, MUTEX_DRIVER,
usr/src/uts/i86pc/io/immu.c
837
mutex_init(&(immu->immu_regs_lock), NULL, MUTEX_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu.c
838
cv_init(&(immu->immu_regs_cv), NULL, CV_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu.c
839
immu->immu_regs_busy = B_FALSE;
usr/src/uts/i86pc/io/immu.c
842
immu->immu_dvma_coherent = B_FALSE;
usr/src/uts/i86pc/io/immu.c
845
rw_init(&(immu->immu_ctx_rwlock), NULL, RW_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu.c
848
list_create(&(immu->immu_domain_list), sizeof (domain_t),
usr/src/uts/i86pc/io/immu.c
852
immu->immu_dvma_gfx_only = B_FALSE;
usr/src/uts/i86pc/io/immu.c
853
list_create(&(immu->immu_dvma_lpc_list), sizeof (immu_devi_t),
usr/src/uts/i86pc/io/immu.c
855
list_create(&(immu->immu_dvma_gfx_list), sizeof (immu_devi_t),
usr/src/uts/i86pc/io/immu.c
859
mutex_init(&(immu->immu_intrmap_lock), NULL, MUTEX_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu.c
862
mutex_init(&(immu->immu_qinv_lock), NULL, MUTEX_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu.c
867
list_insert_tail(&immu_list, immu);
usr/src/uts/i86pc/io/immu.c
877
immu->immu_pgtable_cache = kmem_cache_create(pcachename,
usr/src/uts/i86pc/io/immu.c
878
sizeof (pgtable_t), 0, pgtable_ctor, pgtable_dtor, NULL, immu,
usr/src/uts/i86pc/io/immu.c
880
immu->immu_hdl_cache = kmem_cache_create(hcachename,
usr/src/uts/i86pc/io/immu.c
882
NULL, NULL, immu, NULL, 0);
usr/src/uts/i86pc/io/immu.c
884
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
886
ddi_err(DER_LOG, immu->immu_dip, "unit setup");
usr/src/uts/i86pc/io/immu.c
888
immu_dmar_set_immu(dmar_unit, immu);
usr/src/uts/i86pc/io/immu.c
931
immu_t *immu;
usr/src/uts/i86pc/io/immu.c
938
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu.c
939
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu.c
941
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
943
immu_intr_register(immu);
usr/src/uts/i86pc/io/immu.c
944
immu_dvma_startup(immu);
usr/src/uts/i86pc/io/immu.c
945
immu_intrmap_startup(immu);
usr/src/uts/i86pc/io/immu.c
946
immu_qinv_startup(immu);
usr/src/uts/i86pc/io/immu.c
955
immu_regs_startup(immu);
usr/src/uts/i86pc/io/immu.c
957
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu.c
961
iommulib_ops->ilops_data = (void *)immu;
usr/src/uts/i86pc/io/immu.c
962
(void) iommulib_iommu_register(immu->immu_dip, iommulib_ops,
usr/src/uts/i86pc/io/immu.c
963
&immu->immu_iommulib_handle);
usr/src/uts/i86pc/io/immu_dmar.c
1244
immu_dmar_set_immu(void *dmar_unit, immu_t *immu)
usr/src/uts/i86pc/io/immu_dmar.c
1249
ASSERT(immu);
usr/src/uts/i86pc/io/immu_dmar.c
1251
drhd->dr_immu = immu;
usr/src/uts/i86pc/io/immu_dvma.c
1020
create_xlate_arena(immu_t *immu, domain_t *domain,
usr/src/uts/i86pc/io/immu_dvma.c
1037
"%s-domain-%d-xlate-DVMA-arena", immu->immu_name,
usr/src/uts/i86pc/io/immu_dvma.c
1043
mgaw = IMMU_CAP_MGAW(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_dvma.c
1175
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
1193
immu = immu_dvma_get_immu(rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
1194
if (immu == NULL) {
usr/src/uts/i86pc/io/immu_dvma.c
1247
domain = domain_create(immu, ddip, rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
1267
create_unity_domain(immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
1279
domain->dom_immu = immu;
usr/src/uts/i86pc/io/immu_dvma.c
1280
immu->immu_unity_domain = domain;
usr/src/uts/i86pc/io/immu_dvma.c
1286
domain->dom_pgtable_root = pgtable_alloc(immu, IMMU_FLAGS_SLEEP);
usr/src/uts/i86pc/io/immu_dvma.c
1294
if (!IMMU_ECAP_GET_PT(immu->immu_regs_excap))
usr/src/uts/i86pc/io/immu_dvma.c
1313
domain_create(immu_t *immu, dev_info_t *ddip, dev_info_t *rdip,
usr/src/uts/i86pc/io/immu_dvma.c
1331
did = did_alloc(immu, rdip, ddip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
1334
ASSERT(immu->immu_unity_domain);
usr/src/uts/i86pc/io/immu_dvma.c
1335
return (immu->immu_unity_domain);
usr/src/uts/i86pc/io/immu_dvma.c
1342
"structure for device. IOMMU unit: %s", immu->immu_name);
usr/src/uts/i86pc/io/immu_dvma.c
1349
"immu%s-domain%d-pava-hash", immu->immu_name, did);
usr/src/uts/i86pc/io/immu_dvma.c
1352
domain->dom_immu = immu;
usr/src/uts/i86pc/io/immu_dvma.c
1359
create_xlate_arena(immu, domain, rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
1364
domain->dom_pgtable_root = pgtable_alloc(immu, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
1368
domain->dom_did, immu->immu_name);
usr/src/uts/i86pc/io/immu_dvma.c
1377
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu_dvma.c
1378
list_insert_head(&immu->immu_domain_list, domain);
usr/src/uts/i86pc/io/immu_dvma.c
1379
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu_dvma.c
1419
did_init(immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
1421
(void) snprintf(immu->immu_did_arena_name,
usr/src/uts/i86pc/io/immu_dvma.c
1422
sizeof (immu->immu_did_arena_name),
usr/src/uts/i86pc/io/immu_dvma.c
1423
"%s_domainid_arena", immu->immu_name);
usr/src/uts/i86pc/io/immu_dvma.c
1425
ddi_err(DER_VERB, immu->immu_dip, "creating domainid arena %s",
usr/src/uts/i86pc/io/immu_dvma.c
1426
immu->immu_did_arena_name);
usr/src/uts/i86pc/io/immu_dvma.c
1428
immu->immu_did_arena = vmem_create(
usr/src/uts/i86pc/io/immu_dvma.c
1429
immu->immu_did_arena_name,
usr/src/uts/i86pc/io/immu_dvma.c
1431
immu->immu_max_domains - IMMU_UNITY_DID,
usr/src/uts/i86pc/io/immu_dvma.c
1440
if (immu->immu_did_arena == NULL) {
usr/src/uts/i86pc/io/immu_dvma.c
1442
"IOMMU domainid allocator: %s", immu->immu_name,
usr/src/uts/i86pc/io/immu_dvma.c
1443
immu->immu_did_arena_name);
usr/src/uts/i86pc/io/immu_dvma.c
1450
context_set(immu_t *immu, domain_t *domain, pgtable_t *root_table,
usr/src/uts/i86pc/io/immu_dvma.c
1473
rw_enter(&(immu->immu_ctx_rwlock), RW_READER);
usr/src/uts/i86pc/io/immu_dvma.c
1479
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu_dvma.c
1490
rw_tryupgrade(&(immu->immu_ctx_rwlock)) == 0) {
usr/src/uts/i86pc/io/immu_dvma.c
1491
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu_dvma.c
1492
rw_enter(&(immu->immu_ctx_rwlock), RW_WRITER);
usr/src/uts/i86pc/io/immu_dvma.c
1501
immu_regs_cpu_flush(immu, (caddr_t)hw_rent, sizeof (hw_rce_t));
usr/src/uts/i86pc/io/immu_dvma.c
1510
immu_regs_cpu_flush(immu, (caddr_t)hw_cent, sizeof (hw_rce_t));
usr/src/uts/i86pc/io/immu_dvma.c
1513
immu_flush_context_fsi(immu, 0, sid, domain->dom_did,
usr/src/uts/i86pc/io/immu_dvma.c
1514
&immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu_dvma.c
1518
CONT_SET_AW(hw_cent, immu->immu_dvma_agaw);
usr/src/uts/i86pc/io/immu_dvma.c
1521
IMMU_ECAP_GET_PT(immu->immu_regs_excap))
usr/src/uts/i86pc/io/immu_dvma.c
1527
if (IMMU_ECAP_GET_CH(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_dvma.c
1532
immu_regs_cpu_flush(immu, (caddr_t)hw_cent, sizeof (hw_rce_t));
usr/src/uts/i86pc/io/immu_dvma.c
1534
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu_dvma.c
1538
context_create(immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
1550
root_table = pgtable_alloc(immu, IMMU_FLAGS_SLEEP);
usr/src/uts/i86pc/io/immu_dvma.c
1560
context = pgtable_alloc(immu, IMMU_FLAGS_SLEEP);
usr/src/uts/i86pc/io/immu_dvma.c
1568
immu->immu_unity_domain->dom_pgtable_root;
usr/src/uts/i86pc/io/immu_dvma.c
1570
immu->immu_unity_domain->dom_did);
usr/src/uts/i86pc/io/immu_dvma.c
1571
CONT_SET_AW(hw_cent, immu->immu_dvma_agaw);
usr/src/uts/i86pc/io/immu_dvma.c
1573
if (IMMU_ECAP_GET_PT(immu->immu_regs_excap))
usr/src/uts/i86pc/io/immu_dvma.c
1581
immu_regs_cpu_flush(immu, context->hwpg_vaddr, IMMU_PAGESIZE);
usr/src/uts/i86pc/io/immu_dvma.c
1592
context_init(immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
1594
rw_init(&(immu->immu_ctx_rwlock), NULL, RW_DEFAULT, NULL);
usr/src/uts/i86pc/io/immu_dvma.c
1596
immu_init_inv_wait(&immu->immu_ctx_inv_wait, "ctxglobal", B_TRUE);
usr/src/uts/i86pc/io/immu_dvma.c
1598
immu_regs_wbf_flush(immu);
usr/src/uts/i86pc/io/immu_dvma.c
1600
immu->immu_ctx_root = context_create(immu);
usr/src/uts/i86pc/io/immu_dvma.c
1602
immu_regs_set_root_table(immu);
usr/src/uts/i86pc/io/immu_dvma.c
1604
rw_enter(&(immu->immu_ctx_rwlock), RW_WRITER);
usr/src/uts/i86pc/io/immu_dvma.c
1605
immu_flush_context_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu_dvma.c
1606
immu_flush_iotlb_gbl(immu, &immu->immu_ctx_inv_wait);
usr/src/uts/i86pc/io/immu_dvma.c
1607
rw_exit(&(immu->immu_ctx_rwlock));
usr/src/uts/i86pc/io/immu_dvma.c
1630
immu_context_update(immu_t *immu, domain_t *domain, dev_info_t *ddip,
usr/src/uts/i86pc/io/immu_dvma.c
1678
context_set(immu, domain, immu->immu_ctx_root, r_bus,
usr/src/uts/i86pc/io/immu_dvma.c
1687
context_set(immu, domain, immu->immu_ctx_root, r_bus,
usr/src/uts/i86pc/io/immu_dvma.c
1697
context_set(immu, domain, immu->immu_ctx_root,
usr/src/uts/i86pc/io/immu_dvma.c
1700
context_set(immu, domain, immu->immu_ctx_root,
usr/src/uts/i86pc/io/immu_dvma.c
1710
context_set(immu, domain, immu->immu_ctx_root,
usr/src/uts/i86pc/io/immu_dvma.c
1719
context_set(immu, domain, immu->immu_ctx_root, d_bus,
usr/src/uts/i86pc/io/immu_dvma.c
1726
context_set(immu, domain, immu->immu_ctx_root, d_bus,
usr/src/uts/i86pc/io/immu_dvma.c
1744
PDTE_check(immu_t *immu, hw_pdte_t pdte, pgtable_t *next, paddr_t paddr,
usr/src/uts/i86pc/io/immu_dvma.c
1764
if (next == NULL && immu->immu_TM_reserved == B_FALSE) {
usr/src/uts/i86pc/io/immu_dvma.c
1803
if (next == NULL && immu->immu_SNP_reserved == B_FALSE) {
usr/src/uts/i86pc/io/immu_dvma.c
1847
PTE_clear_all(immu_t *immu, domain_t *domain, xlate_t *xlate,
usr/src/uts/i86pc/io/immu_dvma.c
1972
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
1982
immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
1991
nlevels = immu->immu_dvma_nlevels;
usr/src/uts/i86pc/io/immu_dvma.c
2012
PTE_set_one(immu_t *immu, hw_pdte_t *hwp, paddr_t paddr,
usr/src/uts/i86pc/io/immu_dvma.c
2018
pte = immu->immu_ptemask;
usr/src/uts/i86pc/io/immu_dvma.c
2036
if (immu->immu_TM_reserved == B_FALSE) {
usr/src/uts/i86pc/io/immu_dvma.c
2049
if (immu->immu_SNP_reserved == B_FALSE) {
usr/src/uts/i86pc/io/immu_dvma.c
2076
pte |= immu->immu_ptemask;
usr/src/uts/i86pc/io/immu_dvma.c
2097
PTE_set_all(immu_t *immu, domain_t *domain, xlate_t *xlate,
usr/src/uts/i86pc/io/immu_dvma.c
2139
PTE_set_one(immu, hwp, paddr, rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
2142
ASSERT(PDTE_check(immu, *hwp, NULL, paddr, rdip, immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
2175
PDE_set_one(immu_t *immu, hw_pdte_t *hwp, pgtable_t *next,
usr/src/uts/i86pc/io/immu_dvma.c
2247
PDE_set_all(immu_t *immu, domain_t *domain, xlate_t *xlate, int nlevels,
usr/src/uts/i86pc/io/immu_dvma.c
2285
new = pgtable_alloc(immu, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
2305
PDE_set_one(immu, hwp, next, rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
2329
ASSERT(PDTE_check(immu, *hwp, next, 0, rdip, immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
2337
pgtable_free(immu, new);
usr/src/uts/i86pc/io/immu_dvma.c
2362
immu_t *immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
2363
int nlevels = immu->immu_dvma_nlevels;
usr/src/uts/i86pc/io/immu_dvma.c
2374
if (PDE_set_all(immu, domain, xlate, nlevels, rdip, immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
2380
PTE_set_all(immu, domain, &xlate[1], &dvma, &n, dcookies,
usr/src/uts/i86pc/io/immu_dvma.c
2402
immu_t *immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
2403
int nlevels = immu->immu_dvma_nlevels;
usr/src/uts/i86pc/io/immu_dvma.c
2422
PTE_clear_all(immu, domain, &xlate[1], &dvma, &n, rdip);
usr/src/uts/i86pc/io/immu_dvma.c
2466
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
2471
immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
2472
nlevels = immu->immu_dvma_nlevels;
usr/src/uts/i86pc/io/immu_dvma.c
250
immu_devi_set_spclist(dev_info_t *dip, immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
2505
(void) PDE_set_all(immu, domain, xlate, nlevels, rdip,
usr/src/uts/i86pc/io/immu_dvma.c
2513
PTE_set_all(immu, domain, xlp, &dvma, &n, &immu_precookie,
usr/src/uts/i86pc/io/immu_dvma.c
2561
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
257
spclist = &(immu->immu_dvma_gfx_list);
usr/src/uts/i86pc/io/immu_dvma.c
2579
immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
259
spclist = &(immu->immu_dvma_lpc_list);
usr/src/uts/i86pc/io/immu_dvma.c
2627
rwmask = PDTE_MASK_R | PDTE_MASK_W | immu->immu_ptemask;
usr/src/uts/i86pc/io/immu_dvma.c
2629
rwmask = immu->immu_ptemask;
usr/src/uts/i86pc/io/immu_dvma.c
263
mutex_enter(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu_dvma.c
265
mutex_exit(&(immu->immu_lock));
usr/src/uts/i86pc/io/immu_dvma.c
2725
immu_flush_iotlb_psi(immu, domain->dom_did, sdvma, npgalloc,
usr/src/uts/i86pc/io/immu_dvma.c
2785
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
2807
immu = list_head(listp);
usr/src/uts/i86pc/io/immu_dvma.c
2808
for (; immu; immu = list_next(listp, immu)) {
usr/src/uts/i86pc/io/immu_dvma.c
2809
create_unity_domain(immu);
usr/src/uts/i86pc/io/immu_dvma.c
2810
did_init(immu);
usr/src/uts/i86pc/io/immu_dvma.c
2811
context_init(immu);
usr/src/uts/i86pc/io/immu_dvma.c
2812
immu->immu_dvma_setup = B_TRUE;
usr/src/uts/i86pc/io/immu_dvma.c
2820
immu_dvma_startup(immu_t *immu)
usr/src/uts/i86pc/io/immu_dvma.c
2823
immu->immu_dvma_gfx_only == B_TRUE) {
usr/src/uts/i86pc/io/immu_dvma.c
2830
immu->immu_dvma_running = B_TRUE;
usr/src/uts/i86pc/io/immu_dvma.c
2885
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
2890
immu = immu_dvma_get_immu(rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
2891
if (immu == NULL) {
usr/src/uts/i86pc/io/immu_dvma.c
2904
rdip = get_lpc_devinfo(immu, rdip, immu_flags);
usr/src/uts/i86pc/io/immu_dvma.c
2912
immu = NULL;
usr/src/uts/i86pc/io/immu_dvma.c
2937
immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
2956
if (immu_context_update(immu, domain, ddip, rdip, immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
2970
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
2978
immu = domain->dom_immu;
usr/src/uts/i86pc/io/immu_dvma.c
2986
immu_flush_iotlb_psi(immu, domain->dom_did, mrng->mrng_start,
usr/src/uts/i86pc/io/immu_dvma.c
3069
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
3074
immu = IMMU_DEVI(rdip)->imd_immu;
usr/src/uts/i86pc/io/immu_dvma.c
3076
ihp = kmem_cache_alloc(immu->immu_hdl_cache,
usr/src/uts/i86pc/io/immu_dvma.c
323
get_lpc_devinfo(immu_t *immu, dev_info_t *rdip, immu_flags_t immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
326
dvarg.dva_list = &(immu->immu_dvma_lpc_list);
usr/src/uts/i86pc/io/immu_dvma.c
349
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
358
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu_dvma.c
359
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu_dvma.c
360
list_gfx = &(immu->immu_dvma_gfx_list);
usr/src/uts/i86pc/io/immu_dvma.c
428
immu_t *immu = arg;
usr/src/uts/i86pc/io/immu_dvma.c
446
if (!immu->immu_dvma_coherent)
usr/src/uts/i86pc/io/immu_dvma.c
507
pgtable_alloc(immu_t *immu, immu_flags_t immu_flags)
usr/src/uts/i86pc/io/immu_dvma.c
514
pgtable = kmem_cache_alloc(immu->immu_pgtable_cache, kmflags);
usr/src/uts/i86pc/io/immu_dvma.c
529
pgtable_free(immu_t *immu, pgtable_t *pgtable)
usr/src/uts/i86pc/io/immu_dvma.c
531
kmem_cache_free(immu->immu_pgtable_cache, pgtable);
usr/src/uts/i86pc/io/immu_dvma.c
616
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
638
immu = immu_devi->imd_immu;
usr/src/uts/i86pc/io/immu_dvma.c
640
return (immu);
usr/src/uts/i86pc/io/immu_dvma.c
644
immu = immu_dmar_get_immu(dip);
usr/src/uts/i86pc/io/immu_dvma.c
645
if (immu == NULL) {
usr/src/uts/i86pc/io/immu_dvma.c
666
immu_devi->imd_immu = immu;
usr/src/uts/i86pc/io/immu_dvma.c
667
immu_devi_set_spclist(dip, immu);
usr/src/uts/i86pc/io/immu_dvma.c
673
if (immu_devi->imd_immu != immu) {
usr/src/uts/i86pc/io/immu_dvma.c
676
"actual (%p)", (void *)immu,
usr/src/uts/i86pc/io/immu_dvma.c
683
return (immu);
usr/src/uts/i86pc/io/immu_dvma.c
76
static domain_t *domain_create(immu_t *immu, dev_info_t *ddip,
usr/src/uts/i86pc/io/immu_dvma.c
806
did_alloc(immu_t *immu, dev_info_t *rdip,
usr/src/uts/i86pc/io/immu_dvma.c
811
did = (uintptr_t)vmem_alloc(immu->immu_did_arena, 1,
usr/src/uts/i86pc/io/immu_dvma.c
819
immu->immu_name, immu->immu_unity_domain->dom_did);
usr/src/uts/i86pc/io/immu_dvma.c
820
did = immu->immu_unity_domain->dom_did;
usr/src/uts/i86pc/io/immu_dvma.c
832
immu_t *immu;
usr/src/uts/i86pc/io/immu_dvma.c
853
immu = immu_devi->imd_immu;
usr/src/uts/i86pc/io/immu_dvma.c
854
if (immu == NULL)
usr/src/uts/i86pc/io/immu_dvma.c
855
immu = immu_dvma_get_immu(pdip, dvp->dva_flags);
usr/src/uts/i86pc/io/immu_dvma.c
881
dvp->dva_domain = immu->immu_unity_domain;
usr/src/uts/i86pc/io/immu_intrmap.c
1000
(caddr_t)immu, NULL, NULL, NULL);
usr/src/uts/i86pc/io/immu_intrmap.c
1002
immu_regs_intr_enable(immu, msi_addr, msi_data, uaddr);
usr/src/uts/i86pc/io/immu_intrmap.c
1004
(void) immu_intr_handler((caddr_t)immu, NULL);
usr/src/uts/i86pc/io/immu_intrmap.c
302
init_unit(immu_t *immu)
usr/src/uts/i86pc/io/immu_intrmap.c
334
ASSERT(IMMU_ECAP_GET_QI(immu->immu_regs_excap));
usr/src/uts/i86pc/io/immu_intrmap.c
337
if (!IMMU_ECAP_GET_EIM(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_intrmap.c
348
if (ddi_dma_alloc_handle(immu->immu_dip,
usr/src/uts/i86pc/io/immu_intrmap.c
383
immu->immu_intrmap = intrmap;
usr/src/uts/i86pc/io/immu_intrmap.c
391
immu_t *immu = NULL;
usr/src/uts/i86pc/io/immu_intrmap.c
394
immu = immu_dmar_ioapic_immu(ioapic_index);
usr/src/uts/i86pc/io/immu_intrmap.c
397
immu = immu_dmar_get_immu(dip);
usr/src/uts/i86pc/io/immu_intrmap.c
400
return (immu);
usr/src/uts/i86pc/io/immu_intrmap.c
479
intrmap_enable(immu_t *immu)
usr/src/uts/i86pc/io/immu_intrmap.c
484
intrmap = immu->immu_intrmap;
usr/src/uts/i86pc/io/immu_intrmap.c
491
immu_regs_intrmap_enable(immu, irta_reg);
usr/src/uts/i86pc/io/immu_intrmap.c
503
immu_t *immu = (immu_t *)arg;
usr/src/uts/i86pc/io/immu_intrmap.c
510
mutex_enter(&(immu->immu_intr_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
511
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
514
status = immu_regs_get32(immu, IMMU_REG_FAULT_STS);
usr/src/uts/i86pc/io/immu_intrmap.c
516
idip = immu->immu_dip;
usr/src/uts/i86pc/io/immu_intrmap.c
521
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
522
mutex_exit(&(immu->immu_intr_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
530
max_fault_index = IMMU_CAP_GET_NFR(immu->immu_regs_cap) - 1;
usr/src/uts/i86pc/io/immu_intrmap.c
531
fault_reg_offset = IMMU_CAP_GET_FRO(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_intrmap.c
544
val = immu_regs_get64(immu, fault_reg_offset + index * 16 + 8);
usr/src/uts/i86pc/io/immu_intrmap.c
559
val = immu_regs_get64(immu, fault_reg_offset + index * 16);
usr/src/uts/i86pc/io/immu_intrmap.c
564
immu_regs_put32(immu, fault_reg_offset + index * 16 + 12,
usr/src/uts/i86pc/io/immu_intrmap.c
605
immu_regs_put32(immu, IMMU_REG_FAULT_STS, 1);
usr/src/uts/i86pc/io/immu_intrmap.c
606
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
607
mutex_exit(&(immu->immu_intr_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
620
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
629
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu_intrmap.c
630
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu_intrmap.c
631
if ((immu->immu_intrmap_running == B_TRUE) &&
usr/src/uts/i86pc/io/immu_intrmap.c
632
IMMU_ECAP_GET_IR(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_intrmap.c
633
if (init_unit(immu) == DDI_SUCCESS) {
usr/src/uts/i86pc/io/immu_intrmap.c
652
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
657
immu = list_head(&immu_list);
usr/src/uts/i86pc/io/immu_intrmap.c
658
for (; immu; immu = list_next(&immu_list, immu)) {
usr/src/uts/i86pc/io/immu_intrmap.c
659
if (immu->immu_intrmap_setup == B_TRUE) {
usr/src/uts/i86pc/io/immu_intrmap.c
660
intrmap_enable(immu);
usr/src/uts/i86pc/io/immu_intrmap.c
670
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
686
immu = get_immu(dip, type, ioapic_index);
usr/src/uts/i86pc/io/immu_intrmap.c
687
if ((immu != NULL) && (immu->immu_intrmap_running == B_TRUE)) {
usr/src/uts/i86pc/io/immu_intrmap.c
688
intrmap_private->ir_immu = immu;
usr/src/uts/i86pc/io/immu_intrmap.c
693
intrmap = immu->immu_intrmap;
usr/src/uts/i86pc/io/immu_intrmap.c
713
if (IMMU_CAP_GET_CM(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_intrmap.c
714
immu_qinv_intr_one_cache(immu, idx, iwp);
usr/src/uts/i86pc/io/immu_intrmap.c
716
immu_regs_wbf_flush(immu);
usr/src/uts/i86pc/io/immu_intrmap.c
725
INTRMAP_PRIVATE(intrmap_private_tbl[i])->ir_immu = immu;
usr/src/uts/i86pc/io/immu_intrmap.c
731
if (IMMU_CAP_GET_CM(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_intrmap.c
732
immu_qinv_intr_caches(immu, idx, count, iwp);
usr/src/uts/i86pc/io/immu_intrmap.c
734
immu_regs_wbf_flush(immu);
usr/src/uts/i86pc/io/immu_intrmap.c
750
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
764
immu = INTRMAP_PRIVATE(intrmap_private)->ir_immu;
usr/src/uts/i86pc/io/immu_intrmap.c
766
intrmap = immu->immu_intrmap;
usr/src/uts/i86pc/io/immu_intrmap.c
806
immu_qinv_intr_one_cache(immu, idx, iwp);
usr/src/uts/i86pc/io/immu_intrmap.c
821
immu_qinv_intr_caches(immu, idx, count, iwp);
usr/src/uts/i86pc/io/immu_intrmap.c
829
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
839
immu = INTRMAP_PRIVATE(*intrmap_privatep)->ir_immu;
usr/src/uts/i86pc/io/immu_intrmap.c
841
intrmap = immu->immu_intrmap;
usr/src/uts/i86pc/io/immu_intrmap.c
847
immu_qinv_intr_one_cache(immu, idx, iwp);
usr/src/uts/i86pc/io/immu_intrmap.c
917
immu_t *immu;
usr/src/uts/i86pc/io/immu_intrmap.c
936
immu = list_head(listp);
usr/src/uts/i86pc/io/immu_intrmap.c
937
for (; immu; immu = list_next(listp, immu)) {
usr/src/uts/i86pc/io/immu_intrmap.c
938
mutex_init(&(immu->immu_intrmap_lock), NULL,
usr/src/uts/i86pc/io/immu_intrmap.c
940
mutex_enter(&(immu->immu_intrmap_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
941
immu_init_inv_wait(&immu->immu_intrmap_inv_wait,
usr/src/uts/i86pc/io/immu_intrmap.c
943
immu->immu_intrmap_setup = B_TRUE;
usr/src/uts/i86pc/io/immu_intrmap.c
944
mutex_exit(&(immu->immu_intrmap_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
949
immu_intrmap_startup(immu_t *immu)
usr/src/uts/i86pc/io/immu_intrmap.c
952
mutex_enter(&(immu->immu_intrmap_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
953
if (immu->immu_intrmap_setup == B_TRUE) {
usr/src/uts/i86pc/io/immu_intrmap.c
954
immu->immu_intrmap_running = B_TRUE;
usr/src/uts/i86pc/io/immu_intrmap.c
956
mutex_exit(&(immu->immu_intrmap_lock));
usr/src/uts/i86pc/io/immu_intrmap.c
964
immu_intr_register(immu_t *immu)
usr/src/uts/i86pc/io/immu_intrmap.c
996
"%s-intr-handler", immu->immu_name);
usr/src/uts/i86pc/io/immu_qinv.c
161
static void qinv_submit_inv_dsc(immu_t *immu, qinv_dsc_t *dsc);
usr/src/uts/i86pc/io/immu_qinv.c
162
static void qinv_context_common(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/io/immu_qinv.c
164
static void qinv_iotlb_common(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/io/immu_qinv.c
166
static void qinv_iec_common(immu_t *immu, uint_t iidx,
usr/src/uts/i86pc/io/immu_qinv.c
169
static void qinv_wait_sync(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/io/immu_qinv.c
171
static void qinv_dev_iotlb_common(immu_t *immu, uint16_t sid,
usr/src/uts/i86pc/io/immu_qinv.c
177
qinv_submit_inv_dsc(immu_t *immu, qinv_dsc_t *dsc)
usr/src/uts/i86pc/io/immu_qinv.c
186
qinv = (qinv_t *)immu->immu_qinv;
usr/src/uts/i86pc/io/immu_qinv.c
205
immu_regs_get64(immu, IMMU_REG_INVAL_QH));
usr/src/uts/i86pc/io/immu_qinv.c
214
immu_regs_put64(immu, IMMU_REG_INVAL_QT,
usr/src/uts/i86pc/io/immu_qinv.c
222
qinv_context_common(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/io/immu_qinv.c
230
qinv_submit_inv_dsc(immu, &dsc);
usr/src/uts/i86pc/io/immu_qinv.c
235
qinv_iotlb_common(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/io/immu_qinv.c
242
if (IMMU_CAP_GET_DRD(immu->immu_regs_cap))
usr/src/uts/i86pc/io/immu_qinv.c
244
if (IMMU_CAP_GET_DWD(immu->immu_regs_cap))
usr/src/uts/i86pc/io/immu_qinv.c
249
if (!IMMU_CAP_GET_PSI(immu->immu_regs_cap) ||
usr/src/uts/i86pc/io/immu_qinv.c
250
am > IMMU_CAP_GET_MAMV(immu->immu_regs_cap) ||
usr/src/uts/i86pc/io/immu_qinv.c
274
qinv_submit_inv_dsc(immu, &dsc);
usr/src/uts/i86pc/io/immu_qinv.c
279
qinv_dev_iotlb_common(immu_t *immu, uint16_t sid,
usr/src/uts/i86pc/io/immu_qinv.c
287
qinv_submit_inv_dsc(immu, &dsc);
usr/src/uts/i86pc/io/immu_qinv.c
292
qinv_iec_common(immu_t *immu, uint_t iidx, uint_t im, uint_t g)
usr/src/uts/i86pc/io/immu_qinv.c
299
qinv_submit_inv_dsc(immu, &dsc);
usr/src/uts/i86pc/io/immu_qinv.c
307
qinv_wait_sync(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
331
qinv_submit_inv_dsc(immu, &dsc);
usr/src/uts/i86pc/io/immu_qinv.c
375
qinv_setup(immu_t *immu)
usr/src/uts/i86pc/io/immu_qinv.c
401
mutex_init(&(immu->immu_qinv_lock), NULL, MUTEX_DRIVER, NULL);
usr/src/uts/i86pc/io/immu_qinv.c
404
mutex_enter(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_qinv.c
406
immu->immu_qinv = NULL;
usr/src/uts/i86pc/io/immu_qinv.c
407
if (!IMMU_ECAP_GET_QI(immu->immu_regs_excap) ||
usr/src/uts/i86pc/io/immu_qinv.c
409
mutex_exit(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_qinv.c
489
immu->immu_qinv = qinv;
usr/src/uts/i86pc/io/immu_qinv.c
491
mutex_exit(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_qinv.c
507
mutex_exit(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_qinv.c
526
immu_t *immu;
usr/src/uts/i86pc/io/immu_qinv.c
534
immu = list_head(listp);
usr/src/uts/i86pc/io/immu_qinv.c
535
for (; immu; immu = list_next(listp, immu)) {
usr/src/uts/i86pc/io/immu_qinv.c
536
if (qinv_setup(immu) == DDI_SUCCESS) {
usr/src/uts/i86pc/io/immu_qinv.c
537
immu->immu_qinv_setup = B_TRUE;
usr/src/uts/i86pc/io/immu_qinv.c
548
immu_qinv_startup(immu_t *immu)
usr/src/uts/i86pc/io/immu_qinv.c
553
if (immu->immu_qinv_setup == B_FALSE) {
usr/src/uts/i86pc/io/immu_qinv.c
557
qinv = (qinv_t *)immu->immu_qinv;
usr/src/uts/i86pc/io/immu_qinv.c
559
immu_regs_qinv_enable(immu, qinv_reg_value);
usr/src/uts/i86pc/io/immu_qinv.c
560
immu->immu_flushops = &immu_qinv_flushops;
usr/src/uts/i86pc/io/immu_qinv.c
561
immu->immu_qinv_running = B_TRUE;
usr/src/uts/i86pc/io/immu_qinv.c
569
immu_qinv_context_fsi(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/io/immu_qinv.c
572
qinv_context_common(immu, function_mask, source_id,
usr/src/uts/i86pc/io/immu_qinv.c
574
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
582
immu_qinv_context_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
584
qinv_context_common(immu, 0, 0, domain_id, CTT_INV_G_DOMAIN);
usr/src/uts/i86pc/io/immu_qinv.c
585
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
593
immu_qinv_context_gbl(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
595
qinv_context_common(immu, 0, 0, 0, CTT_INV_G_GLOBAL);
usr/src/uts/i86pc/io/immu_qinv.c
596
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
604
immu_qinv_iotlb_psi(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/io/immu_qinv.c
610
max_am = IMMU_CAP_GET_MAMV(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_qinv.c
613
if (IMMU_CAP_GET_PSI(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_qinv.c
617
qinv_iotlb_common(immu, domain_id,
usr/src/uts/i86pc/io/immu_qinv.c
624
qinv_iotlb_common(immu, domain_id,
usr/src/uts/i86pc/io/immu_qinv.c
630
qinv_iotlb_common(immu, domain_id, dvma,
usr/src/uts/i86pc/io/immu_qinv.c
634
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
642
immu_qinv_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
644
qinv_iotlb_common(immu, domain_id, 0, 0, 0, TLB_INV_G_DOMAIN);
usr/src/uts/i86pc/io/immu_qinv.c
645
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
653
immu_qinv_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
655
qinv_iotlb_common(immu, 0, 0, 0, 0, TLB_INV_G_GLOBAL);
usr/src/uts/i86pc/io/immu_qinv.c
656
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
661
immu_qinv_intr_global(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
663
qinv_iec_common(immu, 0, 0, IEC_INV_GLOBAL);
usr/src/uts/i86pc/io/immu_qinv.c
664
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
669
immu_qinv_intr_one_cache(immu_t *immu, uint_t iidx, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_qinv.c
671
qinv_iec_common(immu, iidx, 0, IEC_INV_INDEX);
usr/src/uts/i86pc/io/immu_qinv.c
672
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
677
immu_qinv_intr_caches(immu_t *immu, uint_t iidx, uint_t cnt,
usr/src/uts/i86pc/io/immu_qinv.c
687
qinv_iec_common(immu, iidx + cnt, 0, IEC_INV_INDEX);
usr/src/uts/i86pc/io/immu_qinv.c
689
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
697
if (mask > IMMU_ECAP_GET_MHMV(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_qinv.c
699
qinv_iec_common(immu, iidx + cnt, 0, IEC_INV_INDEX);
usr/src/uts/i86pc/io/immu_qinv.c
701
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
705
qinv_iec_common(immu, iidx, mask, IEC_INV_INDEX);
usr/src/uts/i86pc/io/immu_qinv.c
707
qinv_wait_sync(immu, iwp);
usr/src/uts/i86pc/io/immu_qinv.c
711
immu_qinv_report_fault(immu_t *immu)
usr/src/uts/i86pc/io/immu_qinv.c
718
mutex_enter(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_qinv.c
720
qinv = (qinv_t *)(immu->immu_qinv);
usr/src/uts/i86pc/io/immu_qinv.c
723
immu_regs_get64(immu, IMMU_REG_INVAL_QH));
usr/src/uts/i86pc/io/immu_qinv.c
729
ddi_err(DER_WARN, immu->immu_dip,
usr/src/uts/i86pc/io/immu_qinv.c
738
mutex_exit(&(immu->immu_qinv_lock));
usr/src/uts/i86pc/io/immu_regs.c
105
iva_offset = IMMU_ECAP_GET_IRO(immu->immu_regs_excap);
usr/src/uts/i86pc/io/immu_regs.c
111
if (IMMU_CAP_GET_DWD(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_regs.c
115
if (IMMU_CAP_GET_DRD(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_regs.c
138
immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
143
put_reg64(immu, iva_offset, iva);
usr/src/uts/i86pc/io/immu_regs.c
144
put_reg64(immu, iotlb_offset, command);
usr/src/uts/i86pc/io/immu_regs.c
145
wait_completion(immu, iotlb_offset, get_reg64,
usr/src/uts/i86pc/io/immu_regs.c
155
immu_regs_iotlb_psi(immu_t *immu, uint_t did, uint64_t dvma, uint_t snpages,
usr/src/uts/i86pc/io/immu_regs.c
167
if (!IMMU_CAP_GET_PSI(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_regs.c
168
immu_regs_iotlb_dsi(immu, did, iwp);
usr/src/uts/i86pc/io/immu_regs.c
172
max_am = IMMU_CAP_GET_MAMV(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_regs.c
174
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
196
iotlb_flush(immu, did, dvma, am, hint, IOTLB_PSI);
usr/src/uts/i86pc/io/immu_regs.c
204
iotlb_flush(immu, did, 0, 0, 0, IOTLB_DSI);
usr/src/uts/i86pc/io/immu_regs.c
206
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
215
immu_regs_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_regs.c
217
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
218
iotlb_flush(immu, domain_id, 0, 0, 0, IOTLB_DSI);
usr/src/uts/i86pc/io/immu_regs.c
219
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
228
immu_regs_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_regs.c
230
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
231
iotlb_flush(immu, 0, 0, 0, 0, IOTLB_GLOBAL);
usr/src/uts/i86pc/io/immu_regs.c
232
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
259
set_agaw(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
273
mgaw = IMMU_CAP_MGAW(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_regs.c
274
sagaw_mask = IMMU_CAP_SAGAW(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_regs.c
293
immu->immu_name, sagaw_mask, max_sagaw_mask);
usr/src/uts/i86pc/io/immu_regs.c
325
"and magaw", immu->immu_name, agaw, magaw);
usr/src/uts/i86pc/io/immu_regs.c
332
immu->immu_name, nlevels);
usr/src/uts/i86pc/io/immu_regs.c
339
immu->immu_dvma_nlevels = nlevels;
usr/src/uts/i86pc/io/immu_regs.c
340
immu->immu_dvma_agaw = agaw;
usr/src/uts/i86pc/io/immu_regs.c
346
setup_regs(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
353
mutex_init(&(immu->immu_regs_lock), NULL, MUTEX_DRIVER,
usr/src/uts/i86pc/io/immu_regs.c
359
error = ddi_regs_map_setup(immu->immu_dip, 0,
usr/src/uts/i86pc/io/immu_regs.c
360
(caddr_t *)&(immu->immu_regs_addr), (offset_t)0,
usr/src/uts/i86pc/io/immu_regs.c
362
&(immu->immu_regs_handle));
usr/src/uts/i86pc/io/immu_regs.c
366
immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
367
mutex_destroy(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
374
immu->immu_regs_cap = get_reg64(immu, IMMU_REG_CAP);
usr/src/uts/i86pc/io/immu_regs.c
375
immu->immu_regs_excap = get_reg64(immu, IMMU_REG_EXCAP);
usr/src/uts/i86pc/io/immu_regs.c
38
#define get_reg32(immu, offset) ddi_get32((immu)->immu_regs_handle, \
usr/src/uts/i86pc/io/immu_regs.c
380
if (IMMU_ECAP_GET_C(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_regs.c
381
immu->immu_dvma_coherent = B_TRUE;
usr/src/uts/i86pc/io/immu_regs.c
383
immu->immu_dvma_coherent = B_FALSE;
usr/src/uts/i86pc/io/immu_regs.c
387
"missing clflush functionality", immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
388
ddi_regs_map_free(&(immu->immu_regs_handle));
usr/src/uts/i86pc/io/immu_regs.c
389
mutex_destroy(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
39
(uint32_t *)(immu->immu_regs_addr + (offset)))
usr/src/uts/i86pc/io/immu_regs.c
395
immu->immu_SNP_reserved = immu_regs_is_SNP_reserved(immu);
usr/src/uts/i86pc/io/immu_regs.c
396
immu->immu_TM_reserved = immu_regs_is_TM_reserved(immu);
usr/src/uts/i86pc/io/immu_regs.c
398
if (IMMU_ECAP_GET_CH(immu->immu_regs_excap) && immu_use_tm)
usr/src/uts/i86pc/io/immu_regs.c
399
immu->immu_ptemask = PDTE_MASK_TM;
usr/src/uts/i86pc/io/immu_regs.c
40
#define get_reg64(immu, offset) ddi_get64((immu)->immu_regs_handle, \
usr/src/uts/i86pc/io/immu_regs.c
401
immu->immu_ptemask = 0;
usr/src/uts/i86pc/io/immu_regs.c
407
!IMMU_CAP_GET_RWBF(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_regs.c
41
(uint64_t *)(immu->immu_regs_addr + (offset)))
usr/src/uts/i86pc/io/immu_regs.c
411
IMMU_CAP_SET_RWBF(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_regs.c
417
immu->immu_max_domains = IMMU_CAP_ND(immu->immu_regs_cap);
usr/src/uts/i86pc/io/immu_regs.c
42
#define put_reg32(immu, offset, val) ddi_put32\
usr/src/uts/i86pc/io/immu_regs.c
422
if (set_agaw(immu) != DDI_SUCCESS) {
usr/src/uts/i86pc/io/immu_regs.c
423
ddi_regs_map_free(&(immu->immu_regs_handle));
usr/src/uts/i86pc/io/immu_regs.c
424
mutex_destroy(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
427
immu->immu_regs_cmdval = 0;
usr/src/uts/i86pc/io/immu_regs.c
429
immu->immu_flushops = &immu_regs_flushops;
usr/src/uts/i86pc/io/immu_regs.c
43
((immu)->immu_regs_handle, \
usr/src/uts/i86pc/io/immu_regs.c
44
(uint32_t *)(immu->immu_regs_addr + (offset)), val)
usr/src/uts/i86pc/io/immu_regs.c
445
immu_t *immu;
usr/src/uts/i86pc/io/immu_regs.c
448
immu = list_head(listp);
usr/src/uts/i86pc/io/immu_regs.c
449
for (; immu; immu = list_next(listp, immu)) {
usr/src/uts/i86pc/io/immu_regs.c
45
#define put_reg64(immu, offset, val) ddi_put64\
usr/src/uts/i86pc/io/immu_regs.c
451
if (setup_regs(immu) != DDI_SUCCESS) {
usr/src/uts/i86pc/io/immu_regs.c
452
immu->immu_regs_setup = B_FALSE;
usr/src/uts/i86pc/io/immu_regs.c
454
immu->immu_regs_setup = B_TRUE;
usr/src/uts/i86pc/io/immu_regs.c
46
((immu)->immu_regs_handle, \
usr/src/uts/i86pc/io/immu_regs.c
464
immu_regs_resume(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
47
(uint64_t *)(immu->immu_regs_addr + (offset)), val)
usr/src/uts/i86pc/io/immu_regs.c
471
error = ddi_regs_map_setup(immu->immu_dip, 0,
usr/src/uts/i86pc/io/immu_regs.c
472
(caddr_t *)&(immu->immu_regs_addr), (offset_t)0,
usr/src/uts/i86pc/io/immu_regs.c
474
&(immu->immu_regs_handle));
usr/src/uts/i86pc/io/immu_regs.c
479
immu_regs_set_root_table(immu);
usr/src/uts/i86pc/io/immu_regs.c
481
immu_regs_intr_enable(immu, immu->immu_regs_intr_msi_addr,
usr/src/uts/i86pc/io/immu_regs.c
482
immu->immu_regs_intr_msi_data, immu->immu_regs_intr_uaddr);
usr/src/uts/i86pc/io/immu_regs.c
484
(void) immu_intr_handler((caddr_t)immu, NULL);
usr/src/uts/i86pc/io/immu_regs.c
486
immu_regs_intrmap_enable(immu, immu->immu_intrmap_irta_reg);
usr/src/uts/i86pc/io/immu_regs.c
488
immu_regs_qinv_enable(immu, immu->immu_qinv_reg_value);
usr/src/uts/i86pc/io/immu_regs.c
498
immu_regs_suspend(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
501
immu->immu_intrmap_running = B_FALSE;
usr/src/uts/i86pc/io/immu_regs.c
504
ddi_regs_map_free(&(immu->immu_regs_handle));
usr/src/uts/i86pc/io/immu_regs.c
512
immu_regs_startup(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
516
if (immu->immu_regs_setup == B_FALSE) {
usr/src/uts/i86pc/io/immu_regs.c
520
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
521
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
522
immu->immu_regs_cmdval | IMMU_GCMD_TE);
usr/src/uts/i86pc/io/immu_regs.c
523
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
525
immu->immu_regs_cmdval |= IMMU_GCMD_TE;
usr/src/uts/i86pc/io/immu_regs.c
526
immu->immu_regs_running = B_TRUE;
usr/src/uts/i86pc/io/immu_regs.c
527
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
529
ddi_err(DER_NOTE, NULL, "%s running", immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
537
immu_regs_shutdown(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
541
if (immu->immu_regs_running == B_FALSE) {
usr/src/uts/i86pc/io/immu_regs.c
545
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
546
immu->immu_regs_cmdval &= ~IMMU_GCMD_TE;
usr/src/uts/i86pc/io/immu_regs.c
547
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
548
immu->immu_regs_cmdval);
usr/src/uts/i86pc/io/immu_regs.c
549
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
551
immu->immu_regs_running = B_FALSE;
usr/src/uts/i86pc/io/immu_regs.c
552
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
554
ddi_err(DER_NOTE, NULL, "IOMMU %s stopped", immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
563
immu_regs_intr_enable(immu_t *immu, uint32_t msi_addr, uint32_t msi_data,
usr/src/uts/i86pc/io/immu_regs.c
566
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
567
immu->immu_regs_intr_msi_addr = msi_addr;
usr/src/uts/i86pc/io/immu_regs.c
568
immu->immu_regs_intr_uaddr = uaddr;
usr/src/uts/i86pc/io/immu_regs.c
569
immu->immu_regs_intr_msi_data = msi_data;
usr/src/uts/i86pc/io/immu_regs.c
570
put_reg32(immu, IMMU_REG_FEVNT_ADDR, msi_addr);
usr/src/uts/i86pc/io/immu_regs.c
571
put_reg32(immu, IMMU_REG_FEVNT_UADDR, uaddr);
usr/src/uts/i86pc/io/immu_regs.c
572
put_reg32(immu, IMMU_REG_FEVNT_DATA, msi_data);
usr/src/uts/i86pc/io/immu_regs.c
573
put_reg32(immu, IMMU_REG_FEVNT_CON, 0);
usr/src/uts/i86pc/io/immu_regs.c
574
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
582
immu_regs_passthru_supported(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
584
if (IMMU_ECAP_GET_PT(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_regs.c
597
immu_regs_is_TM_reserved(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
599
if (IMMU_ECAP_GET_DI(immu->immu_regs_excap) ||
usr/src/uts/i86pc/io/immu_regs.c
600
IMMU_ECAP_GET_CH(immu->immu_regs_excap)) {
usr/src/uts/i86pc/io/immu_regs.c
611
immu_regs_is_SNP_reserved(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
614
return (IMMU_ECAP_GET_SC(immu->immu_regs_excap) ? B_FALSE : B_TRUE);
usr/src/uts/i86pc/io/immu_regs.c
623
immu_regs_wbf_flush(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
627
if (!IMMU_CAP_GET_RWBF(immu->immu_regs_cap)) {
usr/src/uts/i86pc/io/immu_regs.c
631
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
632
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
633
immu->immu_regs_cmdval | IMMU_GCMD_WBF);
usr/src/uts/i86pc/io/immu_regs.c
634
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
636
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
645
immu_regs_cpu_flush(immu_t *immu, caddr_t addr, uint_t size)
usr/src/uts/i86pc/io/immu_regs.c
649
if (immu->immu_dvma_coherent == B_TRUE)
usr/src/uts/i86pc/io/immu_regs.c
65
#define wait_completion(immu, offset, getf, completion, status) \
usr/src/uts/i86pc/io/immu_regs.c
668
context_flush(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/io/immu_regs.c
693
immu->immu_name);
usr/src/uts/i86pc/io/immu_regs.c
697
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
698
put_reg64(immu, IMMU_REG_CONTEXT_CMD, command);
usr/src/uts/i86pc/io/immu_regs.c
699
wait_completion(immu, IMMU_REG_CONTEXT_CMD, get_reg64,
usr/src/uts/i86pc/io/immu_regs.c
701
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
706
immu_regs_context_fsi(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/io/immu_regs.c
709
context_flush(immu, function_mask, source_id, domain_id, CONTEXT_FSI);
usr/src/uts/i86pc/io/immu_regs.c
71
status = getf(immu, offset); \
usr/src/uts/i86pc/io/immu_regs.c
714
immu_regs_context_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_regs.c
716
context_flush(immu, 0, 0, domain_id, CONTEXT_DSI);
usr/src/uts/i86pc/io/immu_regs.c
721
immu_regs_context_gbl(immu_t *immu, immu_inv_wait_t *iwp)
usr/src/uts/i86pc/io/immu_regs.c
723
context_flush(immu, 0, 0, 0, CONTEXT_GLOBAL);
usr/src/uts/i86pc/io/immu_regs.c
736
immu_regs_set_root_table(immu_t *immu)
usr/src/uts/i86pc/io/immu_regs.c
740
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
741
put_reg64(immu, IMMU_REG_ROOTENTRY,
usr/src/uts/i86pc/io/immu_regs.c
742
immu->immu_ctx_root->hwpg_paddr);
usr/src/uts/i86pc/io/immu_regs.c
743
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
744
immu->immu_regs_cmdval | IMMU_GCMD_SRTP);
usr/src/uts/i86pc/io/immu_regs.c
745
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
747
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
753
immu_regs_qinv_enable(immu_t *immu, uint64_t qinv_reg_value)
usr/src/uts/i86pc/io/immu_regs.c
760
mutex_enter(&immu->immu_regs_lock);
usr/src/uts/i86pc/io/immu_regs.c
761
immu->immu_qinv_reg_value = qinv_reg_value;
usr/src/uts/i86pc/io/immu_regs.c
763
put_reg64(immu, IMMU_REG_INVAL_QT, 0);
usr/src/uts/i86pc/io/immu_regs.c
766
put_reg64(immu, IMMU_REG_INVAL_QAR, qinv_reg_value);
usr/src/uts/i86pc/io/immu_regs.c
769
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
770
immu->immu_regs_cmdval | IMMU_GCMD_QIE);
usr/src/uts/i86pc/io/immu_regs.c
771
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
773
mutex_exit(&immu->immu_regs_lock);
usr/src/uts/i86pc/io/immu_regs.c
775
immu->immu_regs_cmdval |= IMMU_GCMD_QIE;
usr/src/uts/i86pc/io/immu_regs.c
776
immu->immu_qinv_running = B_TRUE;
usr/src/uts/i86pc/io/immu_regs.c
782
immu_regs_intrmap_enable(immu_t *immu, uint64_t irta_reg)
usr/src/uts/i86pc/io/immu_regs.c
790
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
791
immu->immu_intrmap_irta_reg = irta_reg;
usr/src/uts/i86pc/io/immu_regs.c
792
put_reg64(immu, IMMU_REG_IRTAR, irta_reg);
usr/src/uts/i86pc/io/immu_regs.c
793
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
794
immu->immu_regs_cmdval | IMMU_GCMD_SIRTP);
usr/src/uts/i86pc/io/immu_regs.c
795
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
797
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
800
immu_qinv_intr_global(immu, &immu->immu_intrmap_inv_wait);
usr/src/uts/i86pc/io/immu_regs.c
803
mutex_enter(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
804
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
805
immu->immu_regs_cmdval | IMMU_GCMD_IRE);
usr/src/uts/i86pc/io/immu_regs.c
806
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
809
immu->immu_regs_cmdval |= IMMU_GCMD_IRE;
usr/src/uts/i86pc/io/immu_regs.c
812
put_reg32(immu, IMMU_REG_GLOBAL_CMD,
usr/src/uts/i86pc/io/immu_regs.c
813
immu->immu_regs_cmdval | IMMU_GCMD_CFI);
usr/src/uts/i86pc/io/immu_regs.c
814
wait_completion(immu, IMMU_REG_GLOBAL_STS,
usr/src/uts/i86pc/io/immu_regs.c
817
immu->immu_regs_cmdval |= IMMU_GCMD_CFI;
usr/src/uts/i86pc/io/immu_regs.c
818
mutex_exit(&(immu->immu_regs_lock));
usr/src/uts/i86pc/io/immu_regs.c
820
immu->immu_intrmap_running = B_TRUE;
usr/src/uts/i86pc/io/immu_regs.c
824
immu_regs_get64(immu_t *immu, uint_t reg)
usr/src/uts/i86pc/io/immu_regs.c
826
return (get_reg64(immu, reg));
usr/src/uts/i86pc/io/immu_regs.c
830
immu_regs_get32(immu_t *immu, uint_t reg)
usr/src/uts/i86pc/io/immu_regs.c
832
return (get_reg32(immu, reg));
usr/src/uts/i86pc/io/immu_regs.c
836
immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val)
usr/src/uts/i86pc/io/immu_regs.c
838
put_reg64(immu, reg, val);
usr/src/uts/i86pc/io/immu_regs.c
842
immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val)
usr/src/uts/i86pc/io/immu_regs.c
844
put_reg32(immu, reg, val);
usr/src/uts/i86pc/io/immu_regs.c
97
iotlb_flush(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/sys/immu.h
105
struct immu;
usr/src/uts/i86pc/sys/immu.h
135
struct immu *dr_immu;
usr/src/uts/i86pc/sys/immu.h
869
void immu_dmar_set_immu(void *dmar_unit, immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
884
void immu_regs_startup(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
885
int immu_regs_resume(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
886
void immu_regs_suspend(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
887
void immu_regs_shutdown(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
890
void immu_regs_intr(immu_t *immu, uint32_t msi_addr, uint32_t msi_data,
usr/src/uts/i86pc/sys/immu.h
893
boolean_t immu_regs_passthru_supported(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
894
boolean_t immu_regs_is_TM_reserved(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
895
boolean_t immu_regs_is_SNP_reserved(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
897
void immu_regs_wbf_flush(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
898
void immu_regs_cpu_flush(immu_t *immu, caddr_t addr, uint_t size);
usr/src/uts/i86pc/sys/immu.h
900
void immu_regs_context_fsi(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/sys/immu.h
902
void immu_regs_context_dsi(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/sys/immu.h
904
void immu_regs_context_gbl(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
905
void immu_regs_iotlb_psi(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/sys/immu.h
907
void immu_regs_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
908
void immu_regs_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
910
void immu_regs_set_root_table(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
911
void immu_regs_qinv_enable(immu_t *immu, uint64_t qinv_reg_value);
usr/src/uts/i86pc/sys/immu.h
912
void immu_regs_intr_enable(immu_t *immu, uint32_t msi_addr, uint32_t msi_data,
usr/src/uts/i86pc/sys/immu.h
914
void immu_regs_intrmap_enable(immu_t *immu, uint64_t irta_reg);
usr/src/uts/i86pc/sys/immu.h
915
uint64_t immu_regs_get64(immu_t *immu, uint_t reg);
usr/src/uts/i86pc/sys/immu.h
916
void immu_regs_put64(immu_t *immu, uint_t reg, uint64_t val);
usr/src/uts/i86pc/sys/immu.h
917
uint32_t immu_regs_get32(immu_t *immu, uint_t reg);
usr/src/uts/i86pc/sys/immu.h
918
void immu_regs_put32(immu_t *immu, uint_t reg, uint32_t val);
usr/src/uts/i86pc/sys/immu.h
922
void immu_dvma_startup(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
923
void immu_dvma_shutdown(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
945
void immu_intrmap_startup(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
946
void immu_intrmap_shutdown(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
950
void immu_intr_register(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
956
void immu_qinv_startup(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
957
void immu_qinv_shutdown(immu_t *immu);
usr/src/uts/i86pc/sys/immu.h
960
void immu_qinv_context_fsi(immu_t *immu, uint8_t function_mask,
usr/src/uts/i86pc/sys/immu.h
962
void immu_qinv_context_dsi(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/sys/immu.h
964
void immu_qinv_context_gbl(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
965
void immu_qinv_iotlb_psi(immu_t *immu, uint_t domain_id,
usr/src/uts/i86pc/sys/immu.h
967
void immu_qinv_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
968
void immu_qinv_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
970
void immu_qinv_intr_global(immu_t *immu, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
971
void immu_qinv_intr_one_cache(immu_t *immu, uint_t idx, immu_inv_wait_t *iwp);
usr/src/uts/i86pc/sys/immu.h
972
void immu_qinv_intr_caches(immu_t *immu, uint_t idx, uint_t cnt,
usr/src/uts/i86pc/sys/immu.h
974
void immu_qinv_report_fault(immu_t *immu);
usr/src/uts/sun4v/promif/promif_emul.c
199
ihandle_t immu;
usr/src/uts/sun4v/promif/promif_emul.c
207
if ((immu = prom_mmu_ihandle()) == (ihandle_t)-1) {
usr/src/uts/sun4v/promif/promif_emul.c
211
node = (pnode_t)prom_getphandle(immu);