CHIP_REV_IS_SLOW
!CHIP_REV_IS_SLOW(params->chip_id)) {
if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) {
if (!CHIP_REV_IS_SLOW(params->chip_id))
if (CHIP_REV_IS_SLOW(params->chip_id)) {
(CHIP_REV_IS_SLOW(_chip_id)&& \
(CHIP_REV_IS_SLOW(_chip_id)&& \
u8 offset = (CHIP_REV_IS_SLOW(pdev) ?
if (CHIP_REV_IS_SLOW(pdev))
if (!CHIP_REV_IS_SLOW(pdev))
if (!CHIP_REV_IS_SLOW(pdev))
if (!CHIP_REV_IS_SLOW(pdev))
if (!CHIP_REV_IS_SLOW(pdev))
if (CHIP_REV_IS_SLOW(pdev))
if((CHIP_REV_IS_SLOW(pdev)
if (CHIP_REV_IS_SLOW(pdev)) {
if (CHIP_REV_IS_SLOW(pdev))
#define CHIP_REV_IS_SLOW(_p) (CHIP_REV(_p) > CHIP_REV_ASIC_MAX)
#define CHIP_REV_IS_FPGA(_p) (CHIP_REV_IS_SLOW(_p) && (CHIP_REV(_p) & CHIP_REV_SIM_IS_FPGA))
#define CHIP_REV_IS_EMUL(_p) (CHIP_REV_IS_SLOW(_p) && !(CHIP_REV(_p)& CHIP_REV_SIM_IS_FPGA)) //if it's simulated, and not FPGA, it's EMUL.
#define CHIP_REV_IS_ASIC(_p) (!CHIP_REV_IS_SLOW(_p))
#define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
((CHIP_REV_IS_SLOW(dev) && (!(dev)->b_is_emul_full)) ? \
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))