usr/src/common/mc/imc/imc_decode.c

145

itgt = BITX(pa, 9, 9);

usr/src/common/mc/imc/imc_decode.c

146

itgt |= (BITX(pa, 8, 7) << 1);

usr/src/common/mc/imc/imc_decode.c

148

itgt = BITX(pa, 8, 6);

usr/src/common/mc/imc/imc_decode.c

153

itgt = BITX(pa, 9, 9);

usr/src/common/mc/imc/imc_decode.c

154

itgt |= (BITX(pa, 8, 7) << 1);

usr/src/common/mc/imc/imc_decode.c

156

itgt = BITX(pa, 8, 6);

usr/src/common/mc/imc/imc_decode.c

158

itgt ^= BITX(pa, 18, 16);

usr/src/common/mc/imc/imc_decode.c

161

itgt = BITX(pa, 10, 8);

usr/src/common/mc/imc/imc_decode.c

164

itgt = BITX(pa, 14, 12);

usr/src/common/mc/imc/imc_decode.c

167

itgt = BITX(pa, 32, 30);

usr/src/grub/grub-0.97/stage2/expand.c

206

if ((family = BITX(vcr->r_eax, 11, 8)) == 0xf)

usr/src/grub/grub-0.97/stage2/expand.c

207

family += BITX(vcr->r_eax, 27, 20);

usr/src/grub/grub-0.97/stage2/expand.c

209

if ((model = BITX(vcr->r_eax, 7, 4)) == 0xf)

usr/src/grub/grub-0.97/stage2/expand.c

210

model += BITX(vcr->r_eax, 19, 16) << 4;

usr/src/grub/grub-0.97/stage2/expand.c

211

step = BITX(vcr->r_eax, 3, 0);

usr/src/grub/grub-0.97/stage2/expand.c

236

if (BITX(xtdfeatures, 29, 29)) /* long mode */

usr/src/grub/grub-0.97/stage2/expand.c

241

if (!BITX(stdfeatures, 0, 0)) {

usr/src/grub/grub-0.97/stage2/expand.c

246

if (!BITX(stdfeatures, 4, 4)) {

usr/src/grub/grub-0.97/stage2/expand.c

251

if (!BITX(stdfeatures, 5, 5)) {

usr/src/grub/grub-0.97/stage2/expand.c

256

if (!BITX(stdfeatures, 6, 6)) {

usr/src/grub/grub-0.97/stage2/expand.c

261

if (!BITX(stdfeatures, 8, 8)) {

usr/src/grub/grub-0.97/stage2/expand.c

266

if (!BITX(stdfeatures, 13, 13)) {

usr/src/grub/grub-0.97/stage2/expand.c

271

if (!BITX(stdfeatures, 19, 19)) {

usr/src/grub/grub-0.97/stage2/expand.c

276

if (!BITX(stdfeatures, 23, 23)) {

usr/src/grub/grub-0.97/stage2/expand.c

281

if (!BITX(stdfeatures, 24, 24)) {

usr/src/grub/grub-0.97/stage2/expand.c

286

if (!BITX(stdfeatures, 25, 25)) {

usr/src/grub/grub-0.97/stage2/expand.c

291

if (!BITX(stdfeatures, 26, 26)) {

usr/src/lib/libipmi/common/ipmi_fru.c

170

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

175

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

181

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

186

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

192

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

198

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

236

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

241

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

246

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

252

len = BITX(typelen, 5, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

96

cmd_data_in.ifr_offset_lsb = BITX(offset, 7, 0);

usr/src/lib/libipmi/common/ipmi_fru.c

97

cmd_data_in.ifr_offset_msb = BITX(offset, 15, 8);

usr/src/lib/libipmi/common/ipmi_util.c

280

tmp = BITX(*(data+j), 5, 0);

usr/src/lib/libipmi/common/ipmi_util.c

283

lo = BITX(*(data+j++), 7, 6);

usr/src/lib/libipmi/common/ipmi_util.c

284

tmp = BITX(*(data+j), 3, 0);

usr/src/lib/libipmi/common/ipmi_util.c

288

lo = BITX(*(data+j++), 7, 4);

usr/src/lib/libipmi/common/ipmi_util.c

289

tmp = BITX(*(data+j), 1, 0);

usr/src/lib/libipmi/common/ipmi_util.c

293

tmp = BITX(*(data+j++), 7, 2);

usr/src/lib/libipmi/common/ipmi_util.c

298

tmp = BITX(*(data+j), 5, 0);

usr/src/lib/libipmi/common/ipmi_util.c

302

tmp = BITX(*(data+j), 5, 0);

usr/src/lib/libipmi/common/ipmi_util.c

305

lo = BITX(*(data+j++), 7, 6);

usr/src/lib/libipmi/common/ipmi_util.c

306

tmp = BITX(*(data+j), 3, 0);

usr/src/uts/common/io/igb/igb_sensor.c

38

#define E1000_THMJT_TEMP(x) BITX(x, 8, 0)

usr/src/uts/common/io/igb/igb_sensor.c

39

#define E1000_THMJT_VALID(x) BITX(x, 31, 31)

usr/src/uts/common/io/igb/igb_sensor.c

47

#define IGB_NVM_ETS_CFG_NSENSORS(x) BITX(x, 2, 0)

usr/src/uts/common/io/igb/igb_sensor.c

48

#define IGB_NVM_ETS_CFG_TYPE(x) BITX(x, 5, 3)

usr/src/uts/common/io/igb/igb_sensor.c

51

#define IGB_NVM_ETS_SENSOR_LOC(x) BITX(x, 13, 10)

usr/src/uts/common/io/igb/igb_sensor.c

52

#define IGB_NVM_ETS_SENSOR_INDEX(x) BITX(x, 9, 8)

usr/src/uts/common/io/igb/igb_sensor.c

53

#define IGB_NVM_ETS_SENSOR_THRESH(x) BITX(x, 7, 0)

usr/src/uts/i86pc/io/immu_qinv.c

49

#define QINV_IQA_HEAD(QH) BITX((QH), 18, 4)

usr/src/uts/i86pc/sys/hpet_acpi.h

140

#define HPET_GCAP_VENDOR_ID(l) BITX(l, 31, 16)

usr/src/uts/i86pc/sys/hpet_acpi.h

141

#define HPET_GCAP_LEG_ROUTE_CAP(l) BITX(l, 15, 15)

usr/src/uts/i86pc/sys/hpet_acpi.h

142

#define HPET_GCAP_CNT_SIZE_CAP(l) BITX(l, 13, 13)

usr/src/uts/i86pc/sys/hpet_acpi.h

143

#define HPET_GCAP_NUM_TIM_CAP(l) BITX(l, 12, 8)

usr/src/uts/i86pc/sys/hpet_acpi.h

144

#define HPET_GCAP_REV_ID(l) BITX(l, 7, 0)

usr/src/uts/i86pc/sys/hpet_acpi.h

175

#define HPET_GCFR_LEG_RT_CNF_BITX(l) BITX(l, 1, 1)

usr/src/uts/i86pc/sys/hpet_acpi.h

176

#define HPET_GCFR_ENABLE_CNF_BITX(l) BITX(l, 0, 0)

usr/src/uts/i86pc/sys/hpet_acpi.h

181

#define HPET_GIS_T2_INT_STS(l) BITX(l, 2, 2)

usr/src/uts/i86pc/sys/hpet_acpi.h

182

#define HPET_GIS_T1_INT_STS(l) BITX(l, 1, 1)

usr/src/uts/i86pc/sys/hpet_acpi.h

183

#define HPET_GIS_T0_INT_STS(l) BITX(l, 0, 0)

usr/src/uts/i86pc/sys/hpet_acpi.h

184

#define HPET_GIS_TN_INT_STS(l, n) BITX(l, n, n)

usr/src/uts/i86pc/sys/hpet_acpi.h

212

#define HPET_TIMER_N_INT_TYPE_CNF(l) BITX(l, 1, 1)

usr/src/uts/i86pc/sys/hpet_acpi.h

213

#define HPET_TIMER_N_INT_ENB_CNF(l) BITX(l, 2, 2)

usr/src/uts/i86pc/sys/hpet_acpi.h

214

#define HPET_TIMER_N_TYPE_CNF(l) BITX(l, 3, 3)

usr/src/uts/i86pc/sys/hpet_acpi.h

215

#define HPET_TIMER_N_PER_INT_CAP(l) BITX(l, 4, 4)

usr/src/uts/i86pc/sys/hpet_acpi.h

216

#define HPET_TIMER_N_SIZE_CAP(l) BITX(l, 5, 5)

usr/src/uts/i86pc/sys/hpet_acpi.h

217

#define HPET_TIMER_N_VAL_SET_CNF(l) BITX(l, 6, 6)

usr/src/uts/i86pc/sys/hpet_acpi.h

218

#define HPET_TIMER_N_MODE32_CNF(l) BITX(l, 8, 8)

usr/src/uts/i86pc/sys/hpet_acpi.h

219

#define HPET_TIMER_N_INT_ROUTE_CNF(l) BITX(l, 13, 9)

usr/src/uts/i86pc/sys/hpet_acpi.h

220

#define HPET_TIMER_N_FSB_EN_CNF(l) BITX(l, 14, 14)

usr/src/uts/i86pc/sys/hpet_acpi.h

221

#define HPET_TIMER_N_FSB_INT_DEL_CAP(l) BITX(l, 15, 15)

usr/src/uts/i86pc/sys/immu.h

378

#define RDT_DLM(rdt) BITX((rdt), 10, 8)

usr/src/uts/i86xpv/os/xen_machdep.c

151

xenver[idx].xv_major = BITX(ver, 31, 16);

usr/src/uts/i86xpv/os/xen_machdep.c

152

xenver[idx].xv_minor = BITX(ver, 15, 0);

usr/src/uts/intel/io/amdnbtemp/amdnbtemp.c

57

#define AMDNBTEMP_TEMPREG_CURTMP(x) BITX(x, 31, 21)

usr/src/uts/intel/io/amdnbtemp/amdnbtemp.c

58

#define AMDNBTEMP_TEMPREG_TJSEL(x) BITX(x, 17, 16)

usr/src/uts/intel/io/imc/imc.h

106

#define IMC_MTR_CA_WIDTH(x) BITX(x, 1, 0)

usr/src/uts/intel/io/imc/imc.h

111

#define IMC_MTR_RA_WIDTH(x) BITX(x, 4, 2)

usr/src/uts/intel/io/imc/imc.h

116

#define IMC_MTR_DENSITY_IVY_BRD(x) BITX(x, 6, 5)

usr/src/uts/intel/io/imc/imc.h

117

#define IMC_MTR_DENSITY_SKX(x) BITX(x, 7, 5)

usr/src/uts/intel/io/imc/imc.h

119

#define IMC_MTR_WIDTH_IVB_HAS(x) BITX(x, 8, 7)

usr/src/uts/intel/io/imc/imc.h

120

#define IMC_MTR_WIDTH_BRD_SKX(x) BITX(x, 9, 8)

usr/src/uts/intel/io/imc/imc.h

122

#define IMC_MTR_DDR_RANKS(x) BITX(x, 13, 12)

usr/src/uts/intel/io/imc/imc.h

126

#define IMC_MTR_PRESENT_SNB_BRD(x) BITX(x, 14, 14)

usr/src/uts/intel/io/imc/imc.h

127

#define IMC_MTR_PRESENT_SKYLAKE(x) BITX(x, 15, 15)

usr/src/uts/intel/io/imc/imc.h

129

#define IMC_MTR_RANK_DISABLE(x) BITX(x, 19, 16)

usr/src/uts/intel/io/imc/imc.h

131

#define IMC_MTR_DDR4_ENABLE_HAS_BRD(x) BITX(x, 20, 20)

usr/src/uts/intel/io/imc/imc.h

132

#define IMC_MTR_HDRL_HAS_SKX(x) BITX(x, 21, 21)

usr/src/uts/intel/io/imc/imc.h

133

#define IMC_MTR_HDRL_PARITY_HAS_SKX(x) BITX(x, 22, 22)

usr/src/uts/intel/io/imc/imc.h

134

#define IMC_MTR_3DSRANKS_HAS_SKX(x) BITX(x, 24, 23)

usr/src/uts/intel/io/imc/imc.h

139

#define IMC_MC_MIRROR_SNB_BRD(x) BITX(x, 0, 0)

usr/src/uts/intel/io/imc/imc.h

205

#define IMC_SAD_DRAM_RULE_ENABLE(x) BITX(x, 0, 0)

usr/src/uts/intel/io/imc/imc.h

207

#define IMC_SAD_DRAM_INTERLEAVE_SNB_BRD(x) BITX(x, 1, 1)

usr/src/uts/intel/io/imc/imc.h

211

#define IMC_SAD_DRAM_INTERLEAVE_SKX(x) BITX(x, 2, 1)

usr/src/uts/intel/io/imc/imc.h

217

#define IMC_SAD_DRAM_ATTR_SNB_BRD(x) BITX(x, 3, 2)

usr/src/uts/intel/io/imc/imc.h

218

#define IMC_SAD_DRAM_ATTR_SKX(x) BITX(x, 4, 3)

usr/src/uts/intel/io/imc/imc.h

223

#define IMC_SAD_DRAM_MOD23_SKX(x) BITX(x, 6, 5)

usr/src/uts/intel/io/imc/imc.h

229

#define IMC_SAD_DRAM_LIMIT_SNB_BRD(x) BITX(x, 25, 6)

usr/src/uts/intel/io/imc/imc.h

230

#define IMC_SAD_DRAM_LIMIT_SKX(x) BITX(x, 26, 7)

usr/src/uts/intel/io/imc/imc.h

234

#define IMC_SAD_DRAM_A7_IVB_BRD(x) BITX(x, 26, 26)

usr/src/uts/intel/io/imc/imc.h

235

#define IMC_SAD_DRAM_MOD3_SKX(x) BITX(x, 27, 27)

usr/src/uts/intel/io/imc/imc.h

236

#define IMC_SAD_DRAM_MOD3_MODE_SKX(x) BITX(x, 31, 30)

usr/src/uts/intel/io/imc/imc.h

252

#define IMC_SAD_ILEAVE_SKX_LOCAL(x) BITX(x, 3, 3)

usr/src/uts/intel/io/imc/imc.h

253

#define IMC_SAD_ILEAVE_SKX_TARGET(x) BITX(x, 2, 0)

usr/src/uts/intel/io/imc/imc.h

284

#define IMC_TAD_LIMIT(x) BITX(x, 31, 12)

usr/src/uts/intel/io/imc/imc.h

288

#define IMC_TAD_SOCK_WAY(x) BITX(x, 11, 10)

usr/src/uts/intel/io/imc/imc.h

293

#define IMC_TAD_CHAN_WAY(x) BITX(x, 9, 8)

usr/src/uts/intel/io/imc/imc.h

294

#define IMC_TAD_TARG3(x) BITX(x, 7, 6)

usr/src/uts/intel/io/imc/imc.h

295

#define IMC_TAD_TARG2(x) BITX(x, 5, 4)

usr/src/uts/intel/io/imc/imc.h

296

#define IMC_TAD_TARG1(x) BITX(x, 3, 2)

usr/src/uts/intel/io/imc/imc.h

297

#define IMC_TAD_TARG0(x) BITX(x, 1, 0)

usr/src/uts/intel/io/imc/imc.h

304

#define IMC_TAD_BASE_BASE(x) BITX(x, 31, 12)

usr/src/uts/intel/io/imc/imc.h

307

#define IMC_TAD_BASE_CHAN_GRAN(x) BITX(x, 7, 6)

usr/src/uts/intel/io/imc/imc.h

312

#define IMC_TAD_BASE_SOCK_GRAN(x) BITX(x, 5, 4)

usr/src/uts/intel/io/imc/imc.h

318

#define IMC_TADCHAN_OFFSET_SNB_BRD(x) BITX(x, 25, 6)

usr/src/uts/intel/io/imc/imc.h

319

#define IMC_TADCHAN_OFFSET_SKX(x) BITX(x, 23, 4)

usr/src/uts/intel/io/imc/imc.h

325

#define IMC_TAD_SYSDEF_LOCKSTEP(x) BITX(x, 7, 7)

usr/src/uts/intel/io/imc/imc.h

326

#define IMC_TAD_SYSDEF2_SHIFTUP(x) BITX(x, 22, 22)

usr/src/uts/intel/io/imc/imc.h

327

#define IMC_TAD_SYSDEF2_CHANHASH(x) BITX(x, 21, 21)

usr/src/uts/intel/io/imc/imc.h

339

#define IMC_RIR_WAYNESS_ENABLED(x) BITX(x, 31, 31)

usr/src/uts/intel/io/imc/imc.h

340

#define IMC_RIR_WAYNESS_WAY(x) BITX(x, 29, 28)

usr/src/uts/intel/io/imc/imc.h

341

#define IMC_RIR_LIMIT_HAS_SKX(x) BITX(x, 11, 1)

usr/src/uts/intel/io/imc/imc.h

342

#define IMC_RIR_LIMIT_SNB_IVB(x) BITX(x, 10, 1)

usr/src/uts/intel/io/imc/imc.h

350

#define IMC_RIR_OFFSET_TARGET_BRD(x) BITX(x, 23, 20)

usr/src/uts/intel/io/imc/imc.h

351

#define IMC_RIR_OFFSET_TARGET(x) BITX(x, 19, 16)

usr/src/uts/intel/io/imc/imc.h

352

#define IMC_RIR_OFFSET_OFFSET_HAS_SKX(x) BITX(x, 15, 2)

usr/src/uts/intel/io/imc/imc.h

353

#define IMC_RIR_OFFSET_OFFSET_SNB_IVB(x) BITX(x, 14, 2)

usr/src/uts/intel/io/imc/imc.h

365

#define IMC_UBOX_CPUBUSNO_0(x) BITX(x, 7, 0)

usr/src/uts/intel/io/imc/imc.h

366

#define IMC_UBOX_CPUBUSNO_1(x) BITX(x, 15, 8)

usr/src/uts/intel/io/imc/imc.h

367

#define IMC_UBOX_CPUBUSNO_2(x) BITX(x, 23, 16)

usr/src/uts/intel/io/imc/imc.h

82

#define IMC_NODEID_IVY_BRD_UPPER(x) BITX(x, 3, 3)

usr/src/uts/intel/io/imc/imc.h

83

#define IMC_NODEID_IVY_BRD_LOWER(x) BITX(x, 1, 0)

usr/src/uts/intel/io/imc/imc.h

84

#define IMC_NODEID_IVY_BRD_HA(x) BITX(x, 2, 2)

usr/src/uts/intel/io/imc/imc.h

89

#define IMC_MCMTR_CLOSED_PAGE(x) BITX(x, 0, 0)

usr/src/uts/intel/io/imc/imc.h

90

#define IMC_MCMTR_LOCKSTEP(x) BITX(x, 1, 1)

usr/src/uts/intel/io/imc/imc.h

91

#define IMC_MCMTR_ECC_ENABLED(x) BITX(x, 2, 2)

usr/src/uts/intel/io/imc/imc.h

93

#define IMC_MCMTR_DDR4_HAS_BRD(x) BITX(x, 14, 14)

usr/src/uts/intel/io/vmm/intel/vmx.c

1877

inout->addrsize = 2 << BITX(inst_info, 9, 7);

usr/src/uts/intel/os/cpuid.c

1943

#define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)

usr/src/uts/intel/os/cpuid.c

1944

#define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)

usr/src/uts/intel/os/cpuid.c

1945

#define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)

usr/src/uts/intel/os/cpuid.c

1946

#define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)

usr/src/uts/intel/os/cpuid.c

1947

#define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)

usr/src/uts/intel/os/cpuid.c

1948

#define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)

usr/src/uts/intel/os/cpuid.c

1960

#define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)

usr/src/uts/intel/os/cpuid.c

1961

#define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)

usr/src/uts/intel/os/cpuid.c

1962

#define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)

usr/src/uts/intel/os/cpuid.c

1963

#define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)

usr/src/uts/intel/os/cpuid.c

1974

#define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)

usr/src/uts/intel/os/cpuid.c

1975

#define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)

usr/src/uts/intel/os/cpuid.c

1976

#define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)

usr/src/uts/intel/os/cpuid.c

1977

#define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)

usr/src/uts/intel/os/cpuid.c

1978

#define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)

usr/src/uts/intel/os/cpuid.c

1979

#define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)

usr/src/uts/intel/os/cpuid.c

1984

#define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)

usr/src/uts/intel/os/cpuid.c

1986

#define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)

usr/src/uts/intel/os/cpuid.c

1987

#define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)

usr/src/uts/intel/os/cpuid.c

1988

#define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)

usr/src/uts/intel/os/cpuid.c

1990

#define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)

usr/src/uts/intel/os/cpuid.c

1992

#define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)

usr/src/uts/intel/os/cpuid.c

2035

#define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)

usr/src/uts/intel/os/cpuid.c

2036

#define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)

usr/src/uts/intel/os/cpuid.c

2041

BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)

usr/src/uts/intel/os/cpuid.c

2464

nthreads = BITX(cpi->cpi_extd[8].cp_ecx, 7, 0) + 1;

usr/src/uts/intel/os/cpuid.c

2477

nthread_per_core = BITX(cpi->cpi_extd[0x1e].cp_ebx, 15, 8) + 1;

usr/src/uts/intel/os/cpuid.c

2499

*ncores = BITX(cpi->cpi_std[4].cp_eax, 31, 26) + 1;

usr/src/uts/intel/os/cpuid.c

2550

coreid_shift = BITX(cp->cp_eax, 4, 0);

usr/src/uts/intel/os/cpuid.c

2551

ncpu_per_core = BITX(cp->cp_ebx, 15, 0);

usr/src/uts/intel/os/cpuid.c

2554

chipid_shift = BITX(cp->cp_eax, 4, 0);

usr/src/uts/intel/os/cpuid.c

2555

ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);

usr/src/uts/intel/os/cpuid.c

2697

uint_t nthreads = BITX(cpi->cpi_extd[0x1e].cp_ebx, 15, 8) + 1;

usr/src/uts/intel/os/cpuid.c

2755

coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);

usr/src/uts/intel/os/cpuid.c

2789

uint_t nthreads = BITX(cpi->cpi_extd[0x1e].cp_ebx, 15, 8) + 1;

usr/src/uts/intel/os/cpuid.c

2809

cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;

usr/src/uts/intel/os/cpuid.c

2810

cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);

usr/src/uts/intel/os/cpuid.c

2818

BITX(cp->cp_ebx, 15, 8) + 1;

usr/src/uts/intel/os/cpuid.c

2819

cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0) +

usr/src/uts/intel/os/cpuid.c

2833

if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {

usr/src/uts/intel/os/cpuid.c

2835

cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,

usr/src/uts/intel/os/cpuid.c

2855

node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;

usr/src/uts/intel/os/cpuid.c

2864

if (BITX(nb_caps_reg, 30, 30) == 0)

usr/src/uts/intel/os/cpuid.c

3768

cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);

usr/src/uts/intel/os/cpuid.c

4580

x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);

usr/src/uts/intel/os/cpuid.c

4827

cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);

usr/src/uts/intel/os/cpuid.c

4828

cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);

usr/src/uts/intel/os/cpuid.c

5017

BITX(cp->cp_eax, 7, 0);

usr/src/uts/intel/os/cpuid.c

5031

if (BITX(cp->cp_eax, 31, 31) == 0) {

usr/src/uts/intel/os/cpuid.c

5037

if (BITX(cp->cp_ebx, 31, 31) == 0) {

usr/src/uts/intel/os/cpuid.c

5043

if (BITX(cp->cp_ecx, 31, 31) == 0) {

usr/src/uts/intel/os/cpuid.c

5049

if (BITX(cp->cp_edx, 31, 31) == 0) {

usr/src/uts/intel/os/cpuid.c

5402

BITX(cp->cp_ecx, 31, 24) << 16 |

usr/src/uts/intel/os/cpuid.c

5403

BITX(cp->cp_ecx, 23, 16) << 12 |

usr/src/uts/intel/os/cpuid.c

5404

BITX(cp->cp_ecx, 15, 8) << 8 |

usr/src/uts/intel/os/cpuid.c

5405

BITX(cp->cp_ecx, 7, 0);

usr/src/uts/intel/os/cpuid.c

5614

switch (BITX(cpi->cpi_brandid, 7, 5)) {

usr/src/uts/intel/os/cpuid.c

6632

dtlb_nent = BITX(cp->cp_ebx, 27, 16);

usr/src/uts/intel/os/cpuid.c

6639

dtlb_nent = BITX(cp->cp_eax, 27, 16);

usr/src/uts/intel/os/cpuid.c

6659

dtlb_nent = BITX(cp->cp_ebx, 23, 16);

usr/src/uts/intel/os/cpuid.c

6662

dtlb_nent = BITX(cp->cp_eax, 23, 16);

usr/src/uts/intel/os/cpuid.c

7390

BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));

usr/src/uts/intel/os/cpuid.c

7392

BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));

usr/src/uts/intel/os/cpuid.c

7407

if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)

usr/src/uts/intel/os/cpuid.c

7412

add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),

usr/src/uts/intel/os/cpuid.c

7419

BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));

usr/src/uts/intel/os/cpuid.c

7421

BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));

usr/src/uts/intel/os/cpuid.c

7430

BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),

usr/src/uts/intel/os/cpuid.c

7431

BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));

usr/src/uts/intel/os/cpuid.c

7438

BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),

usr/src/uts/intel/os/cpuid.c

7439

BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));

usr/src/uts/intel/os/cpuid.c

7447

if (BITX(cp->cp_eax, 31, 16) == 0)

usr/src/uts/intel/os/cpuid.c

7449

BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));

usr/src/uts/intel/os/cpuid.c

7452

BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));

usr/src/uts/intel/os/cpuid.c

7454

BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));

usr/src/uts/intel/os/cpuid.c

7459

if (BITX(cp->cp_ebx, 31, 16) == 0) {

usr/src/uts/intel/os/cpuid.c

7461

BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));

usr/src/uts/intel/os/cpuid.c

7464

BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));

usr/src/uts/intel/os/cpuid.c

7466

BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));

usr/src/uts/intel/os/cpuid.c

7470

BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),

usr/src/uts/intel/os/cpuid.c

7471

BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));

usr/src/uts/intel/os/cpuid.c

7638

"generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));

usr/src/uts/intel/os/cpuid.c

7824

if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&

usr/src/uts/intel/os/cpuid.c

7825

(size = BITX(cp->cp_ecx, 31, 16)) != 0) {

usr/src/uts/intel/os/cpuid.c

7834

*ip = BITX(cp->cp_ecx, 7, 0);

usr/src/uts/intel/os/cpuid_subr.c

902

idx = BITX(cp.cp_ebx, 31, 28);

usr/src/uts/intel/os/cpuid_subr.c

908

if (BITX(val, 8, 8)) {