usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
123
REG_WR(pdev, rv2p.rv2p_instr_high, *rv2p_code);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
125
REG_WR(pdev, rv2p.rv2p_instr_low, *rv2p_code);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
131
REG_WR(pdev, rv2p.rv2p_proc1_addr_cmd, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
136
REG_WR(pdev, rv2p.rv2p_proc2_addr_cmd, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
143
REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC1_RESET);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_cpu.c
147
REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC2_RESET);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
100
REG_WR(pdev, pci_config.pcicfg_reg_window, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
137
REG_WR(pdev, context.ctx_ctx_data, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
138
REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_WRITE_REQ);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
156
REG_WR(pdev, context.ctx_data_adr, offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
157
REG_WR(pdev, context.ctx_data, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
193
REG_WR(pdev, context.ctx_ctx_ctrl, offset | CTX_CTX_CTRL_READ_REQ);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
213
REG_WR(pdev, context.ctx_data_adr, offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
240
REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
247
REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
276
REG_WR(pdev, pci_config.pcicfg_int_ack_cmd, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
282
REG_WR(pdev, hc.hc_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
313
REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
322
REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
332
REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
355
REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
398
REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
40
REG_WR(pdev, emac.emac_mac_match[addr_idx*2], val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
407
REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
417
REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
44
REG_WR(pdev, emac.emac_mac_match[addr_idx*2+1], val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
440
REG_WR(pdev, pci_config.pcicfg_reg_window_address, reg_offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
441
REG_WR(pdev, pci_config.pcicfg_reg_window, *data_ptr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
71
REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_misc.c
99
REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
187
REG_WR(pdev, nvm.nvm_sw_arb, NVM_SW_ARB_ARB_REQ_SET2);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
227
REG_WR(pdev, nvm.nvm_sw_arb, NVM_SW_ARB_ARB_REQ_CLR2);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
266
REG_WR(pdev, misc.misc_cfg, val | MISC_CFG_NVM_WR_EN_PCI);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
272
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
273
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_WREN |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
315
REG_WR(pdev, misc.misc_cfg, val & ~MISC_CFG_NVM_WR_EN);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
324
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
325
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_WRDI |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
367
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
391
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
426
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
429
REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
432
REG_WR(pdev, nvm.nvm_command, cmd_flags);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
499
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
504
REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
508
REG_WR(pdev, nvm.nvm_command, cmd_flags);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
583
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
593
REG_WR(pdev, nvm.nvm_write, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
597
REG_WR(pdev, nvm.nvm_addr, offset & NVM_ADDR_NVM_ADDR_VALUE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
601
REG_WR(pdev, nvm.nvm_command, cmd_flags);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
647
REG_WR(pdev, nvm.nvm_cfg3, 0x57848353);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
648
REG_WR(pdev, nvm.nvm_read, 0);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
649
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DONE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
650
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_DOIT |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
662
REG_WR(pdev, nvm.nvm_cfg3, orig);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
706
REG_WR(pdev, nvm.nvm_addr, NVM_ADDR_NVM_ADDR_VALUE_EECLK_TE |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
711
REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_EECLK_TE |
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
717
REG_WR(pdev, nvm.nvm_cfg1, val | NVM_CFG1_BITBANG_MODE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
724
REG_WR(pdev, nvm.nvm_write, 0);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
729
REG_WR(pdev, nvm.nvm_write, bit);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
731
REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE | bit);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
734
REG_WR(pdev, nvm.nvm_write, 0);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
746
REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_SCLK_TE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
748
REG_WR(pdev, nvm.nvm_write, 0);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
751
REG_WR(pdev, nvm.nvm_write, NVM_WRITE_NVM_WRITE_VALUE_CS_B_TE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
776
REG_WR(pdev, nvm.nvm_cfg1, idx & ~NVM_CFG1_BITBANG_MODE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
907
REG_WR(pdev, nvm.nvm_cfg1, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
908
REG_WR(pdev, nvm.nvm_cfg2, cfg_table[idx].config2);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
909
REG_WR(pdev, nvm.nvm_cfg3, cfg_table[idx].config3);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
910
REG_WR(pdev, nvm.nvm_write1, cfg_table[idx].write1);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_nvram.c
964
REG_WR(pdev, nvm.nvm_command, NVM_COMMAND_RST);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1187
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
126
REG_WR(pdev, emac.emac_mdio_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
137
REG_WR(pdev, emac.emac_mdio_comm, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1555
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1692
REG_WR(pdev, misc.misc_gp_hw_ctl0,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
177
REG_WR(pdev, emac.emac_mdio_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1770
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1884
REG_WR(pdev, emac.emac_tx_lengths, 0x26ff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1984
REG_WR(pdev, emac.emac_tx_lengths, 0x26ff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
1989
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2016
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2042
REG_WR(pdev, hc.hc_attn_bits_enable, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2689
REG_WR(pdev, emac.emac_rx_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2700
REG_WR(pdev, emac.emac_tx_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2941
REG_WR(pdev, emac.emac_tx_lengths, 0x2620);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
2947
REG_WR(pdev, emac.emac_tx_lengths, 0x26ff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3010
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3013
REG_WR(pdev, emac.emac_status, EMAC_STATUS_LINK_CHANGE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3018
REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_MI_INT);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3022
REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3032
REG_WR(pdev, hc.hc_attn_bits_enable, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3955
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
3964
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
53
REG_WR(pdev, emac.emac_mdio_mode, tmp);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
632
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
65
REG_WR(pdev, emac.emac_mdio_comm, tmp);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_phy.c
95
REG_WR(pdev, emac.emac_mdio_mode, tmp);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1452
REG_WR(pdev, csch.csch_ch_ftq_ctl, 8 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1459
REG_WR(pdev, rdma.rdma_ftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1461
REG_WR(pdev, rlup.rlup_ftq_ctl, 8 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1463
REG_WR(pdev, rv2p.rv2p_pftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1464
REG_WR(pdev, rv2p.rv2p_tftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1465
REG_WR(pdev, rv2p.rv2p_mftq_ctl, 4 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1481
REG_WR(pdev, tbdr.tbdr_ftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1483
REG_WR(pdev, tdma.tdma_ftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1490
REG_WR(pdev, tsch.tsch_ftq_ctl, 2 << 12);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1513
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1518
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1527
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1541
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1552
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1596
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1611
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1614
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1617
REG_WR(pdev, pci.pci_msix_tbl_off_bir, PCI_GRC_WINDOW2_BASE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1618
REG_WR(pdev, pci.pci_msix_pba_off_bit, PCI_GRC_WINDOW3_BASE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1668
REG_WR(pdev, hc.hc_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1674
REG_WR(pdev, hc.hc_attn_bits_enable, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1677
REG_WR(pdev, hc.hc_status_addr_l, pdev->vars.status_phy.as_u32.low);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1678
REG_WR(pdev, hc.hc_status_addr_h, pdev->vars.status_phy.as_u32.high);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1680
REG_WR(pdev, hc.hc_statistics_addr_l, pdev->vars.stats_phy.as_u32.low);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1681
REG_WR(pdev, hc.hc_statistics_addr_h, pdev->vars.stats_phy.as_u32.high);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1683
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1688
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1693
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1698
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1703
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1708
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1713
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1727
REG_WR(pdev, hc.hc_stats_ticks, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1729
REG_WR(pdev, hc.hc_stat_collect_ticks, 0xbb8); /* 3ms */
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1730
REG_WR(pdev, hc.hc_command, HC_COMMAND_CLR_STAT_NOW);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1748
REG_WR(pdev, hc.hc_tx_quick_cons_trip_1, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1749
REG_WR(pdev, hc.hc_tx_ticks_1, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1750
REG_WR(pdev, hc.hc_rx_quick_cons_trip_1, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1751
REG_WR(pdev, hc.hc_rx_ticks_1, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1752
REG_WR(pdev, hc.hc_comp_prod_trip_1, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1753
REG_WR(pdev, hc.hc_com_ticks_1, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1754
REG_WR(pdev, hc.hc_cmd_ticks_1, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1755
REG_WR(pdev, hc.hc_periodic_ticks_1, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1763
REG_WR(pdev, hc.hc_tx_quick_cons_trip_2, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1764
REG_WR(pdev, hc.hc_tx_ticks_2, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1765
REG_WR(pdev, hc.hc_rx_quick_cons_trip_2, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1766
REG_WR(pdev, hc.hc_rx_ticks_2, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1767
REG_WR(pdev, hc.hc_comp_prod_trip_2, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1768
REG_WR(pdev, hc.hc_com_ticks_2, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1769
REG_WR(pdev, hc.hc_cmd_ticks_2, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1770
REG_WR(pdev, hc.hc_periodic_ticks_2, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1778
REG_WR(pdev, hc.hc_tx_quick_cons_trip_3, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1779
REG_WR(pdev, hc.hc_tx_ticks_3, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1780
REG_WR(pdev, hc.hc_rx_quick_cons_trip_3, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1781
REG_WR(pdev, hc.hc_rx_ticks_3, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1782
REG_WR(pdev, hc.hc_comp_prod_trip_3, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1783
REG_WR(pdev, hc.hc_com_ticks_3, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1784
REG_WR(pdev, hc.hc_cmd_ticks_3, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1785
REG_WR(pdev, hc.hc_periodic_ticks_3, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1793
REG_WR(pdev, hc.hc_tx_quick_cons_trip_4, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1794
REG_WR(pdev, hc.hc_tx_ticks_4, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1795
REG_WR(pdev, hc.hc_rx_quick_cons_trip_4, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1796
REG_WR(pdev, hc.hc_rx_ticks_4, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1797
REG_WR(pdev, hc.hc_comp_prod_trip_4, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1798
REG_WR(pdev, hc.hc_com_ticks_4, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1799
REG_WR(pdev, hc.hc_cmd_ticks_4, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1800
REG_WR(pdev, hc.hc_periodic_ticks_4, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1808
REG_WR(pdev, hc.hc_tx_quick_cons_trip_5, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1809
REG_WR(pdev, hc.hc_tx_ticks_5, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1810
REG_WR(pdev, hc.hc_rx_quick_cons_trip_5, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1811
REG_WR(pdev, hc.hc_rx_ticks_5, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1812
REG_WR(pdev, hc.hc_comp_prod_trip_5, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1813
REG_WR(pdev, hc.hc_com_ticks_5, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1814
REG_WR(pdev, hc.hc_cmd_ticks_5, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1815
REG_WR(pdev, hc.hc_periodic_ticks_5, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1823
REG_WR(pdev, hc.hc_tx_quick_cons_trip_6, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1824
REG_WR(pdev, hc.hc_tx_ticks_6, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1825
REG_WR(pdev, hc.hc_rx_quick_cons_trip_6, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1826
REG_WR(pdev, hc.hc_rx_ticks_6, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1827
REG_WR(pdev, hc.hc_comp_prod_trip_6, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1828
REG_WR(pdev, hc.hc_com_ticks_6, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1829
REG_WR(pdev, hc.hc_cmd_ticks_6, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1830
REG_WR(pdev, hc.hc_periodic_ticks_6, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1838
REG_WR(pdev, hc.hc_tx_quick_cons_trip_7, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1839
REG_WR(pdev, hc.hc_tx_ticks_7, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1840
REG_WR(pdev, hc.hc_rx_quick_cons_trip_7, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1841
REG_WR(pdev, hc.hc_rx_ticks_7, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1842
REG_WR(pdev, hc.hc_comp_prod_trip_7, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1843
REG_WR(pdev, hc.hc_com_ticks_7, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1844
REG_WR(pdev, hc.hc_cmd_ticks_7, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1845
REG_WR(pdev, hc.hc_periodic_ticks_7, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1853
REG_WR(pdev, hc.hc_tx_quick_cons_trip_8, pdev->params.psb_tx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1854
REG_WR(pdev, hc.hc_tx_ticks_8, pdev->params.psb_tx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1855
REG_WR(pdev, hc.hc_rx_quick_cons_trip_8, pdev->params.psb_rx_cons_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1856
REG_WR(pdev, hc.hc_rx_ticks_8, pdev->params.psb_rx_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1857
REG_WR(pdev, hc.hc_comp_prod_trip_8, pdev->params.psb_comp_prod_trip);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1858
REG_WR(pdev, hc.hc_com_ticks_8, pdev->params.psb_com_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1859
REG_WR(pdev, hc.hc_cmd_ticks_8, pdev->params.psb_cmd_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1860
REG_WR(pdev, hc.hc_periodic_ticks_8, pdev->params.psb_period_ticks);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1884
REG_WR(pdev, hc.hc_sb_haddr_0_lo, pdev->vars.status_phy.as_u32.low);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1885
REG_WR(pdev, hc.hc_sb_haddr_0_hi, pdev->vars.status_phy.as_u32.high);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1887
REG_WR(pdev, hc.hc_sb_select_0_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1890
REG_WR(pdev, hc.hc_sb_select_1_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1893
REG_WR(pdev, hc.hc_sb_select_2_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1896
REG_WR(pdev, hc.hc_sb_select_3_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1899
REG_WR(pdev, hc.hc_sb_select_4_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1902
REG_WR(pdev, hc.hc_sb_select_5_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1905
REG_WR(pdev, hc.hc_sb_select_6_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1908
REG_WR(pdev, hc.hc_sb_select_7_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1911
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1914
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1917
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1920
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1923
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1926
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1929
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1932
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
1935
REG_WR(pdev, hc.hc_sb_select_8_config,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2002
REG_WR(pdev, emac.emac_mode, EMAC_MODE_EXT_LINK_POL | EMAC_MODE_PORT_GMII);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2041
REG_WR(pdev, dma.dma_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2047
REG_WR(pdev, tdma.tdma_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2054
REG_WR(pdev, pci.pci_config_2, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2065
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2091
REG_WR(pdev, mq.mq_map_l4_0, 0x8001c1b9);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2095
REG_WR(pdev, mq.mq_map_l4_0, 0x80010db9);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2096
REG_WR(pdev, mq.mq_map_l4_4, 0x82810eb2);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2097
REG_WR(pdev, mq.mq_map_l4_5, 0x8f0113b4);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2169
REG_WR(pdev, mq.mq_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2174
REG_WR(pdev, mq.mq_knl_byp_wind_start, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2175
REG_WR(pdev, mq.mq_knl_wind_end, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2181
REG_WR(pdev, tbdr.tbdr_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2189
REG_WR(pdev, emac.emac_rx_mtu_size, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
223
REG_WR(pdev, context.ctx_virt_addr, 0x00);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
224
REG_WR(pdev, context.ctx_page_tbl, pcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2300
REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_MI_INT);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2304
REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2308
REG_WR(pdev, emac.emac_attention_ena, EMAC_ATTENTION_ENA_LINK);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2312
REG_WR(pdev, emac.emac_mdio_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
234
REG_WR(pdev, context.ctx_virt_addr, vcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
235
REG_WR(pdev, context.ctx_page_tbl, pcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2357
REG_WR(pdev, mq.mq_knl_cmd_mask1, KNL_L5_MASK(sq_pidx));
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2362
REG_WR(pdev, mq.mq_knl_byp_cmd_mask1, KNL_L5_MASK(cq_cidx)|
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2365
REG_WR(pdev, mq.mq_knl_byp_write_mask1, KNL_L5_MASK(cq_cidx)|
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2370
REG_WR(pdev, mq.mq_knl_cmd_mask1, KNL_L5_MASK(cq_cidx)|
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2373
REG_WR(pdev, mq.mq_knl_write_mask1, KNL_L5_MASK(cq_cidx)|
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2380
REG_WR(pdev, mq.mq_knl_cmd_mask2, KNL_L4_MASK(host_bseq));
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2385
REG_WR(pdev, mq.mq_knl_rx_v2p_mask2, KNL_L4_MASK(host_bseq));
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2412
REG_WR(pdev, rv2p.rv2p_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2494
REG_WR(pdev, misc.misc_enable_set_bits, 0x15ffffff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2521
REG_WR(pdev, hc.hc_command, HC_COMMAND_COAL_NOW_WO_INT);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
2541
REG_WR(pdev, hc.hc_command, HC_COMMAND_COAL_NOW);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
270
REG_WR(pdev, context.ctx_virt_addr, 0x00);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
271
REG_WR(pdev, context.ctx_page_tbl, vcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
281
REG_WR(pdev, context.ctx_virt_addr, vcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
282
REG_WR(pdev, context.ctx_page_tbl, vcid_addr);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
309
REG_WR(pdev, context.ctx_command, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
329
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
333
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
337
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
382
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
450
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
478
REG_WR(pdev, misc.misc_new_core_ctl, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
552
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
595
REG_WR(pdev, misc.misc_command, MISC_COMMAND_SW_RESET);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
617
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
638
REG_WR(pdev, tsch.tsch_ctx_access_cfg, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
647
REG_WR(pdev, misc.misc_new_core_ctl, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
658
REG_WR(pdev, mq.mq_config, val | MQ_CONFIG_HALT_DIS);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
686
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
691
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
695
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
698
REG_WR(pdev,
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
701
REG_WR(pdev, pci.pci_msix_tbl_off_bir, PCI_GRC_WINDOW2_BASE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
702
REG_WR(pdev, pci.pci_msix_pba_off_bit, PCI_GRC_WINDOW3_BASE);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
709
REG_WR(pdev, misc.misc_eco_hw_ctl, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
715
REG_WR(pdev, misc.misc_eco_hw_ctl, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
721
REG_WR(pdev, pci.pci_grc_window_addr, pdev->hw_info.shmem_base & ~0x7fff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
729
REG_WR(pdev, misc.misc_vreg_control, 0x000000fa);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
735
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
748
REG_WR(pdev, emac.emac_backoff_seed, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
964
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
972
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_hw_reset.c
980
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2336
REG_WR(pdev, emac.emac_multicast_hash[idx], hash_reg[idx]);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2432
REG_WR(pdev, emac.emac_multicast_hash[idx], 0xffffffff);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2443
REG_WR(pdev, emac.emac_multicast_hash[idx], 0);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2454
REG_WR(pdev, emac.emac_rx_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2489
REG_WR(pdev, rpm.rpm_sort_user0, 0x00000000);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2490
REG_WR(pdev, rpm.rpm_sort_user0, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2496
REG_WR(pdev, rpm.rpm_sort_user0, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2502
REG_WR(pdev, rpm.rpm_sort_user1, 0x00000000);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2503
REG_WR(pdev, rpm.rpm_sort_user1, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2509
REG_WR(pdev, rpm.rpm_sort_user1, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2515
REG_WR(pdev, rpm.rpm_sort_user2, 0x00000000);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2516
REG_WR(pdev, rpm.rpm_sort_user2, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2522
REG_WR(pdev, rpm.rpm_sort_user2, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2528
REG_WR(pdev, rpm.rpm_sort_user3, 0x00000000);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2529
REG_WR(pdev, rpm.rpm_sort_user3, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2535
REG_WR(pdev, rpm.rpm_sort_user3, sort_mode);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
2718
REG_WR(pdev, hc.hc_command, HC_COMMAND_STATS_NOW);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3511
REG_WR(pdev, rpm.rpm_acpi_byte_enable_ctrl, RPM_ACPI_BYTE_ENABLE_CTRL_INIT);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3552
REG_WR(pdev, rpm.rpm_acpi_pattern_len0, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3579
REG_WR(pdev, rpm.rpm_acpi_pattern_len1, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3604
REG_WR(pdev, rpm.rpm_acpi_data, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3610
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3622
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3687
REG_WR(pdev, rpm.rpm_acpi_data, (prev_val << 16) | (val >> 16));
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3690
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3983
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
3988
REG_WR(pdev, rpm.rpm_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4038
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4056
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4069
REG_WR(pdev, rpm.rpm_config, val & ~RPM_CONFIG_ACPI_ENA);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4088
REG_WR(pdev, rpm.rpm_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4092
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4145
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4151
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4159
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4173
REG_WR(pdev, misc.misc_spio, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4369
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4376
REG_WR(
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4868
REG_WR(pdev, rlup.rlup_rss_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4874
REG_WR(pdev, rlup.rlup_rss_key1, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4880
REG_WR(pdev, rlup.rlup_rss_key2, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4886
REG_WR(pdev, rlup.rlup_rss_key3, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4892
REG_WR(pdev, rlup.rlup_rss_key4, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4898
REG_WR(pdev, rlup.rlup_ipv6_rss_key5, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4904
REG_WR(pdev, rlup.rlup_ipv6_rss_key6, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4910
REG_WR(pdev, rlup.rlup_ipv6_rss_key7, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4916
REG_WR(pdev, rlup.rlup_ipv6_rss_key8, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4922
REG_WR(pdev, rlup.rlup_ipv6_rss_key9, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
4928
REG_WR(pdev, rlup.rlup_ipv6_rss_key10, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5069
REG_WR(pdev, rlup.rlup_rss_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5075
REG_WR(pdev, rlup.rlup_rss_key1, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5081
REG_WR(pdev, rlup.rlup_rss_key2, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5087
REG_WR(pdev, rlup.rlup_rss_key3, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5093
REG_WR(pdev, rlup.rlup_rss_key4, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5099
REG_WR(pdev, rlup.rlup_ipv6_rss_key5, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5105
REG_WR(pdev, rlup.rlup_ipv6_rss_key6, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5111
REG_WR(pdev, rlup.rlup_ipv6_rss_key7, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5117
REG_WR(pdev, rlup.rlup_ipv6_rss_key8, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5123
REG_WR(pdev, rlup.rlup_ipv6_rss_key9, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5129
REG_WR(pdev, rlup.rlup_ipv6_rss_key10, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5265
REG_WR(pdev, rlup.rlup_rss_config, val);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/bnx_lm_main.c
5314
REG_WR(pdev,pci_config.pcicfg_device_control,pci_devctl);
usr/src/uts/common/io/bnx/570x/driver/common/lmdev/lm5706.h
1695
#define TRIGGER(_pdev, _val) REG_WR(_pdev, misc.misc_id, _val)
usr/src/uts/common/io/bnx/bnxint.c
212
REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd,
usr/src/uts/common/io/bnx/bnxint.c
231
REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd, value32);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1016
REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1018
REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
12298
REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
12303
REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1240
REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1243
REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1249
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1251
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1254
REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13576
REG_WR(cb, sync_offset, media_types);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13722
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1374
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13786
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1381
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13811
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1383
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13830
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1385
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13856
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13871
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1389
REG_WR(cb, PBF_REG_ETS_ENABLED, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1392
REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13921
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13936
REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13939
REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13943
REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13989
REG_WR(cb, GRCBASE_MISC +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
13993
REG_WR(cb, GRCBASE_MISC +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1400
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14020
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14024
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1403
REG_WR(cb, PBF_REG_COS0_UPPER_BOUND,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14043
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14047
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1405
REG_WR(cb, PBF_REG_COS1_UPPER_BOUND,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14051
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14056
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14067
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14086
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14230
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14234
REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14235
REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14261
REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14303
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14305
REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14306
REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14313
REG_WR(cb, xmac_base + XMAC_REG_CTRL,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14336
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1434
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1435
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1437
REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14373
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1438
REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14526
REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1455
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1459
REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1461
REG_WR(cb, PBF_REG_ETS_ENABLED, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1463
REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1466
REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1476
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14861
REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14864
REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14866
REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14882
REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
14967
REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15084
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15097
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15155
REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15156
REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1522
REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1523
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1524
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1530
REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1531
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1532
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1536
REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1541
REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15498
REG_WR(cb, sync_offset, vars->aeu_int_mask);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15511
REG_WR(cb, offset, aeu_mask);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
15516
REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1633
REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1675
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1678
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1717
REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1719
REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1721
REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1741
REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1751
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1755
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1761
REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1794
REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1800
REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1802
REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1804
REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1808
REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR0,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1813
REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR1,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1821
REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1830
REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1835
REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1866
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1870
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1876
REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1879
REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1882
REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1887
REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1892
REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1896
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1900
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1919
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1921
REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1929
REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1951
REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1957
REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1960
REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1961
REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1966
REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1969
REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1976
REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1977
REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1979
REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
1994
REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2016
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2020
REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2026
REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2027
REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2037
REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2038
REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2049
REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2051
REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2056
REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2135
REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2145
REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2148
REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2149
REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2150
REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2153
REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2160
REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2161
REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2166
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2170
REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2173
REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2344
REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2354
REG_WR(cb, params->shmem_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2409
REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2411
REG_WR(cb, port ? NIG_REG_LLFC_OUT_EN_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2413
REG_WR(cb, port ? NIG_REG_LLFC_ENABLE_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2415
REG_WR(cb, port ? NIG_REG_PAUSE_ENABLE_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2418
REG_WR(cb, port ? NIG_REG_PPP_ENABLE_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2421
REG_WR(cb, port ? NIG_REG_LLH1_XCM_MASK :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2424
REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2428
REG_WR(cb, port ? NIG_REG_XCM1_OUT_EN :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2432
REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2443
REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2447
REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2451
REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2505
REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2664
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2669
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2673
REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2688
REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2689
REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2690
REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2696
REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2697
REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2698
REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2699
REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2700
REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2701
REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2747
REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2771
REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2773
REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2780
REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2782
REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2794
REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2799
REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2801
REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2804
REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2872
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2879
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2894
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2908
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2915
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2933
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2964
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
2986
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3044
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3065
REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3195
REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3245
REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3262
REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3286
REG_WR(cb, params->shmem2_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3390
REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3394
REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3401
REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3425
REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
351
REG_WR(cb, reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
360
REG_WR(cb, reg, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3613
REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3614
REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3616
REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3619
REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3631
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3633
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3637
REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3652
REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3653
REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3670
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3672
REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
389
REG_WR(cb, params->lfa_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
3924
REG_WR(cb, params->shmem2_base +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
510
REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
5148
REG_WR(cb, MISC_REG_WC0_RESET, 0xE);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
5150
REG_WR(cb, MISC_REG_WC0_RESET, 0xF);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
5157
REG_WR(cb, MISC_REG_WC0_RESET, 0x3FF);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
532
REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
536
REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
585
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
594
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
596
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
600
REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
604
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
605
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
606
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
608
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
609
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
610
REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
612
REG_WR(cb, PBF_REG_ETS_ENABLED, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
616
REG_WR(cb, PBF_REG_COS0_WEIGHT, 0x2710);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
617
REG_WR(cb, PBF_REG_COS1_WEIGHT, 0x2710);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
619
REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
620
REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
622
REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
670
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
672
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
674
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
676
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
6777
REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
678
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
680
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
684
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
686
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
688
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
6939
REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
6960
REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
70
#define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7009
REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7010
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7041
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7042
REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7062
REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7067
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7069
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7074
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7088
REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7092
REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7095
REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7098
REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7100
REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7113
REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7115
REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7117
REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
712
REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
713
REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
715
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
716
REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
721
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
728
REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
729
REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7317
REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
732
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
734
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7364
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7368
REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7381
REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7383
REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7434
REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7436
REG_WR(cb, MISC_REG_CPMU_LP_DR_ENABLE, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7437
REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 +
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
745
REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
747
REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7478
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
749
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7511
REG_WR(cb, addr, val);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7570
REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
758
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
760
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
762
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
764
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
766
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
768
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
771
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7711
REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
772
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
773
REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
7803
REG_WR(cb, ver_addr, spirom_ver);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
806
REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
832
REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
835
REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
840
REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
843
REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
845
REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
849
REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
852
REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
866
REG_WR(cb, base_weight + (0x4 * i), 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9121
REG_WR(cb, sync_offset, media_types);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
933
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
936
REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
939
REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
943
REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9526
REG_WR(cb, MISC_REG_WC0_RESET, 0x0c0e);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9529
REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 1);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9530
REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c
9531
REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_common.h
51
REG_WR(pdev, addr + (i * 4), data[i]);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
210
REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
234
REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
259
REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
260
REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
261
REG_WR(pdev, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
262
REG_WR(pdev, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
292
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init.h
303
REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
275
REG_WR(pdev, addr, op->write.val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
43
REG_WR(pdev, addr + i*4, data[i]);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
519
REG_WR(pdev, read_arb_addr[i].l, read_arb_data[i][r_order].l);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
520
REG_WR(pdev, read_arb_addr[i].add,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
522
REG_WR(pdev, read_arb_addr[i].ubound,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
530
REG_WR(pdev, write_arb_addr[i].l,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
533
REG_WR(pdev, write_arb_addr[i].add,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
536
REG_WR(pdev, write_arb_addr[i].ubound,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
541
REG_WR(pdev, write_arb_addr[i].l,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
545
REG_WR(pdev, write_arb_addr[i].add,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
549
REG_WR(pdev, write_arb_addr[i].ubound,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
557
REG_WR(pdev, PXP2_REG_PSWRQ_BW_RD, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
562
REG_WR(pdev, PXP2_REG_PSWRQ_BW_WR, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
564
REG_WR(pdev, PXP2_REG_RQ_WR_MBS0, w_order);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
565
REG_WR(pdev, PXP2_REG_RQ_WR_MBS1, w_order);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
566
REG_WR(pdev, PXP2_REG_RQ_RD_MBS0, r_order);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
567
REG_WR(pdev, PXP2_REG_RQ_RD_MBS1, r_order);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
570
REG_WR(pdev, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
573
REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
575
REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
577
REG_WR(pdev, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
589
REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
592
REG_WR(pdev, PXP2_REG_WR_DMAE_MPS, 2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
595
REG_WR(pdev, PXP2_REG_WR_HC_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
596
REG_WR(pdev, PXP2_REG_WR_USDM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
597
REG_WR(pdev, PXP2_REG_WR_CSDM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
598
REG_WR(pdev, PXP2_REG_WR_TSDM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
599
REG_WR(pdev, PXP2_REG_WR_XSDM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
600
REG_WR(pdev, PXP2_REG_WR_QM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
601
REG_WR(pdev, PXP2_REG_WR_TM_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
602
REG_WR(pdev, PXP2_REG_WR_SRC_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
603
REG_WR(pdev, PXP2_REG_WR_DBG_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
604
REG_WR(pdev, PXP2_REG_WR_CDU_MPS, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
612
REG_WR(pdev, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
758
REG_WR(pdev, start_reg + PDEV_FUNC(pdev)*4,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
780
REG_WR(pdev, start_reg, (ilt_start + ilt_cli->start));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
781
REG_WR(pdev, end_reg, (ilt_start + ilt_cli->end));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
847
REG_WR(pdev, psz_reg, ILOG2(ilt_cli->page_size >> 12));
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
888
REG_WR(pdev, QM_REG_CONNNUM_0 + port*4,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
903
REG_WR(pdev, base_reg + i*4,
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_init_ops.h
951
REG_WR(pdev, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_sp_verbs.c
1118
REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/ecore_sp_verbs.c
3675
REG_WR(pdev, MC_HASH_OFFSET(pdev, i), mc_filter[i]);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/bnxe_hw_debug.c
104
REG_WR(pdev,TM_REG_EN_LINEAR1_TIMER, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/bnxe_hw_debug.c
134
REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/bnxe_hw_debug.c
137
REG_WR(pdev, TM_REG_EN_LINEAR1_TIMER,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/bnxe_hw_debug.c
208
REG_WR(pdev,PXP2_REG_RQ_HOQ_RAM_RD_REQ,vq);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/bnxe_hw_debug.c
84
REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_dcbx.c
4254
REG_WR(pdev, (admin_mib_offset + i) , *buff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_dcbx.c
4439
REG_WR(pdev, (offset + i) , *buff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_dcbx.c
4487
REG_WR(pdev, (offest+ i) , *buff);//Change to write
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_devinfo.c
607
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_dmae.c
808
REG_WR( pdev,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_dmae.c
813
REG_WR(pdev, lm_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
106
REG_WR(pdev, PXP_REG_HST_DISCARD_DOORBELLS, enable_bit);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
109
REG_WR(pdev, PXP_REG_HST_DISCARD_INTERNAL_WRITES, enable_bit);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
116
REG_WR(pdev, IGU_REG_BLOCK_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
129
REG_WR(pdev, PXP2_REG_RD_START_INIT, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
130
REG_WR(pdev, PXP2_REG_RQ_RBC_DONE, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
189
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
192
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
195
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
197
REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
323
REG_WR(pdev, MISC_REG_UNPREPARED, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
375
REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
448
REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
482
REG_WR(pdev, MISC_REG_AEU_ENABLE2_NIG_0, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
486
REG_WR(pdev, MISC_REG_AEU_ENABLE2_PXP_0, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
491
REG_WR(pdev, MISC_REG_AEU_ENABLE4_NIG_0, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
495
REG_WR(pdev, MISC_REG_AEU_ENABLE4_PXP_0, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
589
REG_WR(pdev, LM_ERROR_RECOVERY_COUNTER_HW_REGISTER, por_aux_register);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
636
REG_WR(pdev, LM_ERROR_RECOVERY_COUNTER_HW_REGISTER, por_aux_register);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
696
REG_WR(pdev, LM_ERROR_RECOVERY_COUNTER_HW_REGISTER, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
727
REG_WR(pdev, LM_ERROR_RECOVERY_COUNTER_HW_REGISTER, por_aux_register);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
757
REG_WR(pdev, LM_ERROR_RECOVERY_COUNTER_HW_REGISTER, por_aux_register);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c
94
REG_WR(pdev, MISC_REG_AEU_GENERAL_MASK, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1000
REG_WR(pdev, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P1, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1001
REG_WR(pdev, NIG_REG_LED_CONTROL_TRAFFIC_P1, value);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1052
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1058
REG_WR(pdev, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1059
REG_WR(pdev, NIG_REG_LED_CONTROL_TRAFFIC_P0, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1060
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1064
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1065
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_RATE_P0, rate);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1069
REG_WR(pdev, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P1, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1070
REG_WR(pdev, NIG_REG_LED_CONTROL_TRAFFIC_P1, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1071
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P1, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1075
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P1, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1076
REG_WR(pdev, NIG_REG_LED_CONTROL_BLINK_RATE_P1, rate);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1177
REG_WR(pdev, NIG_REG_LED_10G_P0 + port*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1178
REG_WR(pdev, NIG_REG_LED_MODE_P0 + port*4,SHARED_HW_CFG_LED_MAC1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1449
REG_WR(pdev, reg_offset, enable_mac);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1521
REG_WR(pdev, hw_lock_cntr_reg + 4, resource_bit);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1580
REG_WR(pdev, hw_lock_cntr_reg, resource_bit);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1631
REG_WR(pdev, hw_lock_cntr_reg, lock_status);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1678
REG_WR(pdev,GRCBASE_PCICONFIG+PCICFG_COMMAND_OFFSET,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1684
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1720
REG_WR(pdev,GRCBASE_PCICONFIG+PCICFG_COMMAND_OFFSET,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1727
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1744
REG_WR(pdev,GRCBASE_PCICONFIG + PCICFG_DEVICE_CONTROL,pci_devctl);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1880
REG_WR(pdev, reg_offset + current_offset, *data_ptr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1914
REG_WR(pdev,DRV_DUMP_TSTORM_WAITP_ADDRESS,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1915
REG_WR(pdev,DRV_DUMP_XSTORM_WAITP_ADDRESS,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1916
REG_WR(pdev,DRV_DUMP_CSTORM_WAITP_ADDRESS,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
1917
REG_WR(pdev,DRV_DUMP_USTORM_WAITP_ADDRESS,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
394
REG_WR(pdev,MISC_REG_SPIO_INT, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
399
REG_WR(pdev,MISC_REG_SPIO_EVENT_EN, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
584
REG_WR(pdev, MISC_REG_GPIO, gpio_reg);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
648
REG_WR(pdev, MISC_REG_GPIO, gpio_reg);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
715
REG_WR(pdev, MISC_REG_GPIO_INT, gpio_reg);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
776
REG_WR(pdev, MISC_REG_SPIO, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
842
REG_WR(pdev, MISC_REG_SPIO, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
869
REG_WR(pdev, NIG_REG_LED_MODE_P0, mode_idx);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
872
REG_WR(pdev, NIG_REG_LED_MODE_P1, mode_idx);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
941
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
950
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
959
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
968
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
972
REG_WR(pdev, NIG_REG_LED_10G_P0, value);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
974
REG_WR(pdev, NIG_REG_LED_10G_P1, value);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
994
REG_WR(pdev, emac_base+ EMAC_REG_EMAC_LED, reg_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
997
REG_WR(pdev, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_access.c
998
REG_WR(pdev, NIG_REG_LED_CONTROL_TRAFFIC_P0, value);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1003
REG_WR(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev), nig_mask);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1069
REG_WR(pdev, offset, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1149
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1150
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0) , val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1158
REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1159
REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
144
REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
147
REG_WR(pdev,PXP_REG_PXP_INT_MASK_1, (PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
151
REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
157
REG_WR(pdev,BRB1_REG_BRB1_INT_MASK ,0xFC00);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1573
REG_WR(pdev, offset ,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
159
REG_WR(pdev,QM_REG_QM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
160
REG_WR(pdev,TM_REG_TM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
161
REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_0 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
162
REG_WR(pdev,XSDM_REG_XSDM_INT_MASK_1 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
163
REG_WR(pdev,XCM_REG_XCM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
166
REG_WR(pdev,USDM_REG_USDM_INT_MASK_0 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
167
REG_WR(pdev,USDM_REG_USDM_INT_MASK_1 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
168
REG_WR(pdev,UCM_REG_UCM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1687
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_7,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1694
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_8,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1701
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_9,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1708
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_10,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
171
REG_WR(pdev,GRCBASE_UPB+PB_REG_PB_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1715
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_11,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
172
REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_0 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
173
REG_WR(pdev,CSDM_REG_CSDM_INT_MASK_1 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
174
REG_WR(pdev,CCM_REG_CCM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
185
REG_WR(pdev, PXP2_REG_PXP2_INT_MASK_0, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
187
REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_0 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
188
REG_WR(pdev,TSDM_REG_TSDM_INT_MASK_1 ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
189
REG_WR(pdev,TCM_REG_TCM_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
192
REG_WR(pdev,CDU_REG_CDU_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
193
REG_WR(pdev,DMAE_REG_DMAE_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
196
REG_WR(pdev,PBF_REG_PBF_INT_MASK ,0X18);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
1993
REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_ATTN_BITS_CLR,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
2001
REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
2017
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
2018
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
2050
REG_WR(pdev, port_reg_name, pdev->vars.aeu_mask_attn_func);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
441
REG_WR(pdev, offset, val );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
488
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
489
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_1,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
490
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
491
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_3,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
492
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
493
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_1,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
494
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
495
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_3,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
496
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
497
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
498
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
499
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
500
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
501
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
502
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
503
REG_WR(pdev,MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
509
REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0xffffffff); // 32 bits
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
512
REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0x1f); // 5 bits
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
516
REG_WR(pdev,PXP_REG_PXP_INT_MASK_1,0xff); // 8 bits
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
518
REG_WR(pdev,PXP2_REG_PXP2_INT_MASK_0,0xffffffff); // 32 bits
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
535
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
543
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
551
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
559
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
567
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
608
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
640
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
648
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
665
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
674
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
683
REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, latch_bit_to_clr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
736
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_1,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
741
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_2,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
746
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_3,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
776
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_4,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
781
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_5,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
786
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_6,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
834
REG_WR(pdev, NIG_REG_STATUS_INTERRUPT_PORT0, nig_status_port);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
866
REG_WR(pdev, NIG_REG_STATUS_INTERRUPT_PORT1, nig_status_port);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
906
REG_WR(pdev, port_reg_name, pdev->vars.aeu_mask_attn_func);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
933
REG_WR(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*PORT_ID(pdev), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
954
REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_ATTN_BITS_SET,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
961
REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
976
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_attn.c
977
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1041
REG_WR(pdev,HC_REG_CONFIG_0+(4*port),0x1000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1048
REG_WR(pdev,MISC_REG_AEU_MASK_ATTN_FUNC_0+(4*port),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1065
REG_WR(pdev,NIG_REG_PORT_SWAP,swap_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1066
REG_WR(pdev,NIG_REG_STRAP_OVERRIDE,swap_en);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1118
REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_FUNC_EN : NIG_REG_LLH0_FUNC_EN), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1127
REG_WR(pdev, nig_mem_enable_base_offset + nig_entry_idx*sizeof(u32_t), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1131
REG_WR(pdev, nig_mem2_enable_base_offset + nig_entry_idx*sizeof(u32_t), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1224
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1225
REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1303
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1304
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1308
REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1309
REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1319
REG_WR(pdev,HC_REG_CONFIG_0+(4*port),0x1000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1323
REG_WR(pdev,TM_REG_EN_LINEAR0_TIMER + (4*port),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1398
REG_WR(pdev, NIG_REG_MASK_INTERRUPT_PORT0 + 4*port,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1401
REG_WR(pdev, NIG_REG_LLH0_BRB1_DRV_MASK + 4*port,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1404
REG_WR(pdev, NIG_REG_LLH0_BRB1_NOT_MCP + 4*32*port,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1419
REG_WR(pdev,MISC_REG_AEU_MASK_ATTN_FUNC_0+(4*port),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1553
REG_WR(pdev, offset, pretend_func_num );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1664
REG_WR(pdev, data->offset, reg_port_arr[idx] );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
1808
REG_WR(pdev, non_split_offsets[idx].offset, non_split_vals[idx]);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2025
REG_WR(pdev, PRS_REG_VLAN_TYPE_0, 0x88a8);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2026
REG_WR(pdev, PBF_REG_VLAN_TYPE_0, 0x88a8);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2027
REG_WR(pdev, offset , 0x88a8);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2127
REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER + 4*PORT_ID(pdev),1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2140
REG_WR(pdev, TM_REG_EN_LINEAR0_TIMER + 4*PORT_ID(pdev),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2400
REG_WR(pdev, ncsi_oem_data_addr + offset, ver_32);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2542
REG_WR(pdev,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2564
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,reset_reg_1_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2566
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_2_SET,reset_reg_2_val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2575
REG_WR(pdev,MISC_REG_E1HMF_MODE , (pdev->params.multi_vnics_mode ? 1 : 0));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2595
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2612
REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2640
REG_WR(pdev, (PORT_ID(pdev) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0), val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2651
REG_WR(pdev, offset, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2661
REG_WR(pdev, offset, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2676
REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2696
REG_WR(pdev, PXP2_REG_RQ_QM_ENDIAN_M, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2697
REG_WR(pdev, PXP2_REG_RQ_TM_ENDIAN_M, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2698
REG_WR(pdev, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2699
REG_WR(pdev, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2700
REG_WR(pdev, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2702
REG_WR(pdev, PXP2_REG_RD_QM_SWAP_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2703
REG_WR(pdev, PXP2_REG_RD_TM_SWAP_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2704
REG_WR(pdev, PXP2_REG_RD_SRC_SWAP_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2705
REG_WR(pdev, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2709
REG_WR(pdev,PXP2_REG_RQ_CDU_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2710
REG_WR(pdev,PXP2_REG_RQ_TM_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2711
REG_WR(pdev,PXP2_REG_RQ_QM_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2712
REG_WR(pdev,PXP2_REG_RQ_SRC_P_SIZE,LOG2(pdev->params.ilt_client_page_size/LM_PAGE_SIZE));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2717
REG_WR(pdev,PXP2_REG_PGL_TAGS_LIMIT,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2724
REG_WR(pdev,PXP2_REG_RQ_DISABLE_INPUTS,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2725
REG_WR(pdev,PXP2_REG_RD_DISABLE_INPUTS,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2735
REG_WR(pdev,PXP2_REG_RQ_ONCHIP_AT_B0+i*8, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2736
REG_WR(pdev,PXP2_REG_RQ_ONCHIP_AT_B0+i*8+4,ONCHIP_ADDR0_VALID());
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2748
REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN,1); /* for 128B cache line value should be 2 */
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2749
REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN_RD,1); /* for 128B cache line value should be 2 */
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2750
REG_WR(pdev,PXP2_REG_RQ_DRAM_ALIGN_SEL,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
286
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2869
REG_WR(pdev,QM_REG_SOFT_RESET,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2870
REG_WR(pdev,QM_REG_SOFT_RESET,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2896
REG_WR(pdev,QM_REG_BASEADDR +4*(func*QM_QUEUES_PER_FUNC+i) , pdev->hw_info.max_common_conns * 4*i);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2906
REG_WR(pdev,QM_REG_BASEADDR_EXT_A +4*(func*QM_QUEUES_PER_FUNC+i) , pdev->hw_info.max_common_conns * 4*i);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2920
REG_WR(pdev, QM_REG_PF_EN, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2934
REG_WR(pdev, (PORT_ID(pdev) ? QM_REG_CONNNUM_1 : QM_REG_CONNNUM_0), pdev->hw_info.max_common_conns/16 -1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2947
REG_WR(pdev,(PORT_ID(pdev) ? TM_REG_LIN1_SCAN_TIME : TM_REG_LIN0_SCAN_TIME), 20);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2949
REG_WR(pdev,(PORT_ID(pdev) ? TM_REG_LIN1_MAX_ACTIVE_CID : TM_REG_LIN0_MAX_ACTIVE_CID), (pdev->hw_info.max_port_conns/32)-1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2964
REG_WR(pdev,DORQ_REG_DPM_CID_OFST,LM_DQ_CID_BITS);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2968
REG_WR(pdev,DORQ_REG_DORQ_INT_MASK,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2978
REG_WR(pdev, DORQ_REG_MAX_RVFID_SIZE, 6); // As long as we want to use absolute VF-id number
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2979
REG_WR(pdev, DORQ_REG_VF_NORM_VF_BASE, 0); //(a VF-id that is unique within the port), like the id
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2982
REG_WR(pdev, DORQ_REG_VF_NORM_CID_BASE, LM_VF_CID_BASE(pdev)); /*64 for single connection.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2986
REG_WR(pdev, DORQ_REG_VF_NORM_CID_WND_SIZE, LM_VF_CID_WND_SIZE(pdev)); /* should reflect the maximal number of connections in a VF.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2990
REG_WR(pdev, DORQ_REG_VF_NORM_CID_OFST, LM_DQ_CID_BITS - 3); /*means the number of bits in a VF doorbell.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
2993
REG_WR(pdev, DORQ_REG_VF_NORM_CID_OFST, LM_VF_DQ_CID_BITS);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3002
REG_WR(pdev, DORQ_REG_VF_TYPE_MASK_0, 0x71);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3003
REG_WR(pdev, DORQ_REG_VF_TYPE_VALUE_0, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3004
REG_WR(pdev, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3005
REG_WR(pdev, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3008
REG_WR(pdev, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3009
REG_WR(pdev, DORQ_REG_VF_USAGE_CT_LIMIT, 64);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3027
REG_WR(pdev, PBF_REG_HDRS_AFTER_BASIC, 0xE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3028
REG_WR(pdev, PBF_REG_MUST_HAVE_HDRS, 0xA);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3029
REG_WR(pdev, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3030
REG_WR(pdev, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3031
REG_WR(pdev, PBF_REG_TAG_LEN_0, 0x4);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3036
REG_WR(pdev, PBF_REG_HDRS_AFTER_BASIC, (pdev->params.path_has_ovlan ? 7 : 6)); //Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3046
REG_WR(pdev,PBF_REG_DISABLE_PF,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3094
REG_WR(pdev,BRB1_REG_PAUSE_LOW_THRESHOLD_0+port*4,low);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3095
REG_WR(pdev,BRB1_REG_PAUSE_HIGH_THRESHOLD_0+port*4,high);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3100
REG_WR(pdev, (PORT_ID(pdev)? BRB1_REG_MAC_GUARANTIED_1 : BRB1_REG_MAC_GUARANTIED_0), 40);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3117
REG_WR(pdev,PRS_REG_E1HOV_MODE, (pdev->params.path_has_ovlan ? 1 : 0));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3126
REG_WR(pdev, PRS_REG_HDRS_AFTER_BASIC, 0xE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3127
REG_WR(pdev, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3128
REG_WR(pdev, PRS_REG_MUST_HAVE_HDRS, 0xA);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3131
REG_WR(pdev, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3132
REG_WR(pdev, PRS_REG_TAG_LEN_0, 0x4);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3139
REG_WR(pdev, PRS_REG_HDRS_AFTER_BASIC, (pdev->params.path_has_ovlan ? 7 : 6)); //Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3154
REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_BASIC_PORT_0 :PRS_REG_HDRS_AFTER_BASIC_PORT_1 , 0xE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3155
REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_TAG_0_PORT_0 :PRS_REG_HDRS_AFTER_TAG_0_PORT_1 , 0x6);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3156
REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_MUST_HAVE_HDRS_PORT_0 :PRS_REG_MUST_HAVE_HDRS_PORT_1 , 0xA);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3164
REG_WR(pdev, (0 == PORT_ID(pdev))? PRS_REG_HDRS_AFTER_BASIC_PORT_0:PRS_REG_HDRS_AFTER_BASIC_PORT_1, (IS_MF_SD_MODE(pdev) ? 7 : 6)); //Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3187
REG_WR(pdev, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3190
REG_WR(pdev, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3242
REG_WR(pdev,TSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3243
REG_WR(pdev,USEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3244
REG_WR(pdev,CSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3245
REG_WR(pdev,XSEM_REG_VFPF_ERR_NUM, (FUNC_ID(pdev) + E2_MAX_NUM_OF_VFS));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3263
REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_PAUSE_ENABLE : PBF_REG_P0_PAUSE_ENABLE),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3265
REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_ARB_THRSH : PBF_REG_P0_ARB_THRSH),(MAXIMUM_PACKET_SIZE/16));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3267
REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_P1_INIT_CRD : PBF_REG_P0_INIT_CRD),(MAXIMUM_PACKET_SIZE/16) + 553 -22);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3269
REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_INIT_P1 : PBF_REG_INIT_P0),1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3271
REG_WR(pdev,(PORT_ID(pdev) ? PBF_REG_INIT_P1 : PBF_REG_INIT_P0),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3283
REG_WR(pdev,SRC_REG_SOFT_RST,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3287
REG_WR(pdev,SRC_REG_KEYSEARCH_0,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[0]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3288
REG_WR(pdev,SRC_REG_KEYSEARCH_1,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[4]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3289
REG_WR(pdev,SRC_REG_KEYSEARCH_2,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[8]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3290
REG_WR(pdev,SRC_REG_KEYSEARCH_3,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[12]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3291
REG_WR(pdev,SRC_REG_KEYSEARCH_4,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[16]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3292
REG_WR(pdev,SRC_REG_KEYSEARCH_5,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[20]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3293
REG_WR(pdev,SRC_REG_KEYSEARCH_6,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[24]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3294
REG_WR(pdev,SRC_REG_KEYSEARCH_7,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[28]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3295
REG_WR(pdev,SRC_REG_KEYSEARCH_8,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[32]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3296
REG_WR(pdev,SRC_REG_KEYSEARCH_9,*(u32_t *)(&pdev->context_info->searcher_hash.searcher_key[36]));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3298
REG_WR(pdev,SRC_REG_SOFT_RST,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3307
REG_WR(pdev, (PORT_ID(pdev) ? SRC_REG_COUNTFREE1 : SRC_REG_COUNTFREE0) ,pdev->vars.searcher_t2_num_pages * pdev->params.ilt_client_page_size/64);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3314
REG_WR(pdev, (PORT_ID(pdev) ? SRC_REG_NUMBER_HASH_BITS1 : SRC_REG_NUMBER_HASH_BITS0),pdev->context_info->searcher_hash.num_hash_bits);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3331
REG_WR(pdev,CDU_REG_CDU_GLOBAL_PARAMS,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3333
REG_WR(pdev,CDU_REG_CDU_CONTROL0,0X1UL);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3334
REG_WR(pdev,CDU_REG_CDU_CHK_MASK0,0X0003d000UL); /* enable region 2 */
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3335
REG_WR(pdev,CDU_REG_CDU_CHK_MASK1,0X0000003dUL); /* enable region 4 */
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3355
REG_WR(pdev, CFC_REG_INIT_REG, cfc_init_reg);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3366
REG_WR(pdev, CFC_REG_DISABLE_ON_ERROR, 0xffdf);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3367
REG_WR(pdev, CFC_REG_CFC_INT_MASK, 0x2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3368
REG_WR(pdev, CFC_REG_DORQ_MASK_PCIERR, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3369
REG_WR(pdev, CFC_REG_DORQ_MASK_VALERR, 0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3373
REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3374
REG_WR(pdev, CFC_REG_DORQ_MASK_PCIERR, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3375
REG_WR(pdev, CFC_REG_DORQ_MASK_VALERR, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3378
REG_WR(pdev,CFC_REG_CFC_INT_MASK ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3384
REG_WR(pdev,CFC_REG_DEBUG0 ,0x20020000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3385
REG_WR(pdev,CFC_REG_INTERFACES ,0x280000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3386
REG_WR(pdev,CFC_REG_INTERFACES ,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3401
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3402
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3419
REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_12 + 4*func,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3420
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3421
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3434
REG_WR(pdev, IGU_REG_COMMAND_DEBUG, 1); // 1 - FIFO collects eight last incoming command
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3439
REG_WR(pdev, IGU_REG_ERROR_HANDLING_FILTER, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3461
REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_12 + 4*FUNC_ID(pdev),0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3462
REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3463
REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3470
REG_WR(pdev, IGU_REG_PF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3490
REG_WR(pdev, IGU_REG_PROD_CONS_MEMORY + (prod_idx + i)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3512
REG_WR(pdev, IGU_REG_PROD_CONS_MEMORY + (base_prod + i*MAX_VNIC_NUM)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3524
REG_WR(pdev, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + igu_func_id*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3525
REG_WR(pdev, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + (igu_func_id + MAX_VNIC_NUM)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3528
REG_WR(pdev, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3529
REG_WR(pdev, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3530
REG_WR(pdev, IGU_REG_SB_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3531
REG_WR(pdev, IGU_REG_SB_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3532
REG_WR(pdev, IGU_REG_PBA_STATUS_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3533
REG_WR(pdev, IGU_REG_PBA_STATUS_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3545
REG_WR(pdev,NIG_REG_LLH_MF_MODE, IS_MULTI_VNIC(pdev) ? 1 : 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3551
REG_WR(pdev,NIG_REG_LLH_E1HOV_MODE, IS_MF_SD_MODE(pdev) ? 1 : 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3562
REG_WR(pdev,(PORT_ID(pdev) ? NIG_REG_XGXS_SERDES1_MODE_SEL : NIG_REG_XGXS_SERDES0_MODE_SEL),1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3570
REG_WR(pdev,(PORT_ID(pdev)? NIG_REG_LLH1_MF_MODE: NIG_REG_LLH_MF_MODE), IS_MULTI_VNIC(pdev) ? 1 : 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3584
REG_WR(pdev, mask_mf_reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3590
REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_CLS_TYPE : NIG_REG_LLH0_CLS_TYPE), 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3594
REG_WR(pdev, (PORT_ID(pdev) ? NIG_REG_LLH1_CLS_TYPE : NIG_REG_LLH0_CLS_TYPE), 2);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3614
REG_WR(pdev, offset , 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3618
REG_WR(pdev, offset , 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3622
REG_WR(pdev, offset , pdev->params.ovlan);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3634
REG_WR(pdev,0x2814,0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3635
REG_WR(pdev,0x3820,0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3639
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_CONTROL_5, (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3640
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3642
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3654
REG_WR(pdev,0x2114,0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3655
REG_WR(pdev,0x2120,0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3666
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
367
REG_WR(PFDEV(pdev),XSDM_REG_OPERATION_GEN, final_cleanup.command);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3680
REG_WR(pdev,PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, FUNC_ID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3690
REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3803
REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3804
REG_WR(pdev,TCM_REG_PRS_IFEN,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3805
REG_WR(pdev,CFC_REG_DEBUG0,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3806
REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3809
REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3856
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x3);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3858
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x3);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3867
REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3868
REG_WR(pdev,TCM_REG_PRS_IFEN,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3869
REG_WR(pdev,CFC_REG_DEBUG0,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3870
REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3873
REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3911
REG_WR(pdev,PRS_REG_CFC_SEARCH_INITIAL_CREDIT,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3933
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x03);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3935
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x03);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3942
REG_WR(pdev,TSDM_REG_ENABLE_IN1,0x7fffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3943
REG_WR(pdev,TCM_REG_PRS_IFEN,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3944
REG_WR(pdev,CFC_REG_DEBUG0,0x0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
3945
REG_WR(pdev,NIG_REG_PRS_REQ_IN_EN,0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4047
REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PAGE_BASE_OFFSET(func)),pdev->sq_info.sq_chain.bd_chain_phy.as_u32.low);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4048
REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PAGE_BASE_OFFSET(func)) + 4,pdev->sq_info.sq_chain.bd_chain_phy.as_u32.high);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4049
REG_WR(pdev,XSEM_REG_FAST_MEMORY + (XSTORM_SPQ_PROD_OFFSET(func)),pdev->sq_info.sq_chain.prod_idx);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4229
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_CLEAR,0x80000000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4230
REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_1_SET,0x80000000);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4244
REG_WR(pdev,IGU_REG_RESET_MEMORIES,0x36);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4260
REG_WR(pdev,CFC_REG_DEBUG0,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4350
REG_WR(pdev,(port ? NIG_REG_MASK_INTERRUPT_PORT1 : NIG_REG_MASK_INTERRUPT_PORT0), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
4634
REG_WR(pdev, start_reg + 4 * i, function_number + 2 * i);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
53
REG_WR(pdev,(PORT_ID(pdev) ? PXP2_REG_PSWRQ_##blk##1_L2P: PXP2_REG_PSWRQ_##blk##0_L2P),((last)<<10 | (first))); \
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
55
REG_WR(pdev,PXP2_REG_RQ_##blk##_FIRST_ILT,(first)); \
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
555
REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
56
REG_WR(pdev,PXP2_REG_RQ_##blk##_LAST_ILT,(last)); \
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
632
REG_WR(pdev,(GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET),MISC_REGISTERS_RESET_REG_1_RST_RBCP);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
715
REG_WR( pdev, reg_arr_ptr[idx], 0 );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
746
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_CLEAR, reg_1_clear );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
756
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, reg_2_clear);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
762
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_1_SET, MISC_REGISTERS_RESET_REG_1_RST_NIG);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
767
REG_WR( pdev, reg_arr_ptr[idx], restore_arr[idx] );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
813
REG_WR(pdev, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << FUNC_ID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c
912
REG_WR( pdev, DORQ_REG_NORM_CID_OFST ,0 );
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
151
REG_WR(pdev, shmem + validity_offset, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
240
REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15 + 4, 0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
246
REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR,
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
253
REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15, 0xffffffff);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
284
REG_WR(pdev, GRCBASE_MCP + 0x9c, val_wr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_mcp.c
326
REG_WR(pdev, GRCBASE_MCP + 0x9c, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_niv.c
373
REG_WR(pdev, output_offset + bytes_written, *field_ptr);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
117
REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port_num));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
155
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
158
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WREN);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
198
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
201
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WRDI);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
240
REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
262
REG_WR(pdev, MCP_REG_MCPR_NVM_ACCESS_ENABLE, val & ~(MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
294
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
297
REG_WR(pdev, MCP_REG_MCPR_NVM_ADDR, offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
300
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
362
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
365
REG_WR(pdev, MCP_REG_MCPR_NVM_WRITE, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
368
REG_WR(pdev, MCP_REG_MCPR_NVM_ADDR, offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
371
REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_nvram.c
69
REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port_num ));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
1013
REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, value);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
1181
REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(LM_FW_VF_DHC_QZONE_ID(vf_info, relative_in_vf_ndsb), HC_INDEX_VF_ETH_RX_CQ_CONS), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
381
REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
382
REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
383
REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
389
REG_WR(pf_dev, 0x24d8, 1<<29);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
391
REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev)));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
973
REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_pf.c
989
REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
202
REG_WR(cb, MISC_REG_AEU_GENERAL_ATTN_12 + FUNC_ID((lm_device_t *)cb)*sizeof(u32), 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
249
REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
258
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
267
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
298
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
300
REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST +
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
323
REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
332
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
341
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
375
REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
377
REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST +
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
787
REG_WR(pdev,MISC_REG_AEU_GENERAL_ATTN_12 + 4*(i*2 + port_id),0x1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_phy.c
82
REG_WR(cb, reg_addr, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
129
REG_WR( pdev, reg_len, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
132
REG_WR( pdev, reg_crc, val ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
255
REG_WR( pdev, offset, nwuf_reg_value ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
277
REG_WR( pdev, offset, nwuf_reg_value ) ;
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
321
REG_WR(pdev, emac_base+ offset , b_enable_mpkt ? val:0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
326
REG_WR(pdev, emac_base+ offset, b_enable_mpkt ? val:0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
379
REG_WR(pdev, emac.emac_mode, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
383
REG_WR(pdev, rpm.rpm_config, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_power.c
485
REG_WR(pdev, pcicfg_device_control_offset, pf0_pcie_status_control);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1001
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1002
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
102
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WOMASK(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1149
REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0x1FFFF);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1152
REG_WR(pdev, reg_name, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1170
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_TRAILING_EDGE_1 : HC_REG_TRAILING_EDGE_0), val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1171
REG_WR(pdev, (PORT_ID(pdev) ? HC_REG_LEADING_EDGE_1 : HC_REG_LEADING_EDGE_0), val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
118
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, INTR_BLK_CMD_CTRL_RD_WMASK(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1224
REG_WR(pdev, IGU_REG_PF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1246
REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1247
REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1286
REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1292
REG_WR(pdev, reg_name, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1322
REG_WR(pdev, IGU_REG_PF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1430
REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(byte_counter_id, index), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
1624
REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(byte_counter_id, index), 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
570
REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_L + 8*PORT_ID(pdev), host_sb_addr->as_u32.low);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
571
REG_WR(pdev, HC_REG_ATTN_MSG0_ADDR_H + 8*PORT_ID(pdev), host_sb_addr->as_u32.high);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
580
REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_L, host_sb_addr->as_u32.low);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
581
REG_WR(pdev, IGU_REG_ATTN_MSG_ADDR_H, host_sb_addr->as_u32.high);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
896
REG_WR(pdev, HC_REG_COMMAND_REG + PORT_ID(pdev)*32 + COMMAND_REG_INT_ACK, result);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
929
REG_WR(pdev, BAR_IGU_INTMEM + cmd_addr*8, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
946
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
947
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
980
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_sb.c
981
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c
66
REG_WR(pdev, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c
71
REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c
76
REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/bnxe_fw_funcs.c
87
REG_WR(pdev, reg_addr, reg_bit_map);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
180
REG_WR((_pdev), 0x2000, kuku); \
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
184
#define LM_GENERAL_ATTN_INTERRUPT_SET(_pdev,_func) REG_WR((_pdev),MISC_REG_AEU_GENERAL_ATTN_12 + 4*(_func),0x1)
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/lm5710.h
4097
#define VF_REG_WR(_pdev, _reg_offset, _val) REG_WR(_pdev, _reg_offset, _val)
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/lm_l4sp.c
1002
REG_WR(pdev, tmr_reg, delayed_ack_ticks);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l4/lm_l4sp.c
993
REG_WR(pdev, max_reg, ack_frequency);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
182
REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
183
REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
184
REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
190
REG_WR(pf_dev, 0x24d8, 1<<29);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
192
REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev)));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
355
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(ABS_VFID(pdev)) + i*sizeof(u32_t),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
358
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev))),pdev->sq_info.sq_chain.bd_chain_phy.as_u32.low);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
359
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(ABS_VFID(pdev)) + 4),pdev->sq_info.sq_chain.bd_chain_phy.as_u32.high);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
360
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PROD_OFFSET(ABS_VFID(pdev))),pdev->sq_info.sq_chain.prod_idx);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
459
REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
460
REG_WR(PFDEV(pdev), PGLUE_B_REG_INTERNAL_VFID_ENABLE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
486
REG_WR(PFDEV(pdev), was_err_reg, was_err_value); /* PglueB - Clear the was_error indication of the relevant function*/
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
492
REG_WR(PFDEV(pdev), IGU_REG_PROD_CONS_MEMORY + prod_idx*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
495
REG_WR(PFDEV(pdev),TSEM_REG_VFPF_ERR_NUM, ABS_VFID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
496
REG_WR(PFDEV(pdev),USEM_REG_VFPF_ERR_NUM, ABS_VFID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
497
REG_WR(PFDEV(pdev),CSEM_REG_VFPF_ERR_NUM, ABS_VFID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
498
REG_WR(PFDEV(pdev),XSEM_REG_VFPF_ERR_NUM, ABS_VFID(pdev));
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
522
REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
523
REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
524
REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
525
REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
526
REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
527
REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
542
REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
550
REG_WR(PFDEV(pdev), IGU_REG_PROD_CONS_MEMORY + (prod_idx + i)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/lm_vf.c
579
REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
209
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + XSTORM_VF_SPQ_DATA_OFFSET(vf_info->abs_vf_id) + i*sizeof(u32_t),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
212
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
213
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vf_info->abs_vf_id)) + 4,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
214
REG_WR(PFDEV(pdev),XSEM_REG_FAST_MEMORY + (XSTORM_VF_SPQ_PROD_OFFSET(vf_info->abs_vf_id)),0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
219
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2939
REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2940
REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2941
REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2942
REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2943
REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_LSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2944
REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_MSB, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2959
REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2966
REG_WR(PFDEV(pdev), IGU_REG_PROD_CONS_MEMORY + (prod_idx + i)*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
2996
REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3025
REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3026
REG_WR(PFDEV(pdev), PGLUE_B_REG_INTERNAL_VFID_ENABLE, 1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3052
REG_WR(PFDEV(pdev), was_err_reg, was_err_value); /* PglueB - Clear the was_error indication of the relevant function*/
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3059
REG_WR(PFDEV(pdev), IGU_REG_PROD_CONS_MEMORY + prod_idx*4, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3062
REG_WR(PFDEV(pdev),TSEM_REG_VFPF_ERR_NUM, abs_vf_id);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3063
REG_WR(PFDEV(pdev),USEM_REG_VFPF_ERR_NUM, abs_vf_id);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3064
REG_WR(PFDEV(pdev),CSEM_REG_VFPF_ERR_NUM, abs_vf_id);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3065
REG_WR(PFDEV(pdev),XSEM_REG_VFPF_ERR_NUM, abs_vf_id);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3088
REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,1);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3089
REG_WR(PFDEV(pdev), PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3296
REG_WR(PFDEV(pdev),XSDM_REG_OPERATION_GEN, final_cleanup.command);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3539
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3707
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3708
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3728
REG_WR(pdev, IGU_REG_COMMAND_REG_32LSB_DATA, cmd_data.sb_id_and_flags);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
3729
REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data);
usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/lm_vf.c
558
REG_WR(PFDEV(pdev), reg, val);
usr/src/uts/common/io/bnxe/bnxe.h
1031
REG_WR((lmdev), 0x2000, (data)); \
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dev.c
1146
REG_WR(p_hwfn, addr, 0);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_dev.c
1165
REG_WR(p_hwfn, addr, 0);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c
200
REG_WR(p_hwfn,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c
273
REG_WR(p_hwfn, bar_addr, val);
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c
395
REG_WR(p_hwfn,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c
411
REG_WR(p_hwfn,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hw.c
428
REG_WR(p_hwfn,
usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_init_ops.c
601
REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
