PUTCSR
PUTCSR(dca, CSR_DMACTL, DMACTL_BE32 | DMACTL_BE64);
PUTCSR(dca, CSR_DMACTL, DMACTL_RESET);
PUTCSR(dca, CSR_DMASTAT, status & DMASTAT_INTERRUPTS);
PUTCSR(dca, csr, workp->dw_mcr_paddr);
PUTCSR(dca, CSR_DMACTL, DMACTL_BE32 | DMACTL_BE64);
PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread | val);
PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
PUTCSR(afep, CSR_SPR, val);
PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(afep, CSR_SPR, val);
PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(afep, CSR_SPR, val);
PUTCSR(afep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(afep, CSR_TDR, 0);
PUTCSR(afep, CSR_TIMER, TIMER_LOOP |
PUTCSR(afep, CSR_SR2, INT_RXSTOPPED | INT_TXSTOPPED);
PUTCSR(afep, CSR_TIMER, 0);
PUTCSR(afep, CSR_RDB, 0);
PUTCSR(afep, CSR_TDB, 0);
PUTCSR(afep, CSR_TDB, afep->afe_txdesc_paddr);
PUTCSR(afep, CSR_RDB, afep->afe_rxdesc_paddr);
PUTCSR(afep, CSR_SR2, status);
PUTCSR(afep, CSR_RDR, 0); /* wake up chip */
PUTCSR(afep, CSR_IER2, mask);
PUTCSR(afep, CSR_IER2, INT_NONE);
PUTCSR(afep, CSR_SR2, INT_ALL);
PUTCSR(afep, CSR_TDR, 0);
PUTCSR(afep, CSR_PAR0, pa0);
PUTCSR(afep, CSR_PAR1, pa1);
PUTCSR(afep, CSR_MAR0, afep->afe_mctab[0]);
PUTCSR(afep, CSR_MAR1, afep->afe_mctab[1]);
PUTCSR(afep, CSR_PAR, par);
PUTCSR(afep, CSR_NAR, nar);
PUTCSR(afep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread | val);
PUTCSR(afep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread | SPR_SROM_CLOCK);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread);
PUTCSR(afep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
#define SETBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) | (val))
#define CLRBIT(afep, reg, val) PUTCSR(afep, reg, GETCSR(afep, reg) & ~(val))
PUTCSR(efep, CSR_PTCDAR, DESCADDR(rp, 0));
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
PUTCSR(efep, CSR_TEST, TEST_CLOCK);
PUTCSR(efep, CSR_RXCON,
PUTCSR(efep, CSR_TXCON, TXCON_LB_3);
PUTCSR(efep, CSR_COMMAND, COMMAND_STOP_RX);
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
PUTCSR(efep, CSR_COMMAND,
PUTCSR(efep, CSR_INTMASK,
PUTCSR(efep, CSR_INTMASK, 0);
PUTCSR(efep, CSR_LAN0, val);
PUTCSR(efep, CSR_LAN1, val);
PUTCSR(efep, CSR_LAN2, val);
PUTCSR(efep, CSR_MC0, mchash[0]);
PUTCSR(efep, CSR_MC1, mchash[1]);
PUTCSR(efep, CSR_MC2, mchash[2]);
PUTCSR(efep, CSR_MC3, mchash[3]);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS |
PUTCSR(efep, CSR_EECTL, EECTL_ENABLE | EECTL_EECS);
PUTCSR(efep, CSR_GENCTL, GENCTL_RESET);
PUTCSR(efep, CSR_GENCTL, GENCTL_PWRDWN);
PUTCSR(efep, CSR_MMCTL, MMCTL_READ |
PUTCSR(efep, CSR_MMDATA, data);
PUTCSR(efep, CSR_MMCTL, MMCTL_WRITE |
PUTCSR(efep, CSR_COMMAND, COMMAND_TXQUEUED);
PUTCSR(efep, CSR_INTSTAT, status);
PUTCSR(efep, CSR_COMMAND, COMMAND_RXQUEUED);
PUTCSR(efep, CSR_GENCTL, val);
PUTCSR(efep, CSR_PBLCNT, BURSTLEN);
PUTCSR(efep, CSR_PRCDAR, DESCADDR(rp, 0));
PUTCSR(efep, reg, (GETCSR(efep, reg) & ~(bit)))
PUTCSR(efep, reg, (GETCSR(efep, reg) | (bit)))
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, CSR_TCTL, tctl);
PUTCSR(mxfep, CSR_TSTAT, TSTAT_ANS_START);
PUTCSR(mxfep, CSR_MXMAGIC, 0x0b2c0000);
PUTCSR(mxfep, CSR_ACOMP, 0x11000);
PUTCSR(mxfep, CSR_SIA, SIA_NRESET);
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, CSR_TCTL, tctl);
PUTCSR(mxfep, CSR_MXMAGIC, 0x0b2c0000);
PUTCSR(mxfep, CSR_ACOMP, 0x11000);
PUTCSR(mxfep, CSR_TIMER, TIMER_LOOP |
PUTCSR(mxfep, CSR_TIMER, TIMER_LOOP |
PUTCSR(mxfep, CSR_SPR, val);
PUTCSR(mxfep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(mxfep, CSR_SPR, val);
PUTCSR(mxfep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(mxfep, CSR_SPR, val);
PUTCSR(mxfep, CSR_SPR, val | SPR_MII_CLOCK);
PUTCSR(mxfep, CSR_NAR, nar & ~NAR_PORTSEL);
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, CSR_NAR, nar & ~NAR_PORTSEL);
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, CSR_TDR, 0);
PUTCSR(mxfep, CSR_SR, INT_RXSTOPPED | INT_TXSTOPPED);
PUTCSR(mxfep, CSR_RDB, 0);
PUTCSR(mxfep, CSR_TDB, 0);
PUTCSR(mxfep, CSR_TDB, mxfep->mxfe_txdesc_paddr);
PUTCSR(mxfep, CSR_RDB, mxfep->mxfe_rxdesc_paddr);
PUTCSR(mxfep, CSR_SR, status);
PUTCSR(mxfep, CSR_IER, mask);
PUTCSR(mxfep, CSR_IER, 0);
PUTCSR(mxfep, CSR_SR, INT_ALL);
PUTCSR(mxfep, CSR_TDR, 0);
PUTCSR(mxfep, CSR_TDR, 0);
PUTCSR(mxfep, CSR_PAR, par);
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread | val);
PUTCSR(mxfep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread | SPR_SROM_CLOCK);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
PUTCSR(mxfep, CSR_SPR, eeread & ~SPR_SROM_CHIP);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread | val);
PUTCSR(mxfep, CSR_SPR, eeread | val | SPR_SROM_CLOCK);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread | SPR_SROM_CLOCK);
PUTCSR(mxfep, CSR_SPR, eeread);
PUTCSR(mxfep, CSR_SPR, eeread &~ SPR_SROM_CHIP);
PUTCSR(mxfep, CSR_TIMER, 0);
PUTCSR(mxfep, CSR_SIA, SIA_RESET);
PUTCSR(mxfep, CSR_NAR, nar);
PUTCSR(mxfep, reg, GETCSR(mxfep, reg) | (val))
PUTCSR(mxfep, reg, GETCSR(mxfep, reg) & ~(val))
PUTCSR(dca, reg, GETCSR(dca, reg) | val)
PUTCSR(dca, reg, GETCSR(dca, reg) & ~val)