BAR_1
for(i = BAR_1; i <= BAR_5; i++) {
LM_BAR_WR32_OFFSET((PDEV), BAR_1, (u32_t)((int_ptr_t)((u8_t *)(PDEV)->context_info->array[CID].cid_resc.mapped_cid_bar_addr - \
(PDEV)->hw_info.mem_base[BAR_1].as_u64 + (DPM_TRIGER_TYPE))), (VAL))
(volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + j*LM_DQ_CID_SIZE);
context->array[j].cid_resc.reg_handle = pdev->vars.reg_handle[BAR_1];
phy_addr.as_u32.low = (pdev->hw_info.mem_base[BAR_1].as_u32.low) & 0xfffffff0;
phy_addr.as_u32.high = pdev->hw_info.mem_base[BAR_1].as_u32.high;
(volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + cid*LM_DQ_CID_SIZE);
context->array[cid].cid_resc.reg_handle = pdev->vars.reg_handle[BAR_1];
BAR_1,
(volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + cid*LM_DQ_CID_SIZE);
max_bar_supported_cons[port] = pdev->hw_info.bar_size[BAR_1] / LM_DQ_CID_SIZE;
max_bar_supported_cons[port] = pdev->hw_info.bar_size[BAR_1] / LM_DQ_CID_SIZE;
case BAR_1:
case BAR_1:
if (BAR_1 == i )
MM_WRITE_DOORBELL(PDEV,BAR_1,CID,VAL);\
MM_WRITE_DOORBELL(PDEV,BAR_1,CID,VAL);\
BnxeCheckAccHandle(pLM->vars.reg_handle[BAR_1]) != DDI_FM_OK)