usr/src/cmd/pcitool/pcitool.c

281

{ PCI_CONF_ROM, 4, "ROM", "Expansion ROM Base Address Register (@30)" },

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3007

pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3009

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3019

PCI_CONF_ROM, request,

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3026

PCI_CONF_ROM) != PCICFG_SUCCESS) {

usr/src/uts/common/io/cardbus/cardbus_cfg.c

3530

if (reg_offset == PCI_CONF_ROM) {

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4363

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/common/io/e1000g/e1000g_debug.c

436

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_init.c

349

w16 = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_ROM);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_init.c

351

ql_pci_config_put16(ha, PCI_CONF_ROM, w16);

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

685

pci_config_get32(qlge->pci_handle, PCI_CONF_ROM);

usr/src/uts/common/io/igb/igb_debug.c

129

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

254

pci_config_get32(handle, PCI_CONF_ROM));

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

765

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_ROM));

usr/src/uts/i86pc/io/pci/pci_tools.c

1213

cfg.offset = PCI_CONF_ROM;

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3081

if (reg_offset == PCI_CONF_ROM) {

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3162

if (reg_offset == PCI_CONF_ROM) {

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3638

pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3640

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3648

PCI_CONF_ROM, request,

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3653

if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM)

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3738

base = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3739

pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3740

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3741

pci_config_put32(config_handle, PCI_CONF_ROM, base);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3749

PCI_CONF_ROM, request,

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3754

if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM)

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

3763

base, 0, PCI_CONF_ROM) != PCICFG_SUCCESS) {

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

447

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/intel/io/pci/pci_boot.c

2955

offset = PCI_CONF_ROM;

usr/src/uts/sun4/io/efcode/fcpci.c

1390

if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {

usr/src/uts/sun4/io/efcode/fcpci.c

1618

if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {

usr/src/uts/sun4/io/pcicfg.c

2936

(PCI_REG_REG_G(assigned[i].pci_phys_hi) != PCI_CONF_ROM))

usr/src/uts/sun4/io/pcicfg.c

3210

if (reg_offset == PCI_CONF_ROM) {

usr/src/uts/sun4/io/pcicfg.c

3336

if (reg_offset == PCI_CONF_ROM) {

usr/src/uts/sun4/io/pcicfg.c

4253

pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe);

usr/src/uts/sun4/io/pcicfg.c

4255

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

4263

PCI_CONF_ROM, request,

usr/src/uts/sun4/io/pcicfg.c

4269

request, PCI_CONF_ROM) != PCICFG_SUCCESS) {

usr/src/uts/sun4/io/pcicfg.c

4497

pci_config_put32(h, PCI_CONF_ROM, 0xfffffffe);

usr/src/uts/sun4/io/pcicfg.c

4499

request = pci_config_get32(h, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

478

pci_config_get32(config_handle, PCI_CONF_ROM));

usr/src/uts/sun4/io/pcicfg.c

4859

base = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

4860

pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe);

usr/src/uts/sun4/io/pcicfg.c

4861

request = pci_config_get32(config_handle, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

4862

pci_config_put32(config_handle, PCI_CONF_ROM, base);

usr/src/uts/sun4/io/pcicfg.c

4870

PCI_CONF_ROM, request,

usr/src/uts/sun4/io/pcicfg.c

4876

request, PCI_CONF_ROM) != PCICFG_SUCCESS) {

usr/src/uts/sun4/io/pcicfg.c

4884

base, 0, PCI_CONF_ROM) != PCICFG_SUCCESS) {

usr/src/uts/sun4/io/pcicfg.c

5821

func, PCI_CONF_ROM);

usr/src/uts/sun4/io/pcicfg.c

6097

"[0x%x]=[0x%x]\n", PCI_CONF_ROM, fc_request, size);

usr/src/uts/sun4/io/pcicfg.c

6122

pci_config_put32(h, PCI_CONF_ROM,

usr/src/uts/sun4/io/pcicfg.c

6129

PCI_CONF_ROM) | PCI_ADDR_MEM32;

usr/src/uts/sun4/io/pcicfg.c

6419

if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {

usr/src/uts/sun4/io/pcicfg.c

6595

if (PCI_REG_REG_G(phys_spec.pci_phys_hi) == PCI_CONF_ROM) {

usr/src/uts/sun4/io/px/px_tools.c

558

(cfg_prg.offset != PCI_CONF_ROM)) {

usr/src/uts/sun4/io/px/px_tools.c

572

(cfg_prg.offset != PCI_CONF_ROM)) {

usr/src/uts/sun4/io/px/px_tools.c

602

} else if (cfg_prg.offset == PCI_CONF_ROM) { /* ROM requested */

usr/src/uts/sun4/io/px/px_tools.c

63

PCI_CONF_ROM

usr/src/uts/sun4/io/px/px_tools.c

721

if ((PCI_BAR_OFFSET(prg) == PCI_CONF_ROM) && (write_flag)) {

usr/src/uts/sun4u/io/pci/db21554.c

1646

hdr_off + PCI_CONF_ROM);

usr/src/uts/sun4u/io/pci/pci_tools.c

768

(bar_offset != PCI_CONF_ROM)) {

usr/src/uts/sun4u/io/pci/pci_tools.c

781

} else if ((PCI_BASE_TYPE_ALL & *bar) && (bar_offset != PCI_CONF_ROM)) {

usr/src/uts/sun4u/io/pci/pci_tools.c

932

if (PCI_BAR_OFFSET(prg) == PCI_CONF_ROM) {

usr/src/uts/sun4u/io/pci/pci_tools.c

96

PCI_CONF_ROM

usr/src/uts/sun4u/sys/pci/db21554_config.h

55

#define DB_PCONF_EXP_ROM PCI_CONF_ROM