Symbol: PCI_CONF_BASE5
usr/src/cmd/pcitool/pcitool.c
280
{ PCI_CONF_BASE5, 4, "BAR5", "Base Address Register 5 (@24)" },
usr/src/uts/common/io/cardbus/cardbus_cfg.c
2952
while (i <= PCI_CONF_BASE5) {
usr/src/uts/common/io/cardbus/cardbus_cfg.c
4359
pci_config_get32(config_handle, PCI_CONF_BASE5));
usr/src/uts/common/io/comstar/port/qlt/qlt.c
530
w32h = PCICFG_RD32(qlt, PCI_CONF_BASE5);
usr/src/uts/common/io/e1000g/e1000g_debug.c
423
pciconfig_bar(Adapter, PCI_CONF_BASE5, "PCI_CONF_BASE5");
usr/src/uts/common/io/e1000g/e1000g_main.c
1218
(bar_offset <= PCI_CONF_BASE5));
usr/src/uts/common/io/e1000g/e1000g_main.c
748
offset <= PCI_CONF_BASE5; offset += 4) {
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16351
chs.chs_base5 = ql_pci_config_get32(ha, PCI_CONF_BASE5);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16416
ql_pci_config_put32(ha, PCI_CONF_BASE5, chs_p->chs_base5);
usr/src/uts/common/io/igb/igb_debug.c
117
pci_config_get32(handle, PCI_CONF_BASE5));
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
242
pci_config_get32(handle, PCI_CONF_BASE5));
usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c
761
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE5));
usr/src/uts/common/io/scsi/adapters/pvscsi/pvscsi.c
843
for (offset = PCI_CONF_BASE0; offset <= PCI_CONF_BASE5; offset += 4) {
usr/src/uts/common/os/sunpci.c
426
chsp->chs_base5 = pci_config_get32(confhdl, PCI_CONF_BASE5);
usr/src/uts/common/os/sunpci.c
780
pci_config_put32(confhdl, PCI_CONF_BASE5, chs_p->chs_base5);
usr/src/uts/common/os/sunpci.c
802
(void) pci_config_get32(confhdl, PCI_CONF_BASE5);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3595
while (i <= PCI_CONF_BASE5) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
3677
while (i <= PCI_CONF_BASE5) {
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
439
pci_config_get32(config_handle, PCI_CONF_BASE5));
usr/src/uts/intel/io/vmm/io/ppt.c
161
(b) <= PCI_CONF_BASE5 && \
usr/src/uts/sun4/io/pcicfg.c
2935
if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) > PCI_CONF_BASE5) &&
usr/src/uts/sun4/io/pcicfg.c
4208
while (i <= PCI_CONF_BASE5) {
usr/src/uts/sun4/io/pcicfg.c
470
pci_config_get32(config_handle, PCI_CONF_BASE5));
usr/src/uts/sun4/io/pcicfg.c
4796
while (i <= PCI_CONF_BASE5) {
usr/src/uts/sun4/io/pcicfg.c
6024
for (i = PCI_CONF_BASE0; i <= PCI_CONF_BASE5; ) {
usr/src/uts/sun4/io/px/px_tools.c
577
if (cfg_prg.offset >= PCI_CONF_BASE5) {
usr/src/uts/sun4/io/px/px_tools.c
62
PCI_CONF_BASE5,
usr/src/uts/sun4u/io/pci/db21554.c
1638
ph->bar5 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE5);
usr/src/uts/sun4u/io/pci/pci_tools.c
786
if (bar_offset >= PCI_CONF_BASE5) {
usr/src/uts/sun4u/io/pci/pci_tools.c
95
PCI_CONF_BASE5,
usr/src/uts/sun4u/sys/pci/db21554_config.h
54
#define DB_PCONF_DS_UMEM3 PCI_CONF_BASE5
usr/src/uts/sun4u/sys/pci/db21554_config.h
68
#define DB_SCONF_DS_UMEM3 DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE5