usr/src/cmd/pcitool/pcitool.c

278

{ PCI_CONF_BASE3, 4, "BAR3", "Base Address Register 3 (@1C)" },

usr/src/uts/common/io/cardbus/cardbus_cfg.c

4355

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/common/io/comstar/port/qlt/qlt.c

487

w32h = PCICFG_RD32(qlt, PCI_CONF_BASE3);

usr/src/uts/common/io/comstar/port/qlt/qlt.c

586

w32 = PCICFG_RD32(qlt, PCI_CONF_BASE3);

usr/src/uts/common/io/comstar/port/qlt/qlt.c

622

w32l = PCICFG_RD32(qlt, PCI_CONF_BASE3);

usr/src/uts/common/io/e1000g/e1000g_debug.c

421

pciconfig_bar(Adapter, PCI_CONF_BASE3, "PCI_CONF_BASE3");

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

16349

chs.chs_base3 = ql_pci_config_get32(ha, PCI_CONF_BASE3);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

16414

ql_pci_config_put32(ha, PCI_CONF_BASE3, chs_p->chs_base3);

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c

19164

PCI_CONF_BASE3, ha->mbar_size) != DDI_SUCCESS) {

usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c

673

pci_config_get32(qlge->pci_handle, PCI_CONF_BASE3);

usr/src/uts/common/io/igb/igb_debug.c

108

msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);

usr/src/uts/common/io/ixgbe/ixgbe_debug.c

233

msix_bar = pci_config_get32(handle, PCI_CONF_BASE3);

usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c

757

pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE3));

usr/src/uts/common/os/sunpci.c

424

chsp->chs_base3 = pci_config_get32(confhdl, PCI_CONF_BASE3);

usr/src/uts/common/os/sunpci.c

778

pci_config_put32(confhdl, PCI_CONF_BASE3, chs_p->chs_base3);

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

164

PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,

usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c

435

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/sun4/io/pcicfg.c

205

PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,

usr/src/uts/sun4/io/pcicfg.c

466

pci_config_get32(config_handle, PCI_CONF_BASE3));

usr/src/uts/sun4/io/px/px_tools.c

60

PCI_CONF_BASE3,

usr/src/uts/sun4u/io/pci/db21554.c

1056

(off_t)(p_offset + PCI_CONF_BASE3))) & ~DB_IO_BIT));

usr/src/uts/sun4u/io/pci/db21554.c

1068

(off_t)(s_offset + PCI_CONF_BASE3))) & ~DB_IO_BIT));

usr/src/uts/sun4u/io/pci/db21554.c

1636

ph->bar3 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE3);

usr/src/uts/sun4u/io/pci/pci_tools.c

93

PCI_CONF_BASE3,

usr/src/uts/sun4u/sys/pci/db21554_config.h

52

#define DB_PCONF_DS_MEM2 PCI_CONF_BASE3

usr/src/uts/sun4u/sys/pci/db21554_config.h

57

#define DB_PCONF_US_MEM1 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE3

usr/src/uts/sun4u/sys/pci/db21554_config.h

63

#define DB_SCONF_US_MEM1 PCI_CONF_BASE3

usr/src/uts/sun4u/sys/pci/db21554_config.h

66

#define DB_SCONF_DS_MEM2 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE3