PCI_CONF_BASE2
{ PCI_CONF_BASE2, 4, "BAR2", "Base Address Register 2 (@18)" },
data = pci_config_get32(dev->pcih, PCI_CONF_BASE2);
pci_config_get32(config_handle, PCI_CONF_BASE2),
w32l = PCICFG_RD32(qlt, PCI_CONF_BASE2);
pciconfig_bar(Adapter, PCI_CONF_BASE2, "PCI_CONF_BASE2");
chs.chs_base2 = ql_pci_config_get32(ha, PCI_CONF_BASE2);
ql_pci_config_put32(ha, PCI_CONF_BASE2, chs_p->chs_base2);
pci_config_get32(qlge->pci_handle, PCI_CONF_BASE2);
pci_config_get32(handle, PCI_CONF_BASE2));
pci_config_get32(handle, PCI_CONF_BASE2));
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE2));
chsp->chs_base2 = pci_config_get32(confhdl, PCI_CONF_BASE2);
pci_config_put32(confhdl, PCI_CONF_BASE2, chs_p->chs_base2);
PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
pci_config_get32(config_handle, PCI_CONF_BASE2));
PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3,
pci_config_get32(config_handle, PCI_CONF_BASE2));
PCI_CONF_BASE2,
(off_t)(p_offset + PCI_CONF_BASE2))) & ~DB_IO_BIT));
(off_t)(s_offset + PCI_CONF_BASE2))) & ~DB_IO_BIT));
ph->bar2 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE2);
PCI_CONF_BASE2,
#define DB_PCONF_DS_IO_MEM1 PCI_CONF_BASE2
#define DB_PCONF_US_IO_MEM0 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE2
#define DB_SCONF_US_IO_MEM0 PCI_CONF_BASE2
#define DB_SCONF_DS_IO_MEM1 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE2