PCI_CONF_BASE1
{ PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
{ PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
pci_config_get32(config_handle, PCI_CONF_BASE1));
pciconfig_bar(Adapter, PCI_CONF_BASE1, "PCI_CONF_BASE1");
for (offset = PCI_CONF_BASE1;
chs.chs_base1 = ql_pci_config_get32(ha, PCI_CONF_BASE1);
ql_pci_config_put32(ha, PCI_CONF_BASE1, chs_p->chs_base1);
chip.MemAddr = ql_pci_config_get32(ha, PCI_CONF_BASE1);
pci_config_get32(qlge->pci_handle, PCI_CONF_BASE1);
pci_config_get32(handle, PCI_CONF_BASE1));
pci_config_get32(handle, PCI_CONF_BASE1));
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1));
chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
pci_config_get32(config_handle, PCI_CONF_BASE1));
pci_config_get32(config_handle, PCI_CONF_BASE1));
PCI_CONF_BASE1,
ph->bar1 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE1);
PCI_CONF_BASE1,
#define DB_PCONF_IO_CSR PCI_CONF_BASE1
#define DB_SCONF_IO_CSR PCI_CONF_BASE1