Symbol: PCI_CONF_BASE1
usr/src/cmd/pcitool/pcitool.c
276
{ PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
usr/src/cmd/pcitool/pcitool.c
288
{ PCI_CONF_BASE1, 4, "BAR1", "Base Address Register 1 (@14)" },
usr/src/uts/common/io/cardbus/cardbus_cfg.c
4351
pci_config_get32(config_handle, PCI_CONF_BASE1));
usr/src/uts/common/io/e1000g/e1000g_debug.c
419
pciconfig_bar(Adapter, PCI_CONF_BASE1, "PCI_CONF_BASE1");
usr/src/uts/common/io/e1000g/e1000g_main.c
747
for (offset = PCI_CONF_BASE1;
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16347
chs.chs_base1 = ql_pci_config_get32(ha, PCI_CONF_BASE1);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_api.c
16412
ql_pci_config_put32(ha, PCI_CONF_BASE1, chs_p->chs_base1);
usr/src/uts/common/io/fibre-channel/fca/qlc/ql_xioctl.c
1457
chip.MemAddr = ql_pci_config_get32(ha, PCI_CONF_BASE1);
usr/src/uts/common/io/fibre-channel/fca/qlge/qlge_dbg.c
667
pci_config_get32(qlge->pci_handle, PCI_CONF_BASE1);
usr/src/uts/common/io/igb/igb_debug.c
102
pci_config_get32(handle, PCI_CONF_BASE1));
usr/src/uts/common/io/ixgbe/ixgbe_debug.c
227
pci_config_get32(handle, PCI_CONF_BASE1));
usr/src/uts/common/io/scsi/adapters/pmcs/pmcs_fwlog.c
753
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE1));
usr/src/uts/common/os/sunpci.c
422
chsp->chs_base1 = pci_config_get32(confhdl, PCI_CONF_BASE1);
usr/src/uts/common/os/sunpci.c
776
pci_config_put32(confhdl, PCI_CONF_BASE1, chs_p->chs_base1);
usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c
421
pci_config_get32(config_handle, PCI_CONF_BASE1));
usr/src/uts/sun4/io/pcicfg.c
452
pci_config_get32(config_handle, PCI_CONF_BASE1));
usr/src/uts/sun4/io/px/px_tools.c
58
PCI_CONF_BASE1,
usr/src/uts/sun4u/io/pci/db21554.c
1634
ph->bar1 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE1);
usr/src/uts/sun4u/io/pci/pci_tools.c
91
PCI_CONF_BASE1,
usr/src/uts/sun4u/sys/pci/db21554_config.h
50
#define DB_PCONF_IO_CSR PCI_CONF_BASE1
usr/src/uts/sun4u/sys/pci/db21554_config.h
61
#define DB_SCONF_IO_CSR PCI_CONF_BASE1