PCI_CONF_BASE0
if (!ops->pop_cfg(PCI_CONF_BASE0 + i * 4, sizeof (uint32_t),
"device at offset 0x%x", PCI_CONF_BASE0 + i * 4);
uint32_t targ = PCI_CONF_BASE0 + arg.pblo_idx *
{ PCI_CONF_BASE0, 4, "BAR0", "Base Address Register 0 (@10)" },
{ PCI_CONF_BASE0, 4, "BAR0", "Base Address Register 0 (@10)" },
pci_config_get32(pci_config_handle, PCI_CONF_BASE0);
PCI_CONF_BASE0, 0xffffffff);
PCI_CONF_BASE0);
PCI_CONF_BASE0) != PCICFG_SUCCESS) {
PCI_CONF_BASE0, request,
PCI_CONF_BASE0) != PCICFG_SUCCESS) {
i = PCI_CONF_BASE0;
pci_config_get32(config_handle, PCI_CONF_BASE0),
pciconfig_bar(Adapter, PCI_CONF_BASE0, "PCI_CONF_BASE0");
ASSERT((bar_offset >= PCI_CONF_BASE0) &&
bar_offset = PCI_CONF_BASE0 + sizeof (uint32_t) * bar;
size = ql_pci_config_get32(ha, PCI_CONF_BASE0) & BIT_0 ?
chs.chs_base0 = ql_pci_config_get32(ha, PCI_CONF_BASE0);
ql_pci_config_put32(ha, PCI_CONF_BASE0, chs_p->chs_base0);
chip.IoAddr = ql_pci_config_get32(ha, PCI_CONF_BASE0);
pci_config_get32(qlge->pci_handle, PCI_CONF_BASE0);
pci_config_get32(handle, PCI_CONF_BASE0));
pci_config_get32(handle, PCI_CONF_BASE0));
instance->pci_handle, PCI_CONF_BASE0);
instance->pci_handle, PCI_CONF_BASE0);
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE0));
for (offset = PCI_CONF_BASE0; offset <= PCI_CONF_BASE5; offset += 4) {
bar_offset = PCI_CONF_BASE0 + sizeof (uint32_t) * bar;
chsp->chs_base0 = pci_config_get32(confhdl, PCI_CONF_BASE0);
pci_config_put32(confhdl, PCI_CONF_BASE0, chs_p->chs_base0);
uint32_t targ = PCI_CONF_BASE0 + ((cb->pbwc_reg->barnum - 1) *
cfg->offset = PCI_CONF_BASE0 + i * 4;
offset = PCI_CONF_BASE0;
offset = PCI_CONF_BASE0;
i = PCI_CONF_BASE0;
i = PCI_CONF_BASE0;
pci_config_get32(config_handle, PCI_CONF_BASE0));
end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
for (bar = 0, offset = PCI_CONF_BASE0; offset < end;
lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
#define BAR_TO_IDX(bar) (((bar) - PCI_CONF_BASE0) / PCI_BAR_SZ_32)
(b) >= PCI_CONF_BASE0 && \
offset = PCI_CONF_BASE0;
i = PCI_CONF_BASE0;
pci_config_get32(config_handle, PCI_CONF_BASE0));
i = PCI_CONF_BASE0;
for (i = PCI_CONF_BASE0; i <= PCI_CONF_BASE5; ) {
PCI_CONF_BASE0,
if ((offset == PCI_CONF_BASE0) &&
(off_t)(p_offset + PCI_CONF_BASE0)));
(off_t)(p_offset + PCI_CONF_BASE0)));
ph->bar0 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE0);
PCI_CONF_BASE0,
#define DB_PCONF_MEM_CSR PCI_CONF_BASE0
#define DB_SCONF_MEM_CSR PCI_CONF_BASE0