MDIO_REG_BANK_AER_BLOCK
CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
(MDIO_REG_BANK_AER_BLOCK +