LOCK_LEVEL
for (i = 0; i < LOCK_LEVEL + 1; i++) {
static struct av_head softvec_tbl[LOCK_LEVEL + 1];
newnglobpris = maxglobpri + 1 + LOCK_LEVEL;
maxglobpri = (pri_t)(v.v_nglobpris - LOCK_LEVEL - 1);
if (i < 0 || i > LOCK_LEVEL)
uint_t actv = CPU->cpu_intr_actv >> (LOCK_LEVEL + 1); \
if (((hi_pri > LOCK_LEVEL) && (lvl < LOCK_LEVEL)) ||
((hi_pri < LOCK_LEVEL) && (lvl > LOCK_LEVEL))) {
if (lvl <= 0 || lvl > LOCK_LEVEL) {
if (lvl <= 0 && lvl >= LOCK_LEVEL) {
if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL)
struct av_head softvect[LOCK_LEVEL + 1];
if (mlxp->mlx_async_intr_pri < LOCK_LEVEL) {
pcic->pc_irq = LOCK_LEVEL + 1;
if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) {
pcieb->pcieb_intr_priority = LOCK_LEVEL - 1;
(void *)ipltospl(LOCK_LEVEL)); \
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
(void *)ipltospl(LOCK_LEVEL));
clock_tick_intr = create_softint(LOCK_LEVEL,
for (i = 0; i < LOCK_LEVEL - 1; i++)
for (i = 0; i < LOCK_LEVEL - 1; i++)
return (LOCK_LEVEL + 1);
ASSERT(ipl > 0 && ipl <= LOCK_LEVEL);
if ((intptr_t)ibc > ipltospl(LOCK_LEVEL) && ibc < (void *)KERNELBASE) {
ASSERT(new_pil > LOCK_LEVEL);
cp->cpu_intr_actv &= ((1 << (LOCK_LEVEL + 1)) - 1);
(interrupts_unleashed && (spltoipl(s) > LOCK_LEVEL));
if (ndi_event_alloc_hdl(dip, (ddi_iblock_cookie_t)(LOCK_LEVEL-1),
if (*(int *)result > LOCK_LEVEL)
#define CPU_ON_INTR(cpup) ((cpup)->cpu_intr_actv >> (LOCK_LEVEL + 1))
((level) <= LOCK_LEVEL ? \
#define PCIE_INTR_PRI (LOCK_LEVEL - 1)
if (*(int *)result > LOCK_LEVEL)
splx(ipltospl(LOCK_LEVEL));
if (av->av_ticksp && av->av_prilevel <= LOCK_LEVEL)
mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
ASSERT(newipl > LOCK_LEVEL && newipl > cpu->cpu_base_spl);
ASSERT(newipl <= LOCK_LEVEL);
} else if (newipl > LOCK_LEVEL) {
for (ipl = 1; ipl < MIN(LOCK_LEVEL, vecp->v_pri); ipl++)
if (*(int *)result > LOCK_LEVEL)
if (*(int *)result > LOCK_LEVEL)
splx(ipltospl(LOCK_LEVEL));
if (*(int *)result > LOCK_LEVEL)
printf("#define\tLOCK_LEVEL 0x%x\n", LOCK_LEVEL);
ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
if (newipl > LOCK_LEVEL) {
ASSERT(pil > LOCK_LEVEL);
mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
(void) add_avsoftintr((void *)&lbolt_softint_hdl, LOCK_LEVEL,
splx(ipltospl(LOCK_LEVEL));
ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
((ipl) <= LOCK_LEVEL ? \
((apixp)->x_intr_pending >> (LOCK_LEVEL + 1)))
#define CBE_LOCK_PIL LOCK_LEVEL
#define NINTR_THREADS (LOCK_LEVEL-1) /* number of interrupt threads */
ASSERT(newipl != LOCK_LEVEL + 1);
rem_avintr(NULL, LOCK_LEVEL - 1, acpi_wrapper_isr,
#define SCI_IPL (LOCK_LEVEL-1)
#define DISP_LEVEL (LOCK_LEVEL + 1)
#define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
#define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
#define DISP_LEVEL (LOCK_LEVEL + 1)
#define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
#define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
if (getpil() > LOCK_LEVEL)
if (pil <= LOCK_LEVEL)
if (pil <= LOCK_LEVEL)
printf("#define\tCPU_INTRSTAT_LOW_PIL_OFFSET %d\n", (LOCK_LEVEL + 1) *
abort_seq_inum = add_softintr(LOCK_LEVEL,
on_intr = CPU_ON_INTR(CPU) || (spltoipl(s) > LOCK_LEVEL);
if (getpil() > LOCK_LEVEL) {
ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
lbolt_softint_inum = add_softintr(LOCK_LEVEL,
#define CBE_LOCK_PIL LOCK_LEVEL
ASSERT(getpil() > LOCK_LEVEL);
if (ipil_p->ipil_pil <= LOCK_LEVEL)
else if (intr_info->pil >= LOCK_LEVEL) {
#define NINTR_THREADS (LOCK_LEVEL) /* number of interrupt threads */
#define NINTR_THREADS (LOCK_LEVEL) /* number of interrupt threads */