PCIR_BAR
#define PCI_CBMEM PCIR_BAR(0)
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
rid = PCIR_BAR(0);
rid = PCIR_BAR(0);
rid = PCIR_BAR(2);
#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */
#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */
#define PCI_CBIO PCIR_BAR(0) /* Configuration Base IO Address */
#define PCI_CBMA PCIR_BAR(1) /* Configuration Base Memory Address */
rid = PCIR_BAR(0);
scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR);
rid = PCIR_BAR(0);
for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
rid = PCIR_BAR(2);
rid = PCIR_BAR(3);
bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2),
PCIR_BAR(3), sc->nfe_msix_pba_res);
PCIR_BAR(2), sc->nfe_msix_res);
rid = PCIR_BAR(0);
bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3),
bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2),
bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
i = PCIR_BAR(0);
sc->vte_res_id = PCIR_BAR(1);
sc->vte_res_id = PCIR_BAR(0);
sc->rl_res_id = PCIR_BAR(0);
sc->rl_res_id = PCIR_BAR(1);
sc->rl_res_id = PCIR_BAR(1);
sc->rl_res_id = PCIR_BAR(2);
sc->rl_res_id = PCIR_BAR(0);
sc->rl_res_id = PCIR_BAR(0);
rid = PCIR_BAR(4);
rid = PCIR_BAR(4);
sc->sge_res_id = PCIR_BAR(0);
{ SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
sc->vr_res_id = PCIR_BAR(0);
rid = PCIR_BAR(0);
rid = PCIR_BAR(1);
rid = PCIR_BAR(1);
PCIR_BAR(1), sc->vge_res);
sc->port_rid = PCIR_BAR(0);
sc->mem_rid = PCIR_BAR(1);
sc->mem_aux_rid = PCIR_BAR(2);
#define BWI_PCIR_BAR PCIR_BAR(0)
i = PCIR_BAR(0);
i = PCIR_BAR(0);
rid = PCIR_BAR(0);
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
{ SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
rid = PCIR_BAR(0);
rid = PCIR_BAR(2);
return PCIR_BAR(bar);