OS_REG_RMW_FIELD
OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_ALLOW);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_WAKE);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE,
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
OS_REG_RMW_FIELD(ah, AR_IMR_S2,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]);
OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]);
OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_IMR_S2,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE,
OS_REG_RMW_FIELD(ah, AR_MISC_MODE, AR_PCU_BT_ANT_PREVENT_RX,
OS_REG_RMW_FIELD(ah, AR_QUIET1,
OS_REG_RMW_FIELD(ah, AR_MISC_MODE,
OS_REG_RMW_FIELD(ah, AR_QUIET1,
OS_REG_RMW_FIELD(ah, AR_MISC_MODE,
OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
OS_REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4_CHAIN(i),
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_CAUSE,
OS_REG_RMW_FIELD(ah, AR_GPIO_INTR_POL,
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_ENABLE,
OS_REG_RMW_FIELD(ah, AR_INTR_ASYNC_MASK,
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_ENABLE,
OS_REG_RMW_FIELD(ah, AR_INTR_SYNC_MASK,
OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
OS_REG_RMW_FIELD(ah, AR_MAC_LED,
OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah,
OS_REG_RMW_FIELD(ah,
OS_REG_RMW_FIELD(ah,
OS_REG_RMW_FIELD(ah,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits);
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK,
OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,
OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250);
OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700);
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
OS_REG_RMW_FIELD(ah, AR_IMR_S2,
OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
OS_REG_RMW_FIELD(ah,
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
OS_REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
OS_REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
OS_REG_RMW_FIELD(ah, AR_PHY_CCA,
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,