B_PRIxPHYSADDR
TRACE("area = %" B_PRId32 ", size = %ld, virt = %p, phy = %" B_PRIxPHYSADDR "\n", area, size, virtadr,
TRACE("Allocated area %" B_PRId32 " length %ld buf %p phys %" B_PRIxPHYSADDR "\n", areaid,
SHOW_FLOW(1, "addr=%" B_PRIxPHYSADDR ", size=%" B_PRIuPHYSADDR,
SHOW_FLOW(0, "S/G-entry crosses DMA boundary @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "S/G-entry has bad alignment @%#" B_PRIxPHYSADDR,
SHOW_FLOW(0, "end of S/G-entry has bad alignment @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "S/G-entry above high address @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "buffer = %p, virt_addr = %#" B_PRIxPHYSADDR ", bytes = %"
SHOW_FLOW(3, "physical = %#" B_PRIxPHYSADDR ", address = %p",
SHOW_FLOW(4, "addr=%#" B_PRIxPHYSADDR ", size=%" B_PRIxPHYSADDR
B_PRIxPHYSADDR "\n", area, size, logAddress, physicalEntry.address);
TRACE("area = %" B_PRId32 ", size = %ld, virt = %p, phy = %#" B_PRIxPHYSADDR "\n",
TRACE("GTT base %" B_PRIxPHYSADDR ", size %lu, entries %lu, stolen %lu\n",
ERROR("GTT base = 0x%" B_PRIxPHYSADDR "\n", info.gtt_physical_base);
ERROR("GMR base = 0x%" B_PRIxPHYSADDR "\n", info.aperture_physical_base);
TRACE_ALWAYS("init_bus() addr 0x%" B_PRIxPHYSADDR " size 0x%" B_PRIx64
TRACE_ALWAYS("init_bus() addr 0x%" B_PRIxPHYSADDR " size 0x%" B_PRIx64
TRACE("registers at %#" B_PRIxPHYSADDR ", size %#" B_PRIxSIZE "\n", addr,
FLOW("FillPrdTable: sg-entry addr %#" B_PRIxPHYSADDR ", size %lu\n",
TRACE("sg_memcpy phyAddr %#" B_PRIxPHYSADDR ", size %lu\n",
TRACE("area = %" B_PRId32 ", size = %ld, virt = %p, phy = %#" B_PRIxPHYSADDR "\n",
TRACE("mapping physical address %#" B_PRIxPHYSADDR " with %" B_PRIuSIZE
TRACE("physical = %#" B_PRIxPHYSADDR ", virtual = %p, offset = %"
B_PRId32 ", phyadr = %#" B_PRIxPHYSADDR ", mapadr = %p, size = %"
TRACE("isochronous created itd, filling it with phy %" B_PRIxPHYSADDR
TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR
panic("EHCI_PERIODICLISTBASE not aligned on 4k: 0x%" B_PRIxPHYSADDR
TRACE("insert endpoint for pipe: trb_addr, device 0x%" B_PRIxPHYSADDR
" endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr,
TRACE("_LinkDescriptorForPipe pLink %p phys 0x%" B_PRIxPHYSADDR
" 0x%" B_PRIxPHYSADDR " 0x%08" B_PRIx32 "\n", &endpoint->trbs[link],
TRACE_ERROR("successful TRB 0x%" B_PRIxPHYSADDR " was found, but it wasn't "
TRACE_ERROR("TRB 0x%" B_PRIxPHYSADDR " was not found in the endpoint!\n", source);
TRACE("map registers %08" B_PRIxPHYSADDR ", size: %" B_PRIuSIZE "\n",
TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress);
TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
dprintf("cmedia_pci: physical %#" B_PRIxPHYSADDR " logical %p\n",
B_PRIxPHYSADDR "\n", areaid, size, virtadr, pe.address);
TRACE("mapping physical address %" B_PRIxPHYSADDR " with %ld bytes for %s\n",
TRACE("physical = %" B_PRIxPHYSADDR ", virtual = %p, offset = %" B_PRIu32
", phyadr = %" B_PRIxPHYSADDR ", mapadr = %p, size = %" B_PRIuSIZE
B_PRIxPHYSADDR "\n", regsBase);
B_PRIxADDR " (%" B_PRIxPHYSADDR ")\n",
SHOW_ERROR(2, "Physical address > 4 GB: %#" B_PRIxPHYSADDR
TRACE("framebuffer paddr: %#" B_PRIxPHYSADDR "\n", fbAddr);
TRACE("virtio_gpu_attach_backing %d %" B_PRIxPHYSADDR " %" B_PRIxPHYSADDR "\n", i,
TRACE_DMA("ata_adapter: %#" B_PRIxPHYSADDR ", %" B_PRIuPHYSADDR " => "
"0x%" B_PRIxPHYSADDR "\n", dmat->lowaddr);
"low 0x%" B_PRIxPHYSADDR ", high 0x%" B_PRIxPHYSADDR ", "
"boundary 0x%" B_PRIxPHYSADDR ")\n",
dprintf("%s memory_region v: %#" B_PRIxADDR " p: %#" B_PRIxPHYSADDR " size: %lu\n", msg, vaddr,
dprintf(" base 0x%" B_PRIxPHYSADDR
", length 0x%" B_PRIxPHYSADDR "\n",
dprintf(" base 0x%" B_PRIxPHYSADDR
", length 0x%" B_PRIxPHYSADDR "\n",
dprintf(" base 0x%" B_PRIxPHYSADDR
", length 0x%" B_PRIxPHYSADDR "\n",
"0x%08" B_PRIxPHYSADDR " -> 0x%08" B_PRIxPHYSADDR "\n",
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
"pgtable. phys=%#" B_PRIxPHYSADDR ", virt=%#" B_PRIxADDR "\n",
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
"pgtable. %#" B_PRIxPHYSADDR "\n", pgtable);
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE("early_tmap: entry pa %#" B_PRIxPHYSADDR " va %#" B_PRIxADDR "\n", pa,
TRACE(" %" B_PRIxPHYSADDR " - %" B_PRIxPHYSADDR "\n", start, end);
TRACE(" %" B_PRIxPHYSADDR " - %" B_PRIxPHYSADDR "\n", start, end);
TRACE(" %" B_PRIxPHYSADDR " - %" B_PRIxPHYSADDR "\n", start, end);
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE("early_tmap: entry pa %#" B_PRIxPHYSADDR " va %#" B_PRIxADDR "\n", pa,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
TRACE(" %#10" B_PRIxPHYSADDR " - %#10" B_PRIxPHYSADDR "\n", start,
"pgtable. %#" B_PRIxPHYSADDR "\n", pgtable);
TRACE("X86PagingMethod64Bit::MapEarly(%#" B_PRIxADDR ", %#" B_PRIxPHYSADDR
" %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n", virtualAddress,
" %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n", virtualAddress,
" for va %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n",
"for va %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n", virtualAddress,
"directory for va %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n",
"table for va %#" B_PRIxADDR " at %#" B_PRIxPHYSADDR "\n",
B_PRIxPHYSADDR "\n", i, j, k, address);
B_PRIxPHYSADDR "\n", i, j, address);
panic("PDPT %u on invalid page %#" B_PRIxPHYSADDR "\n", i,
panic("PML4 %u on invalid page %#" B_PRIxPHYSADDR "\n", p,
TRACE("X86VMTranslationMap64Bit::Map(%#" B_PRIxADDR ", %#" B_PRIxPHYSADDR
B_PRIxADDR " (%#" B_PRIxPHYSADDR ")\n", start,
B_PRIxPHYSADDR " %#" B_PRIx32 " (entry: %#" B_PRIx64 ")\n",
"page table: %#" B_PRIxPHYSADDR "\n", physicalPageTable);
TRACE("page dir: %p (physical: %#" B_PRIxPHYSADDR ")\n",
B_PRIxPHYSADDR ", virtual base: %#" B_PRIxADDR "\n",
TRACE("X86VMTranslationMapPAE::Map(): %#" B_PRIxADDR " -> %#" B_PRIxPHYSADDR
"page table: %#" B_PRIxPHYSADDR "\n", physicalPageTable);
B_PRIxPHYSADDR ":\n", virtualAddress, *_physicalAddress);
B_PRIxPHYSADDR ":\n", virtualAddress, *_physicalAddress);
kprintf(" bounce buffer: %p (physical %#" B_PRIxPHYSADDR ")\n",
kprintf(" bounce buffer size: %" B_PRIxPHYSADDR "\n", fBounceBuffer->size);
kprintf(" address: 0x%" B_PRIxPHYSADDR " (%s)\n", entry->address,
kprintf("\t%p ppn %#" B_PRIxPHYSADDR " offset %#" B_PRIxPHYSADDR
ASSERT_PRINT(page != NULL, "page number: %#" B_PRIxPHYSADDR
B_PRIxPHYSADDR ", accessed: %d, modified: %d", page,
ASSERT_PRINT(page != NULL, "page number: %#" B_PRIxPHYSADDR, pageNumber);
B_PRIxPHYSADDR, page, pageNumber);
panic("looking up page failed for pa %#" B_PRIxPHYSADDR
B_PRIu32 ", phys = %#" B_PRIxPHYSADDR ")\n", team, name, *_address,
FTRACE(("vm_soft_fault: just allocated page 0x%" B_PRIxPHYSADDR "\n",
panic("area %p looking up page failed for pa %#" B_PRIxPHYSADDR
TRACE(("mark_page_range_in_use: start %#" B_PRIxPHYSADDR ", len %#"
B_PRIxPHYSADDR "\n", startPage, length));
dprintf("mark_page_range_in_use(%#" B_PRIxPHYSADDR ", %#" B_PRIxPHYSADDR
dprintf("mark_page_range_in_use(%#" B_PRIxPHYSADDR ", %#" B_PRIxPHYSADDR
panic("mark_page_range_in_use: page %#" B_PRIxPHYSADDR
TRACE(("first phys page = %#" B_PRIxPHYSADDR ", end %#" B_PRIxPHYSADDR "\n",
" (size %#" B_PRIxPHYSADDR ")\n", sPages, sNumPages,
out.Print("page alloc: %#" B_PRIxPHYSADDR, fPageNumber);
out.Print("page alloc run: start %#" B_PRIxPHYSADDR " length: %"
out.Print("page free: %#" B_PRIxPHYSADDR, fPageNumber);
kprintf("page number %#" B_PRIxPHYSADDR, pageNumber);
kprintf("page %#" B_PRIxPHYSADDR "\n", pageNumber);
kprintf("physical_number: %#" B_PRIxPHYSADDR "\n", page->physical_page_number);
dprintf("DMA Test area %p, physical %#" B_PRIxPHYSADDR
", second physical %#" B_PRIxPHYSADDR "\n",
dprintf("DMA Test area %p, physical %#" B_PRIxPHYSADDR "\n",