headers/private/graphics/radeon/radeon_interface.h

222

(ai->si->asic == rt_rv100) || \

headers/private/graphics/radeon/radeon_interface.h

223

(ai->si->asic == rt_rv200) || \

headers/private/graphics/radeon/radeon_interface.h

224

(ai->si->asic == rt_rs100) || \

headers/private/graphics/radeon/radeon_interface.h

225

(ai->si->asic == rt_rs200) || \

headers/private/graphics/radeon/radeon_interface.h

226

(ai->si->asic == rt_rv250) || \

headers/private/graphics/radeon/radeon_interface.h

227

(ai->si->asic == rt_rv280) || \

headers/private/graphics/radeon/radeon_interface.h

228

(ai->si->asic == rt_rs300))

headers/private/graphics/radeon/radeon_interface.h

238

(ai->si->asic == rt_r300) || \

headers/private/graphics/radeon/radeon_interface.h

239

(ai->si->asic == rt_r350) || \

headers/private/graphics/radeon/radeon_interface.h

240

(ai->si->asic == rt_rv350) || \

headers/private/graphics/radeon/radeon_interface.h

241

(ai->si->asic == rt_rv380) || \

headers/private/graphics/radeon/radeon_interface.h

242

(ai->si->asic == rt_r420))

headers/private/kernel/arch/x86/32/iframe.h

19

uint32 si;

headers/private/kernel/arch/x86/64/iframe.h

21

uint64 si;

src/add-ons/accelerants/3dfx/3dfx_cursor.cpp

44

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/3dfx_cursor.cpp

49

uint64* fbCursor64 = (uint64*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/3dfx/3dfx_cursor.cpp

67

uint8* fbCursor = (uint8*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/3dfx/3dfx_init.cpp

53

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

55

si.videoMemSize = TDFX_GetVideoMemorySize();

src/add-ons/accelerants/3dfx/3dfx_init.cpp

57

si.cursorOffset = 0;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

58

si.frameBufferOffset = si.cursorOffset + CURSOR_BYTES;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

59

si.maxFrameBufferSize = si.videoMemSize - si.frameBufferOffset;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

61

TRACE("Video Memory size: %d MB\n", si.videoMemSize / 1024 / 1024);

src/add-ons/accelerants/3dfx/3dfx_init.cpp

63

si.frameBufferOffset, si.cursorOffset);

src/add-ons/accelerants/3dfx/3dfx_init.cpp

65

switch (si.chipType) {

src/add-ons/accelerants/3dfx/3dfx_init.cpp

67

si.maxPixelClock = 270000;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

70

si.maxPixelClock = 300000;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

73

si.maxPixelClock = 350000;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

76

TRACE("Undefined chip type: %d\n", si.chipType);

src/add-ons/accelerants/3dfx/3dfx_init.cpp

82

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

83

si.colorSpaces[1] = B_RGB16;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

84

si.colorSpaces[2] = B_RGB32;

src/add-ons/accelerants/3dfx/3dfx_init.cpp

85

si.colorSpaceCount = 3;

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

208

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

209

bool clock2X = mode.timing.pixel_clock > si.maxPixelClock / 2;

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

314

if (si.chipType == BANSHEE && pllFreq == 45831

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

340

OUTREG32(HW_CURSOR_PAT_ADDR, si.cursorOffset);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

342

OUTREG32(VIDEO_DESKTOP_START_ADDR, si.frameBufferOffset);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

350

OUTREG32(SRC_BASE_ADDR, si.frameBufferOffset);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

351

OUTREG32(DST_BASE_ADDR, si.frameBufferOffset);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

366

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

372

address += si.frameBufferOffset;

src/add-ons/accelerants/3dfx/3dfx_overlay.cpp

21

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/3dfx_overlay.cpp

29

if (si.displayMode.bitsPerPixel == 16) {

src/add-ons/accelerants/3dfx/accelerant.cpp

188

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/accelerant.cpp

192

strcpy(adi->chipset, si.chipName);

src/add-ons/accelerants/3dfx/accelerant.cpp

194

adi->memory = si.maxFrameBufferSize;

src/add-ons/accelerants/3dfx/accelerant.cpp

79

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/accelerant.cpp

81

TRACE("Vendor ID: 0x%X, Device ID: 0x%X\n", si.vendorID, si.deviceID);

src/add-ons/accelerants/3dfx/accelerant.cpp

85

if (si.bAccelerantInUse) {

src/add-ons/accelerants/3dfx/accelerant.cpp

90

result = si.engineLock.Init("3DFX engine lock");

src/add-ons/accelerants/3dfx/accelerant.cpp

92

result = si.overlayLock.Init("3DFX overlay lock");

src/add-ons/accelerants/3dfx/accelerant.cpp

98

si.bAccelerantInUse = true;

src/add-ons/accelerants/3dfx/cursor.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/cursor.cpp

26

si.cursorHotX = hot_x;

src/add-ons/accelerants/3dfx/cursor.cpp

27

si.cursorHotY = hot_y;

src/add-ons/accelerants/3dfx/cursor.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/cursor.cpp

48

DisplayModeEx& dm = si.displayMode;

src/add-ons/accelerants/3dfx/cursor.cpp

75

x -= (hds + si.cursorHotX);

src/add-ons/accelerants/3dfx/cursor.cpp

76

y -= (vds + si.cursorHotY);

src/add-ons/accelerants/3dfx/mode.cpp

101

si.bHaveEDID = TDFX_GetEdidInfo(si.edidInfo);

src/add-ons/accelerants/3dfx/mode.cpp

103

if (si.bHaveEDID) {

src/add-ons/accelerants/3dfx/mode.cpp

105

edid_dump(&(si.edidInfo));

src/add-ons/accelerants/3dfx/mode.cpp

116

si.bHaveEDID ? &si.edidInfo : NULL,

src/add-ons/accelerants/3dfx/mode.cpp

117

NULL, 0, si.colorSpaces, si.colorSpaceCount,

src/add-ons/accelerants/3dfx/mode.cpp

123

si.modeArea = gInfo.modeListArea = listArea;

src/add-ons/accelerants/3dfx/mode.cpp

124

si.modeCount = count;

src/add-ons/accelerants/3dfx/mode.cpp

138

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

147

if ((target->timing.pixel_clock > si.maxPixelClock / 2)

src/add-ons/accelerants/3dfx/mode.cpp

153

uint32 modeCount = si.modeCount;

src/add-ons/accelerants/3dfx/mode.cpp

175

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

220

si.displayMode = mode;

src/add-ons/accelerants/3dfx/mode.cpp

280

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

282

pFBC->frame_buffer = (void*)((addr_t)si.videoMemAddr

src/add-ons/accelerants/3dfx/mode.cpp

283

+ si.frameBufferOffset);

src/add-ons/accelerants/3dfx/mode.cpp

284

pFBC->frame_buffer_dma = (void*)((addr_t)si.videoMemPCI

src/add-ons/accelerants/3dfx/mode.cpp

285

+ si.frameBufferOffset);

src/add-ons/accelerants/3dfx/mode.cpp

286

pFBC->bytes_per_row = si.displayMode.virtual_width

src/add-ons/accelerants/3dfx/mode.cpp

287

* si.displayMode.bytesPerPixel;

src/add-ons/accelerants/3dfx/mode.cpp

298

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

309

if (lowClock > si.maxPixelClock)

src/add-ons/accelerants/3dfx/mode.cpp

322

*high = si.maxPixelClock / 2;

src/add-ons/accelerants/3dfx/mode.cpp

324

*high = si.maxPixelClock;

src/add-ons/accelerants/3dfx/mode.cpp

336

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

338

if ( ! si.bHaveEDID)

src/add-ons/accelerants/3dfx/mode.cpp

344

memcpy(info, &si.edidInfo, sizeof(struct edid1_info));

src/add-ons/accelerants/3dfx/mode.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/mode.cpp

58

if (mode->timing.pixel_clock > si.maxPixelClock)

src/add-ons/accelerants/3dfx/mode.cpp

64

for (uint32 j = 0; j < si.colorSpaceCount; j++) {

src/add-ons/accelerants/3dfx/mode.cpp

65

if (mode->space == uint32(si.colorSpaces[j])) {

src/add-ons/accelerants/3dfx/mode.cpp

77

if ((mode->timing.pixel_clock > si.maxPixelClock / 2)

src/add-ons/accelerants/3dfx/mode.cpp

94

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

124

addr_t fbEndAddr = si.videoMemAddr + si.frameBufferOffset

src/add-ons/accelerants/3dfx/overlay.cpp

125

+ (si.displayMode.virtual_width * si.displayMode.bytesPerPixel

src/add-ons/accelerants/3dfx/overlay.cpp

126

* si.displayMode.virtual_height);

src/add-ons/accelerants/3dfx/overlay.cpp

129

si.overlayLock.Release();

src/add-ons/accelerants/3dfx/overlay.cpp

140

si.overlayLock.Release();

src/add-ons/accelerants/3dfx/overlay.cpp

151

ovBuff->buffer_dma = (void*)(si.videoMemPCI

src/add-ons/accelerants/3dfx/overlay.cpp

152

+ ((addr_t)ovBuff->buffer - si.videoMemAddr));

src/add-ons/accelerants/3dfx/overlay.cpp

155

si.overlayBuffer = ovBuff;

src/add-ons/accelerants/3dfx/overlay.cpp

159

si.overlayLock.Release();

src/add-ons/accelerants/3dfx/overlay.cpp

169

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

178

OverlayBuffer* ovBuff = si.overlayBuffer;

src/add-ons/accelerants/3dfx/overlay.cpp

187

si.overlayBuffer = ovBuff->nextBuffer;

src/add-ons/accelerants/3dfx/overlay.cpp

256

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

263

if (atomic_or(&si.overlayAllocated, 1) != 0) {

src/add-ons/accelerants/3dfx/overlay.cpp

268

si.overlayToken);

src/add-ons/accelerants/3dfx/overlay.cpp

269

return (overlay_token)++si.overlayToken;

src/add-ons/accelerants/3dfx/overlay.cpp

276

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

280

if (overlayToken != (overlay_token)si.overlayToken)

src/add-ons/accelerants/3dfx/overlay.cpp

285

atomic_and(&si.overlayAllocated, 0); // mark overlay as unallocated

src/add-ons/accelerants/3dfx/overlay.cpp

296

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

298

if (overlayToken != (overlay_token)si.overlayToken)

src/add-ons/accelerants/3dfx/overlay.cpp

50

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/3dfx/overlay.cpp

55

si.overlayLock.Acquire();

src/add-ons/accelerants/3dfx/overlay.cpp

71

si.overlayLock.Release();

src/add-ons/accelerants/3dfx/overlay.cpp

89

if (si.chipType == VOODOO_5)

src/add-ons/accelerants/3dfx/overlay.cpp

92

OverlayBuffer* ovBuff = si.overlayBuffer;

src/add-ons/accelerants/3dfx/overlay.cpp

98

addr_t prevBuffAddr = si.videoMemAddr + si.frameBufferOffset

src/add-ons/accelerants/3dfx/overlay.cpp

99

+ si.maxFrameBufferSize;

src/add-ons/accelerants/ati/accelerant.cpp

104

si.bAccelerantInUse = true;

src/add-ons/accelerants/ati/accelerant.cpp

204

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/accelerant.cpp

209

adi->memory = si.maxFrameBufferSize;

src/add-ons/accelerants/ati/accelerant.cpp

216

if (si.displayType == MT_VGA)

src/add-ons/accelerants/ati/accelerant.cpp

217

strcpy(adi->chipset, si.chipName);

src/add-ons/accelerants/ati/accelerant.cpp

86

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/accelerant.cpp

88

TRACE("Vendor ID: 0x%X, Device ID: 0x%X\n", si.vendorID, si.deviceID);

src/add-ons/accelerants/ati/accelerant.cpp

92

if (si.bAccelerantInUse) {

src/add-ons/accelerants/ati/accelerant.cpp

97

result = si.engineLock.Init("ATI engine lock");

src/add-ons/accelerants/ati/cursor.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/cursor.cpp

26

si.cursorHotX = hot_x;

src/add-ons/accelerants/ati/cursor.cpp

27

si.cursorHotY = hot_y;

src/add-ons/accelerants/ati/cursor.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/cursor.cpp

48

DisplayModeEx& dm = si.displayMode;

src/add-ons/accelerants/ati/cursor.cpp

75

x -= (hds + si.cursorHotX);

src/add-ons/accelerants/ati/cursor.cpp

76

y -= (vds + si.cursorHotY);

src/add-ons/accelerants/ati/mach64_cursor.cpp

29

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_cursor.cpp

46

OUTREG(CUR_OFFSET, (si.cursorOffset >> 3) + (yOffset << 1));

src/add-ons/accelerants/ati/mach64_cursor.cpp

55

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_cursor.cpp

60

uint16* fbCursor = (uint16*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/ati/mach64_init.cpp

133

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_init.cpp

153

if (si.chipType >= MACH64_264VTB) {

src/add-ons/accelerants/ati/mach64_init.cpp

154

if ((si.chipType >= MACH64_264VT4) && (si.chipType != MACH64_264LTPRO))

src/add-ons/accelerants/ati/mach64_init.cpp

156

else if (si.chipType >= MACH64_264VT3)

src/add-ons/accelerants/ati/mach64_init.cpp

177

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_init.cpp

183

if (si.chipType < MACH64_264VTB) {

src/add-ons/accelerants/ati/mach64_init.cpp

184

si.videoMemSize = videoRamSizes[memCntl & 0x7] * 1024;

src/add-ons/accelerants/ati/mach64_init.cpp

188

si.videoMemSize = (ioValue + 1) * 512 * 1024;

src/add-ons/accelerants/ati/mach64_init.cpp

190

si.videoMemSize = (ioValue - 3) * 1024 * 1024;

src/add-ons/accelerants/ati/mach64_init.cpp

192

si.videoMemSize = (ioValue - 7) * 2048 * 1024;

src/add-ons/accelerants/ati/mach64_init.cpp

195

si.cursorOffset = (si.videoMemSize - CURSOR_BYTES) & ~0xfff; // align to 4k boundary

src/add-ons/accelerants/ati/mach64_init.cpp

196

si.frameBufferOffset = 0;

src/add-ons/accelerants/ati/mach64_init.cpp

197

si.maxFrameBufferSize = si.cursorOffset - si.frameBufferOffset;

src/add-ons/accelerants/ati/mach64_init.cpp

200

si.videoMemSize / 1024 / 1024, si.frameBufferOffset, si.cursorOffset);

src/add-ons/accelerants/ati/mach64_init.cpp

204

if ((si.chipType >= MACH64_264VTB) && !Mach64_InitDSPParams())

src/add-ons/accelerants/ati/mach64_init.cpp

209

si.displayType = MT_VGA;

src/add-ons/accelerants/ati/mach64_init.cpp

211

if (si.chipType == MACH64_MOBILITY && si.panelX > 0 && si.panelY > 0) {

src/add-ons/accelerants/ati/mach64_init.cpp

213

si.displayType = MT_LAPTOP;

src/add-ons/accelerants/ati/mach64_init.cpp

218

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/ati/mach64_init.cpp

219

si.colorSpaces[1] = B_RGB15;

src/add-ons/accelerants/ati/mach64_init.cpp

220

si.colorSpaces[2] = B_RGB16;

src/add-ons/accelerants/ati/mach64_init.cpp

221

si.colorSpaces[3] = B_RGB32;

src/add-ons/accelerants/ati/mach64_init.cpp

222

si.colorSpaceCount = 4;

src/add-ons/accelerants/ati/mach64_init.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_init.cpp

26

M64_Params& params = si.m64Params;

src/add-ons/accelerants/ati/mach64_init.cpp

64

if (si.chipType < MACH64_264VT4) {

src/add-ons/accelerants/ati/mach64_init.cpp

77

if (si.videoMemSize <= 1024 * 1024) {

src/add-ons/accelerants/ati/mach64_init.cpp

87

if (si.videoMemSize <= 1024 * 1024) {

src/add-ons/accelerants/ati/mach64_init.cpp

96

if (si.videoMemSize <= 1024 * 1024) {

src/add-ons/accelerants/ati/mach64_mode.cpp

125

if (si.chipType >= MACH64_264VTB) {

src/add-ons/accelerants/ati/mach64_mode.cpp

156

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_mode.cpp

157

M64_Params& params = si.m64Params;

src/add-ons/accelerants/ati/mach64_mode.cpp

230

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_mode.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_mode.cpp

26

M64_Params& params = si.m64Params;

src/add-ons/accelerants/ati/mach64_mode.cpp

289

if (si.chipType < MACH64_264VTB)

src/add-ons/accelerants/ati/mach64_mode.cpp

326

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_mode.cpp

328

if (si.displayType == MT_VGA) {

src/add-ons/accelerants/ati/mach64_mode.cpp

334

if (si.chipType >= MACH64_264VTB)

src/add-ons/accelerants/ati/mach64_mode.cpp

377

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_mode.cpp

38

if (si.chipType >= MACH64_264VTB) {

src/add-ons/accelerants/ati/mach64_mode.cpp

383

address += si.frameBufferOffset;

src/add-ons/accelerants/ati/mach64_overlay.cpp

125

uint32 offset = (uint32)((addr_t)buffer->buffer - si.videoMemAddr);

src/add-ons/accelerants/ati/mach64_overlay.cpp

127

if (si.chipType < MACH64_264VTB) {

src/add-ons/accelerants/ati/mach64_overlay.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mach64_overlay.cpp

43

if (x2 > si.displayMode.timing.h_display)

src/add-ons/accelerants/ati/mach64_overlay.cpp

44

x2 = si.displayMode.timing.h_display;

src/add-ons/accelerants/ati/mach64_overlay.cpp

46

if (y2 > si.displayMode.timing.v_display)

src/add-ons/accelerants/ati/mach64_overlay.cpp

47

y2 = si.displayMode.timing.v_display;

src/add-ons/accelerants/ati/mach64_overlay.cpp

71

if (si.chipType >= MACH64_264GTPRO) {

src/add-ons/accelerants/ati/mach64_overlay.cpp

88

switch (si.displayMode.bitsPerPixel) {

src/add-ons/accelerants/ati/mode.cpp

109

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

121

if (si.displayType == MT_VGA) {

src/add-ons/accelerants/ati/mode.cpp

131

for (uint32 j = 0; j < si.colorSpaceCount; j++) {

src/add-ons/accelerants/ati/mode.cpp

132

if (mode->space == uint32(si.colorSpaces[j])) {

src/add-ons/accelerants/ati/mode.cpp

154

if (si.chipType == MACH64_MOBILITY && mode->timing.h_display == 640

src/add-ons/accelerants/ati/mode.cpp

171

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

180

si.bHaveEDID = false;

src/add-ons/accelerants/ati/mode.cpp

182

if (si.displayType == MT_VGA && !si.bHaveEDID) {

src/add-ons/accelerants/ati/mode.cpp

191

edid_decode(&si.edidInfo, &rawEdid); // decode & save EDID info

src/add-ons/accelerants/ati/mode.cpp

192

si.bHaveEDID = true;

src/add-ons/accelerants/ati/mode.cpp

196

if (si.bHaveEDID) {

src/add-ons/accelerants/ati/mode.cpp

198

edid_dump(&(si.edidInfo));

src/add-ons/accelerants/ati/mode.cpp

210

si.bHaveEDID ? &si.edidInfo : NULL,

src/add-ons/accelerants/ati/mode.cpp

211

NULL, 0, si.colorSpaces, si.colorSpaceCount,

src/add-ons/accelerants/ati/mode.cpp

217

si.modeArea = gInfo.modeListArea = listArea;

src/add-ons/accelerants/ati/mode.cpp

218

si.modeCount = count;

src/add-ons/accelerants/ati/mode.cpp

261

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

284

if (si.displayType == MT_VGA) {

src/add-ons/accelerants/ati/mode.cpp

308

si.displayMode = mode;

src/add-ons/accelerants/ati/mode.cpp

368

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

370

pFBC->frame_buffer = (void*)((addr_t)si.videoMemAddr + si.frameBufferOffset);

src/add-ons/accelerants/ati/mode.cpp

371

pFBC->frame_buffer_dma = (void*)((addr_t)si.videoMemPCI + si.frameBufferOffset);

src/add-ons/accelerants/ati/mode.cpp

372

uint32 bytesPerPixel = (si.displayMode.bitsPerPixel + 7) / 8;

src/add-ons/accelerants/ati/mode.cpp

373

pFBC->bytes_per_row = si.displayMode.virtual_width * bytesPerPixel;

src/add-ons/accelerants/ati/mode.cpp

422

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

424

if (si.displayType == MT_LAPTOP) {

src/add-ons/accelerants/ati/mode.cpp

425

display_mode* mode = FindDisplayMode(si.panelX, si.panelY, 60, 0);

src/add-ons/accelerants/ati/mode.cpp

440

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

442

if ( ! si.bHaveEDID)

src/add-ons/accelerants/ati/mode.cpp

448

memcpy(info, &si.edidInfo, sizeof(struct edid1_info));

src/add-ons/accelerants/ati/mode.cpp

82

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/mode.cpp

84

VesaMode* vesaModeTable = (VesaMode*)((uint8*)&si + si.vesaModeTableOffset);

src/add-ons/accelerants/ati/mode.cpp

86

for (uint32 j = 0; j < si.vesaModeCount; j++) {

src/add-ons/accelerants/ati/overlay.cpp

119

addr_t fbEndAddr = si.videoMemAddr + si.frameBufferOffset

src/add-ons/accelerants/ati/overlay.cpp

120

+ (si.displayMode.virtual_width

src/add-ons/accelerants/ati/overlay.cpp

121

* ((si.displayMode.bitsPerPixel + 7) / 8) // bytes per pixel

src/add-ons/accelerants/ati/overlay.cpp

122

* si.displayMode.virtual_height);

src/add-ons/accelerants/ati/overlay.cpp

125

si.overlayLock.Release();

src/add-ons/accelerants/ati/overlay.cpp

136

si.overlayLock.Release();

src/add-ons/accelerants/ati/overlay.cpp

147

ovBuff->buffer_dma = (void*)(si.videoMemPCI

src/add-ons/accelerants/ati/overlay.cpp

148

+ ((addr_t)ovBuff->buffer - si.videoMemAddr));

src/add-ons/accelerants/ati/overlay.cpp

151

si.overlayBuffer = ovBuff;

src/add-ons/accelerants/ati/overlay.cpp

155

si.overlayLock.Release();

src/add-ons/accelerants/ati/overlay.cpp

165

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/overlay.cpp

172

OverlayBuffer* ovBuff = si.overlayBuffer;

src/add-ons/accelerants/ati/overlay.cpp

181

si.overlayBuffer = ovBuff->nextBuffer;

src/add-ons/accelerants/ati/overlay.cpp

248

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/overlay.cpp

253

if (atomic_or(&si.overlayAllocated, 1) != 0) {

src/add-ons/accelerants/ati/overlay.cpp

258

return (overlay_token)(addr_t)++si.overlayToken;

src/add-ons/accelerants/ati/overlay.cpp

265

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/overlay.cpp

267

if (overlayToken != (overlay_token)(addr_t)si.overlayToken) {

src/add-ons/accelerants/ati/overlay.cpp

272

if (MACH64_FAMILY(si.chipType))

src/add-ons/accelerants/ati/overlay.cpp

277

atomic_and(&si.overlayAllocated, 0); // mark overlay as unallocated

src/add-ons/accelerants/ati/overlay.cpp

286

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/overlay.cpp

288

if (overlayToken != (overlay_token)(addr_t)si.overlayToken)

src/add-ons/accelerants/ati/overlay.cpp

295

if (MACH64_FAMILY(si.chipType))

src/add-ons/accelerants/ati/overlay.cpp

304

if (MACH64_FAMILY(si.chipType)) {

src/add-ons/accelerants/ati/overlay.cpp

50

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/overlay.cpp

57

if (MACH64_FAMILY(si.chipType)) {

src/add-ons/accelerants/ati/overlay.cpp

59

|| (width > 384 && si.chipType < MACH64_264VTB)

src/add-ons/accelerants/ati/overlay.cpp

60

|| (width > 720 && (si.chipType < MACH64_264GTPRO

src/add-ons/accelerants/ati/overlay.cpp

61

|| si.chipType > MACH64_264LTPRO)))

src/add-ons/accelerants/ati/overlay.cpp

65

si.overlayLock.Acquire();

src/add-ons/accelerants/ati/overlay.cpp

74

si.overlayLock.Release();

src/add-ons/accelerants/ati/overlay.cpp

85

OverlayBuffer* ovBuff = si.overlayBuffer;

src/add-ons/accelerants/ati/overlay.cpp

94

addr_t prevBuffAddr = (si.videoMemAddr + si.cursorOffset - 0xfff) & ~0xfff;

src/add-ons/accelerants/ati/rage128_cursor.cpp

33

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_cursor.cpp

52

OUTREG(R128_CUR_OFFSET, si.cursorOffset + yOffset * 16);

src/add-ons/accelerants/ati/rage128_cursor.cpp

59

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_cursor.cpp

66

uint32* fbCursor32 = (uint32*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/ati/rage128_cursor.cpp

84

uint8* fbCursor = (uint8*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/ati/rage128_dpms.cpp

58

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_dpms.cpp

60

TRACE("Rage128_SetDPMSMode() mode: %d, display type: %d\n", dpmsMode, si.displayType);

src/add-ons/accelerants/ati/rage128_dpms.cpp

94

if (si.displayType == MT_LAPTOP) {

src/add-ons/accelerants/ati/rage128_draw.cpp

104

si.r128_dpGuiMasterCntl = ((dataType << R128_GMC_DST_DATATYPE_SHIFT)

src/add-ons/accelerants/ati/rage128_draw.cpp

108

OUTREG(R128_DP_GUI_MASTER_CNTL, (si.r128_dpGuiMasterCntl

src/add-ons/accelerants/ati/rage128_draw.cpp

66

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_init.cpp

119

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_init.cpp

121

si.videoMemSize = INREG(R128_CONFIG_MEMSIZE);

src/add-ons/accelerants/ati/rage128_init.cpp

123

si.cursorOffset = (si.videoMemSize - CURSOR_BYTES) & ~0xfff; // align to 4k boundary

src/add-ons/accelerants/ati/rage128_init.cpp

124

si.frameBufferOffset = 0;

src/add-ons/accelerants/ati/rage128_init.cpp

125

si.maxFrameBufferSize = si.cursorOffset - si.frameBufferOffset;

src/add-ons/accelerants/ati/rage128_init.cpp

128

si.videoMemSize / 1024 / 1024, si.frameBufferOffset, si.cursorOffset);

src/add-ons/accelerants/ati/rage128_init.cpp

136

switch (si.deviceID) {

src/add-ons/accelerants/ati/rage128_init.cpp

164

si.r128MemSpec = sRAMSpecs[offset];

src/add-ons/accelerants/ati/rage128_init.cpp

165

TRACE("RAM type: %s\n", si.r128MemSpec.name);

src/add-ons/accelerants/ati/rage128_init.cpp

169

si.displayType = MT_VGA;

src/add-ons/accelerants/ati/rage128_init.cpp

172

si.displayType = MT_DVI;

src/add-ons/accelerants/ati/rage128_init.cpp

174

if (si.chipType == RAGE128_MOBILITY && si.panelX > 0 && si.panelY > 0) {

src/add-ons/accelerants/ati/rage128_init.cpp

176

si.displayType = MT_LAPTOP; // laptop LCD display is on

src/add-ons/accelerants/ati/rage128_init.cpp

181

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/ati/rage128_init.cpp

182

si.colorSpaces[1] = B_RGB15;

src/add-ons/accelerants/ati/rage128_init.cpp

183

si.colorSpaces[2] = B_RGB16;

src/add-ons/accelerants/ati/rage128_init.cpp

184

si.colorSpaces[3] = B_RGB32;

src/add-ons/accelerants/ati/rage128_init.cpp

185

si.colorSpaceCount = 4;

src/add-ons/accelerants/ati/rage128_mode.cpp

144

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_mode.cpp

145

R128_RAMSpec& memSpec = si.r128MemSpec;

src/add-ons/accelerants/ati/rage128_mode.cpp

146

R128_PLLParams& pll = si.r128PLLParams;

src/add-ons/accelerants/ati/rage128_mode.cpp

412

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_mode.cpp

418

address += si.frameBufferOffset;

src/add-ons/accelerants/ati/rage128_overlay.cpp

134

uint32 offset = (uint32)((addr_t)buffer->buffer - si.videoMemAddr);

src/add-ons/accelerants/ati/rage128_overlay.cpp

31

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/ati/rage128_overlay.cpp

42

switch (si.displayMode.bitsPerPixel) {

src/add-ons/accelerants/ati/rage128_overlay.cpp

97

if (si.displayMode.timing.pixel_clock < 125000)

src/add-ons/accelerants/ati/rage128_overlay.cpp

99

else if (si.displayMode.timing.pixel_clock < 250000)

src/add-ons/accelerants/et6x00/Acceleration.c

153

si->engine.count++;

src/add-ons/accelerants/et6x00/Acceleration.c

169

uint16 screenWidth = si->dm.virtual_width;

src/add-ons/accelerants/et6x00/Acceleration.c

170

uint8 bpp = si->bytesPerPixel;

src/add-ons/accelerants/et6x00/Acceleration.c

189

srcAddr = (uint32)si->framebuffer - (uint32)si->memory +

src/add-ons/accelerants/et6x00/Acceleration.c

190

si->dm.virtual_width * si->dm.virtual_height * bpp;

src/add-ons/accelerants/et6x00/Acceleration.c

196

((vuint16 *)((uint32)si->memory + srcAddr))[i] = (uint16)color;

src/add-ons/accelerants/et6x00/Acceleration.c

201

((vuint8 *)((uint32)si->memory + srcAddr))[i] = ((uint8 *)&color)[i];

src/add-ons/accelerants/et6x00/Acceleration.c

255

si->engine.count++;

src/add-ons/accelerants/et6x00/Acceleration.c

79

uint16 screenWidth = si->dm.virtual_width;

src/add-ons/accelerants/et6x00/Acceleration.c

80

uint8 bpp = si->bytesPerPixel;

src/add-ons/accelerants/et6x00/EngineManagment.c

23

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/et6x00/EngineManagment.c

36

st->counter = si->engine.count;

src/add-ons/accelerants/et6x00/EngineManagment.c

40

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/et6x00/EngineManagment.c

47

si->engine.lastIdle = si->engine.count;

src/add-ons/accelerants/et6x00/EngineManagment.c

52

st->counter = si->engine.count;

src/add-ons/accelerants/et6x00/EngineManagment.c

58

si->engine.lastIdle = st->counter;

src/add-ons/accelerants/et6x00/GetModeInfo.c

17

*current_mode = si->dm;

src/add-ons/accelerants/et6x00/GetModeInfo.c

26

*afb = si->fbc;

src/add-ons/accelerants/et6x00/GetModeInfo.c

43

case B_RGB24: clockLimit = si->pixelClockMax24; break;

src/add-ons/accelerants/et6x00/GetModeInfo.c

45

case B_RGB16: clockLimit = si->pixelClockMax16; break;

src/add-ons/accelerants/et6x00/GlobalData.c

11

ET6000SharedInfo *si;

src/add-ons/accelerants/et6x00/GlobalData.h

14

extern ET6000SharedInfo *si;

src/add-ons/accelerants/et6x00/InitAccelerant.c

101

si->engine.lastIdle = si->engine.count = 0;

src/add-ons/accelerants/et6x00/InitAccelerant.c

112

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/et6x00/InitAccelerant.c

187

(void **)&et6000ModesList, B_ANY_ADDRESS, B_READ_AREA, si->modesArea);

src/add-ons/accelerants/et6x00/InitAccelerant.c

222

adi->memory = si->memSize;

src/add-ons/accelerants/et6x00/InitAccelerant.c

223

adi->dac_speed = si->pixelClockMax16;

src/add-ons/accelerants/et6x00/InitAccelerant.c

34

sharedInfoArea = clone_area("ET6000 shared info", (void **)&si,

src/add-ons/accelerants/et6x00/InitAccelerant.c

41

mmRegs = si->mmRegs;

src/add-ons/accelerants/et6x00/InitAccelerant.c

53

si = 0;

src/add-ons/accelerants/et6x00/InitAccelerant.c

92

si->fbc.frame_buffer = si->framebuffer;

src/add-ons/accelerants/et6x00/InitAccelerant.c

93

si->fbc.frame_buffer_dma = si->physFramebuffer;

src/add-ons/accelerants/et6x00/InitAccelerant.c

96

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

102

si->modesArea = et6000ModesListArea =

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

112

si->modesNum = 0;

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

132

si->modesNum++;

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

65

mode.memSize = si->memSize;

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

75

return si->modesNum;

src/add-ons/accelerants/et6x00/ProposeDisplayMode.c

83

memcpy(dm, et6000ModesList, si->modesNum * sizeof(display_mode));

src/add-ons/accelerants/et6x00/SetDisplayMode.c

20

mode.pciConfigSpace = si->pciConfigSpace;

src/add-ons/accelerants/et6x00/SetDisplayMode.c

56

si->fbc.bytes_per_row = target.virtual_width * bpp;

src/add-ons/accelerants/et6x00/SetDisplayMode.c

57

si->dm = target;

src/add-ons/accelerants/et6x00/SetDisplayMode.c

58

si->bytesPerPixel = bpp;

src/add-ons/accelerants/intel_810/accelerant.cpp

114

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/accelerant.cpp

116

TRACE("Vendor ID: 0x%X, Device ID: 0x%X\n", si.vendorID, si.deviceID);

src/add-ons/accelerants/intel_810/accelerant.cpp

121

if (si.bAccelerantInUse) {

src/add-ons/accelerants/intel_810/accelerant.cpp

126

result = si.engineLock.Init("i810 engine lock");

src/add-ons/accelerants/intel_810/accelerant.cpp

130

si.bAccelerantInUse = true;

src/add-ons/accelerants/intel_810/accelerant.cpp

225

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/accelerant.cpp

229

strcpy(adi->chipset, si.chipName);

src/add-ons/accelerants/intel_810/accelerant.cpp

231

adi->memory = si.maxFrameBufferSize;

src/add-ons/accelerants/intel_810/accelerant.cpp

41

SharedInfo& si = *((SharedInfo*)dataPtr);

src/add-ons/accelerants/intel_810/accelerant.cpp

44

uint32* src = ((uint32*)(si.videoMemAddr)) + si.videoMemSize / 4 - 1;

src/add-ons/accelerants/intel_810/i810_init.cpp

54

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/i810_init.cpp

58

si.maxFrameBufferSize = si.videoMemSize;

src/add-ons/accelerants/intel_810/i810_init.cpp

62

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/intel_810/i810_init.cpp

63

si.colorSpaces[1] = B_RGB16;

src/add-ons/accelerants/intel_810/i810_init.cpp

64

si.colorSpaceCount = 2;

src/add-ons/accelerants/intel_810/mode.cpp

103

edid_decode(&si.edidInfo, &rawEdid); // decode & save EDID info

src/add-ons/accelerants/intel_810/mode.cpp

104

si.bHaveEDID = true;

src/add-ons/accelerants/intel_810/mode.cpp

108

if (si.bHaveEDID) {

src/add-ons/accelerants/intel_810/mode.cpp

110

edid_dump(&(si.edidInfo));

src/add-ons/accelerants/intel_810/mode.cpp

122

si.bHaveEDID ? &si.edidInfo : NULL,

src/add-ons/accelerants/intel_810/mode.cpp

123

NULL, 0, si.colorSpaces, si.colorSpaceCount,

src/add-ons/accelerants/intel_810/mode.cpp

129

si.modeArea = gInfo.modeListArea = listArea;

src/add-ons/accelerants/intel_810/mode.cpp

130

si.modeCount = count;

src/add-ons/accelerants/intel_810/mode.cpp

171

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/mode.cpp

217

si.displayMode = mode;

src/add-ons/accelerants/intel_810/mode.cpp

277

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/mode.cpp

279

pFBC->frame_buffer = (void*)((addr_t)(si.videoMemAddr));

src/add-ons/accelerants/intel_810/mode.cpp

280

pFBC->frame_buffer_dma = (void*)((addr_t)(si.videoMemPCI));

src/add-ons/accelerants/intel_810/mode.cpp

281

pFBC->bytes_per_row = si.displayMode.virtual_width

src/add-ons/accelerants/intel_810/mode.cpp

282

* si.displayMode.bytesPerPixel;

src/add-ons/accelerants/intel_810/mode.cpp

321

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/mode.cpp

323

if ( ! si.bHaveEDID)

src/add-ons/accelerants/intel_810/mode.cpp

329

memcpy(info, &si.edidInfo, sizeof(struct edid1_info));

src/add-ons/accelerants/intel_810/mode.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/mode.cpp

65

for (uint32 j = 0; j < si.colorSpaceCount; j++) {

src/add-ons/accelerants/intel_810/mode.cpp

66

if (mode->space == uint32(si.colorSpaces[j])) {

src/add-ons/accelerants/intel_810/mode.cpp

88

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/intel_810/mode.cpp

92

si.bHaveEDID = false;

src/add-ons/accelerants/intel_810/mode.cpp

94

if (!si.bHaveEDID) {

src/add-ons/accelerants/matrox/Cursor.c

101

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/matrox/Cursor.c

105

if (x >= ((si->dm.timing.h_display * 2) + hds))

src/add-ons/accelerants/matrox/Cursor.c

107

hds = ((x - (si->dm.timing.h_display * 2)) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/matrox/Cursor.c

109

if ((hds + (si->dm.timing.h_display * 2)) > si->dm.virtual_width)

src/add-ons/accelerants/matrox/Cursor.c

116

if (x >= (si->dm.timing.h_display + hds))

src/add-ons/accelerants/matrox/Cursor.c

118

hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/matrox/Cursor.c

120

if ((hds + si->dm.timing.h_display) > si->dm.virtual_width)

src/add-ons/accelerants/matrox/Cursor.c

128

if (y >= (si->dm.timing.v_display + vds))

src/add-ons/accelerants/matrox/Cursor.c

129

vds = y - si->dm.timing.v_display + 1;

src/add-ons/accelerants/matrox/Cursor.c

134

if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))

src/add-ons/accelerants/matrox/Cursor.c

141

x -= hds + si->cursor.hot_x;

src/add-ons/accelerants/matrox/Cursor.c

142

y -= vds + si->cursor.hot_y;

src/add-ons/accelerants/matrox/Cursor.c

145

if (si->switched_crtcs) x -= si->dm.timing.h_display;

src/add-ons/accelerants/matrox/Cursor.c

154

si->cursor.is_visible = is_visible;

src/add-ons/accelerants/matrox/Cursor.c

41

si->cursor.width = width;

src/add-ons/accelerants/matrox/Cursor.c

42

si->cursor.height = height;

src/add-ons/accelerants/matrox/Cursor.c

43

si->cursor.hot_x = hot_x;

src/add-ons/accelerants/matrox/Cursor.c

44

si->cursor.hot_y = hot_y;

src/add-ons/accelerants/matrox/Cursor.c

53

uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */

src/add-ons/accelerants/matrox/Cursor.c

54

uint16 vds = si->dm.v_display_start; /* the current vertical starting line */

src/add-ons/accelerants/matrox/Cursor.c

58

if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;

src/add-ons/accelerants/matrox/Cursor.c

59

if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;

src/add-ons/accelerants/matrox/Cursor.c

62

si->cursor.x = x;

src/add-ons/accelerants/matrox/Cursor.c

63

si->cursor.y = y;

src/add-ons/accelerants/matrox/Cursor.c

66

if (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/matrox/Cursor.c

68

switch(si->dm.space)

src/add-ons/accelerants/matrox/Cursor.c

83

switch(si->dm.space)

src/add-ons/accelerants/matrox/EngineManagment.c

26

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/matrox/EngineManagment.c

41

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/matrox/EngineManagment.c

55

st->counter = si->engine.count;

src/add-ons/accelerants/matrox/GetAccelerantHook.c

173

if (si->ps.card_type >= G200)

src/add-ons/accelerants/matrox/GetAccelerantHook.c

221

if (si->acc_mode)

src/add-ons/accelerants/matrox/GetAccelerantHook.c

226

((si->fbc.bytes_per_row * si->dm.virtual_height) > (16 * 1024 * 1024)))

src/add-ons/accelerants/matrox/GetAccelerantHook.c

33

#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed

src/add-ons/accelerants/matrox/GetDeviceInfo.c

18

strcpy(adi->name, si->adi.name);

src/add-ons/accelerants/matrox/GetDeviceInfo.c

19

strcpy(adi->chipset, si->adi.chipset);

src/add-ons/accelerants/matrox/GetDeviceInfo.c

21

adi->memory = (si->ps.memory_size * 1024 * 1024);

src/add-ons/accelerants/matrox/GetDeviceInfo.c

22

adi->dac_speed = si->ps.max_dac1_clock;

src/add-ons/accelerants/matrox/GetModeInfo.c

100

*low = ((si->ps.min_pixel_vco * 1000) / 16);

src/add-ons/accelerants/matrox/GetModeInfo.c

103

*low = ((si->ps.min_pixel_vco * 1000) / 8);

src/add-ons/accelerants/matrox/GetModeInfo.c

110

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/GetModeInfo.c

114

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/GetModeInfo.c

117

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/GetModeInfo.c

120

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/GetModeInfo.c

124

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/GetModeInfo.c

143

if (si->ps.int_assigned)

src/add-ons/accelerants/matrox/GetModeInfo.c

144

return si->vblank;

src/add-ons/accelerants/matrox/GetModeInfo.c

25

*current_mode = si->dm;

src/add-ons/accelerants/matrox/GetModeInfo.c

35

*afb = si->fbc;

src/add-ons/accelerants/matrox/GetModeInfo.c

57

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/GetModeInfo.c

61

*low = ((si->ps.min_video_vco * 1000) / 16);

src/add-ons/accelerants/matrox/GetModeInfo.c

64

*low = ((si->ps.min_video_vco * 1000) / 8);

src/add-ons/accelerants/matrox/GetModeInfo.c

71

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/matrox/GetModeInfo.c

75

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/GetModeInfo.c

78

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/matrox/GetModeInfo.c

82

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/GetModeInfo.c

86

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/GetModeInfo.c

96

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/InitAccelerant.c

122

if (si->accelerant_in_use)

src/add-ons/accelerants/matrox/InitAccelerant.c

129

si->crossed_conns = false;

src/add-ons/accelerants/matrox/InitAccelerant.c

154

si->cursor.width = 16;

src/add-ons/accelerants/matrox/InitAccelerant.c

155

si->cursor.height = 16;

src/add-ons/accelerants/matrox/InitAccelerant.c

156

si->cursor.hot_x = 0;

src/add-ons/accelerants/matrox/InitAccelerant.c

157

si->cursor.hot_y = 0;

src/add-ons/accelerants/matrox/InitAccelerant.c

158

si->cursor.x = 0;

src/add-ons/accelerants/matrox/InitAccelerant.c

159

si->cursor.y = 0;

src/add-ons/accelerants/matrox/InitAccelerant.c

168

if ((si->ps.card_type >= G100) && si->settings.hardcursor)

src/add-ons/accelerants/matrox/InitAccelerant.c

171

si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);

src/add-ons/accelerants/matrox/InitAccelerant.c

172

si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);

src/add-ons/accelerants/matrox/InitAccelerant.c

175

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/matrox/InitAccelerant.c

176

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/matrox/InitAccelerant.c

178

INIT_BEN(si->overlay.lock);

src/add-ons/accelerants/matrox/InitAccelerant.c

182

si->overlay.myBuffer[cnt].buffer = NULL;

src/add-ons/accelerants/matrox/InitAccelerant.c

183

si->overlay.myBuffer[cnt].buffer_dma = NULL;

src/add-ons/accelerants/matrox/InitAccelerant.c

186

si->overlay.myToken = NULL;

src/add-ons/accelerants/matrox/InitAccelerant.c

189

si->overlay.active = false;

src/add-ons/accelerants/matrox/InitAccelerant.c

198

si->dpms_flags = B_DPMS_ON;

src/add-ons/accelerants/matrox/InitAccelerant.c

203

si->accelerant_in_use = true;

src/add-ons/accelerants/matrox/InitAccelerant.c

285

if (!(si->accelerant_in_use))

src/add-ons/accelerants/matrox/InitAccelerant.c

297

si->mode_area

src/add-ons/accelerants/matrox/InitAccelerant.c

328

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/matrox/InitAccelerant.c

329

DELETE_BEN(si->overlay.lock);

src/add-ons/accelerants/matrox/InitAccelerant.c

332

si->accelerant_in_use = false;

src/add-ons/accelerants/matrox/InitAccelerant.c

36

shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS,

src/add-ons/accelerants/matrox/InitAccelerant.c

44

si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.greensync));

src/add-ons/accelerants/matrox/InitAccelerant.c

48

if (si->use_clone_bugfix)

src/add-ons/accelerants/matrox/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/matrox/InitAccelerant.c

58

B_READ_AREA | B_WRITE_AREA, si->regs_area);

src/add-ons/accelerants/matrox/InitAccelerant.c

87

si = 0;

src/add-ons/accelerants/matrox/Overlay.c

115

si->overlay.myBuffer[offset].width = width;

src/add-ons/accelerants/matrox/Overlay.c

119

si->overlay.myBuffer[offset].width = (width & ~0x0007) + 8;

src/add-ons/accelerants/matrox/Overlay.c

121

si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;

src/add-ons/accelerants/matrox/Overlay.c

126

if (si->overlay.myBuffer[offset].width > 4088)

src/add-ons/accelerants/matrox/Overlay.c

131

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

172

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

179

if (si->ps.card_type < G450) {

src/add-ons/accelerants/matrox/Overlay.c

180

if (si->overlay.myBuffer[offset].width > 1024) {

src/add-ons/accelerants/matrox/Overlay.c

184

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

194

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

199

if (si->overlay.myBuffer[offset].width > 1920) {

src/add-ons/accelerants/matrox/Overlay.c

203

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

213

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

220

si->overlay.myBufInfo[offset].slopspace = si->overlay.myBuffer[offset].width - width;

src/add-ons/accelerants/matrox/Overlay.c

222

si->overlay.myBuffer[offset].space = cs;

src/add-ons/accelerants/matrox/Overlay.c

223

si->overlay.myBuffer[offset].height = height;

src/add-ons/accelerants/matrox/Overlay.c

249

adress2 = (((uintptr_t)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */

src/add-ons/accelerants/matrox/Overlay.c

250

(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */

src/add-ons/accelerants/matrox/Overlay.c

254

oldsize = si->overlay.myBufInfo[offset].size;

src/add-ons/accelerants/matrox/Overlay.c

255

si->overlay.myBufInfo[offset].size

src/add-ons/accelerants/matrox/Overlay.c

256

= si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;

src/add-ons/accelerants/matrox/Overlay.c

269

adress = (((uintptr_t)((uint8*)si->framebuffer)) + (si->ps.memory_size * 1024 * 1024));

src/add-ons/accelerants/matrox/Overlay.c

272

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/matrox/Overlay.c

280

temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));

src/add-ons/accelerants/matrox/Overlay.c

285

si->overlay.myBufInfo[offset].size += (temp32 - (temp32 & 0xfffffff0));

src/add-ons/accelerants/matrox/Overlay.c

306

if (si->overlay.myBuffer[cnt].buffer != NULL)

src/add-ons/accelerants/matrox/Overlay.c

309

if (si->overlay.myBufInfo[offset].size <= oldsize)

src/add-ons/accelerants/matrox/Overlay.c

313

adress -= (oldsize - si->overlay.myBufInfo[offset].size);

src/add-ons/accelerants/matrox/Overlay.c

314

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/matrox/Overlay.c

327

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/matrox/Overlay.c

330

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

345

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

350

si->overlay.myBuffer[offset].buffer = (void *) adress;

src/add-ons/accelerants/matrox/Overlay.c

363

adress = (((uintptr_t)((uint8*)si->framebuffer_pci)) + (si->ps.memory_size * 1024 * 1024));

src/add-ons/accelerants/matrox/Overlay.c

366

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/matrox/Overlay.c

369

si->overlay.myBuffer[offset].buffer_dma = (void *) adress;

src/add-ons/accelerants/matrox/Overlay.c

372

(uint8*)si->overlay.myBuffer[offset].buffer,

src/add-ons/accelerants/matrox/Overlay.c

373

(uint8*)si->overlay.myBuffer[offset].buffer_dma, cs));

src/add-ons/accelerants/matrox/Overlay.c

374

LOG(4, ("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));

src/add-ons/accelerants/matrox/Overlay.c

377

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

379

return &si->overlay.myBuffer[offset];

src/add-ons/accelerants/matrox/Overlay.c

385

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

402

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/matrox/Overlay.c

408

si->overlay.myBuffer[offset].buffer = NULL;

src/add-ons/accelerants/matrox/Overlay.c

409

si->overlay.myBuffer[offset].buffer_dma = NULL;

src/add-ons/accelerants/matrox/Overlay.c

449

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/matrox/Overlay.c

513

if (si->dm.timing.pixel_clock > BESMAXSPEED)

src/add-ons/accelerants/matrox/Overlay.c

516

oc->h_scale.max = (16384 * 2)/(float)(ob->width - si->overlay.myBufInfo[offset].slopspace);

src/add-ons/accelerants/matrox/Overlay.c

521

oc->h_scale.max = 16384/(float)(ob->width - si->overlay.myBufInfo[offset].slopspace);

src/add-ons/accelerants/matrox/Overlay.c

546

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

549

if (si->overlay.myToken == NULL)

src/add-ons/accelerants/matrox/Overlay.c

554

si->overlay.myToken = &tmpToken;

src/add-ons/accelerants/matrox/Overlay.c

557

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

559

return si->overlay.myToken;

src/add-ons/accelerants/matrox/Overlay.c

567

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

578

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/matrox/Overlay.c

593

si->overlay.myToken = NULL;

src/add-ons/accelerants/matrox/Overlay.c

636

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/matrox/Overlay.c

649

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/matrox/Overlay.c

87

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/matrox/Overlay.c

89

LOG(4, ("Overlay: cardRAM_start = $%p\n", (uint8*)si->framebuffer));

src/add-ons/accelerants/matrox/Overlay.c

90

LOG(4, ("Overlay: cardRAM_start_DMA = $%p\n", (uint8*)si->framebuffer_pci));

src/add-ons/accelerants/matrox/Overlay.c

91

LOG(4, ("Overlay: cardRAM_size = %dMb\n", si->ps.memory_size));

src/add-ons/accelerants/matrox/Overlay.c

96

if (si->overlay.myBuffer[offset].buffer == NULL) break;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

257

if ((si->ps.card_type >= G100) && si->settings.hardcursor) pointer_reservation = 1024;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

260

((si->ps.memory_size * 1024 * 1024) - pointer_reservation))

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

263

((si->ps.memory_size * 1024 * 1024) - pointer_reservation) / row_bytes;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

299

max_vclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

304

max_vclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

308

max_vclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

312

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

317

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

324

if (si->ps.secondary_head &&

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

330

if (si->ps.card_type <= G400MAX) vblank_fix = 1;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

336

if ((((si->ps.memory_size * 1024 * 1024) - pointer_reservation) >=

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

344

if (((si->ps.memory_size * 1024 * 1024) - pointer_reservation) >=

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

351

if (((si->ps.memory_size * 1024 * 1024) - pointer_reservation) >=

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

367

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

372

if (si->ps.tvout &&

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

382

if (si->ps.tvout &&

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

395

if (si->ps.tvout &&

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

408

if (si->ps.secondary_head && (i2c_sec_tv_adapter() != B_OK))

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

421

if ((target->flags & TV_BITS) && !si->ps.secondary_head)

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

431

if (si->settings.hardcursor)

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

435

if (si->ps.card_type >= G200)

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

444

if (si->settings.greensync)

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

458

LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

460

return si->mode_count;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

468

memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

490

si->mode_area = my_mode_list_area =

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

498

si->mode_count = 0;

src/add-ons/accelerants/matrox/ProposeDisplayMode.c

527

si->mode_count++;

src/add-ons/accelerants/matrox/SetDisplayMode.c

147

si->interlaced_tv_mode = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

148

if ((target2.flags & TV_BITS) && (si->ps.card_type >= G450))

src/add-ons/accelerants/matrox/SetDisplayMode.c

149

si->interlaced_tv_mode = true;

src/add-ons/accelerants/matrox/SetDisplayMode.c

161

si->crtc_delay = 44;

src/add-ons/accelerants/matrox/SetDisplayMode.c

162

if (colour_depth2 == 16) si->crtc_delay += 0;

src/add-ons/accelerants/matrox/SetDisplayMode.c

165

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/SetDisplayMode.c

179

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

188

si->switched_crtcs = true;

src/add-ons/accelerants/matrox/SetDisplayMode.c

196

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

198

si->crtc_delay = 17;

src/add-ons/accelerants/matrox/SetDisplayMode.c

199

if (colour_depth1 == 16) si->crtc_delay += 4;

src/add-ons/accelerants/matrox/SetDisplayMode.c

211

if (!si->ps.primary_dvi)

src/add-ons/accelerants/matrox/SetDisplayMode.c

220

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

229

si->switched_crtcs = true;

src/add-ons/accelerants/matrox/SetDisplayMode.c

237

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

24

if (si->ps.int_assigned)

src/add-ons/accelerants/matrox/SetDisplayMode.c

253

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

260

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

270

si->switched_crtcs = true;

src/add-ons/accelerants/matrox/SetDisplayMode.c

276

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

286

if (si->switched_crtcs)

src/add-ons/accelerants/matrox/SetDisplayMode.c

313

if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2);

src/add-ons/accelerants/matrox/SetDisplayMode.c

344

if (si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/SetDisplayMode.c

359

si->interlaced_tv_mode = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

368

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/SetDisplayMode.c

374

if (!si->ps.secondary_head && si->ps.tvout && (target.flags & TV_BITS))

src/add-ons/accelerants/matrox/SetDisplayMode.c

389

if (!si->ps.secondary_head && si->ps.tvout && (target.flags & TV_BITS))

src/add-ons/accelerants/matrox/SetDisplayMode.c

392

si->crtc_delay = 17;

src/add-ons/accelerants/matrox/SetDisplayMode.c

393

if (colour_depth1 == 16) si->crtc_delay += 4;

src/add-ons/accelerants/matrox/SetDisplayMode.c

405

si->dm = target;

src/add-ons/accelerants/matrox/SetDisplayMode.c

411

SET_DPMS_MODE(si->dpms_flags);

src/add-ons/accelerants/matrox/SetDisplayMode.c

418

if ((target.flags & DUALHEAD_BITS) && (si->ps.card_type <= G400MAX))

src/add-ons/accelerants/matrox/SetDisplayMode.c

451

if (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/matrox/SetDisplayMode.c

453

switch(si->dm.space)

src/add-ons/accelerants/matrox/SetDisplayMode.c

464

LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));

src/add-ons/accelerants/matrox/SetDisplayMode.c

470

switch(si->dm.space)

src/add-ons/accelerants/matrox/SetDisplayMode.c

490

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/matrox/SetDisplayMode.c

494

if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/matrox/SetDisplayMode.c

498

if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/matrox/SetDisplayMode.c

502

if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)

src/add-ons/accelerants/matrox/SetDisplayMode.c

506

si->dm.h_display_start = h_display_start;

src/add-ons/accelerants/matrox/SetDisplayMode.c

507

si->dm.v_display_start = v_display_start;

src/add-ons/accelerants/matrox/SetDisplayMode.c

511

startadd = v_display_start * si->fbc.bytes_per_row;

src/add-ons/accelerants/matrox/SetDisplayMode.c

513

startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/matrox/SetDisplayMode.c

514

startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);

src/add-ons/accelerants/matrox/SetDisplayMode.c

517

if (si->switched_crtcs)

src/add-ons/accelerants/matrox/SetDisplayMode.c

526

switch (si->dm.flags&DUALHEAD_BITS)

src/add-ons/accelerants/matrox/SetDisplayMode.c

554

if (si->dm.space != B_CMAP8) return;

src/add-ons/accelerants/matrox/SetDisplayMode.c

556

r=si->color_data;

src/add-ons/accelerants/matrox/SetDisplayMode.c

579

si->dpms_flags = dpms_flags;

src/add-ons/accelerants/matrox/SetDisplayMode.c

581

if (si->dm.flags & DUALHEAD_BITS) /* dualhead */

src/add-ons/accelerants/matrox/SetDisplayMode.c

587

if (si->ps.secondary_head) g400_crtc2_dpms(true, true, true);

src/add-ons/accelerants/matrox/SetDisplayMode.c

590

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

599

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/SetDisplayMode.c

601

if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))

src/add-ons/accelerants/matrox/SetDisplayMode.c

613

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

622

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/SetDisplayMode.c

624

if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))

src/add-ons/accelerants/matrox/SetDisplayMode.c

636

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

645

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/SetDisplayMode.c

647

if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))

src/add-ons/accelerants/matrox/SetDisplayMode.c

671

if (si->dm.flags & TV_BITS) gx00_maven_dpms(true, true, true);

src/add-ons/accelerants/matrox/SetDisplayMode.c

674

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

684

if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, false, true);

src/add-ons/accelerants/matrox/SetDisplayMode.c

687

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

697

if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, true, false);

src/add-ons/accelerants/matrox/SetDisplayMode.c

700

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

71

si->switched_crtcs = false;

src/add-ons/accelerants/matrox/SetDisplayMode.c

710

if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, false, false);

src/add-ons/accelerants/matrox/SetDisplayMode.c

725

if (si->settings.greensync)

src/add-ons/accelerants/matrox/SetDisplayMode.c

738

return si->dpms_flags;

src/add-ons/accelerants/matrox/SetDisplayMode.c

78

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/SetDisplayMode.c

85

if (si->ps.tvout) gx00_maven_dpms(false, false, false);

src/add-ons/accelerants/matrox/SetDisplayMode.c

89

startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/matrox/SetDisplayMode.c

92

gx00_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);

src/add-ons/accelerants/matrox/engine/mga_acc.c

104

si->engine.y_lin = 0x01;

src/add-ons/accelerants/matrox/engine/mga_acc.c

108

ACCW(PITCH, (si->engine.y_lin << 15) |

src/add-ons/accelerants/matrox/engine/mga_acc.c

109

((si->fbc.bytes_per_row / (si->engine.depth >> 3)) & 0x0FFF));

src/add-ons/accelerants/matrox/engine/mga_acc.c

112

switch (si->fbc.bytes_per_row / (si->engine.depth >> 3))

src/add-ons/accelerants/matrox/engine/mga_acc.c

131

si->engine.y_lin = 0x01;

src/add-ons/accelerants/matrox/engine/mga_acc.c

135

ACCW(PITCH, (si->engine.y_lin << 15) |

src/add-ons/accelerants/matrox/engine/mga_acc.c

136

((si->fbc.bytes_per_row / (si->engine.depth >> 3)) & 0x0FFF));

src/add-ons/accelerants/matrox/engine/mga_acc.c

141

ACCW(PITCH, ((si->fbc.bytes_per_row / (si->engine.depth >> 3)) & 0x0FFF));

src/add-ons/accelerants/matrox/engine/mga_acc.c

147

ACCW(PITCH, ((si->fbc.bytes_per_row / (si->engine.depth >> 3)) & 0x1FFF));

src/add-ons/accelerants/matrox/engine/mga_acc.c

155

if (si->ps.card_type >= G200) {

src/add-ons/accelerants/matrox/engine/mga_acc.c

157

ACCW(DSTORG,((uint8*)si->fbc.frame_buffer) - ((uint8*)si->framebuffer));

src/add-ons/accelerants/matrox/engine/mga_acc.c

160

ACCW(SRCORG,((uint8*)si->fbc.frame_buffer) - ((uint8*)si->framebuffer));

src/add-ons/accelerants/matrox/engine/mga_acc.c

164

si->engine.src_dst = 0;

src/add-ons/accelerants/matrox/engine/mga_acc.c

165

ACCW(YDSTORG, si->engine.src_dst);

src/add-ons/accelerants/matrox/engine/mga_acc.c

169

if ((si->ps.card_type == G100) && (si->settings.hardcursor))

src/add-ons/accelerants/matrox/engine/mga_acc.c

171

switch (si->dm.space)

src/add-ons/accelerants/matrox/engine/mga_acc.c

174

si->engine.src_dst = 1024 / 1;

src/add-ons/accelerants/matrox/engine/mga_acc.c

178

si->engine.src_dst = 1024 / 2;

src/add-ons/accelerants/matrox/engine/mga_acc.c

181

si->engine.src_dst = 1024 / 4;

src/add-ons/accelerants/matrox/engine/mga_acc.c

188

ACCW(YDSTORG, si->engine.src_dst);

src/add-ons/accelerants/matrox/engine/mga_acc.c

192

ACCW(CXBNDRY,(((si->fbc.bytes_per_row / (si->engine.depth >> 3)) - 1) << 16) | (0));

src/add-ons/accelerants/matrox/engine/mga_acc.c

196

ACCW(YTOP, 0 + si->engine.src_dst);

src/add-ons/accelerants/matrox/engine/mga_acc.c

198

ACCW(YBOT,((si->dm.virtual_height - 1) *

src/add-ons/accelerants/matrox/engine/mga_acc.c

199

(si->fbc.bytes_per_row / (si->engine.depth >> 3))) + si->engine.src_dst);

src/add-ons/accelerants/matrox/engine/mga_acc.c

22

if (si->engine.y_lin) { \

src/add-ons/accelerants/matrox/engine/mga_acc.c

221

offset = (si->fbc.bytes_per_row / (si->engine.depth >> 3));

src/add-ons/accelerants/matrox/engine/mga_acc.c

227

list[i].src_left + (offset * list[i].src_top) + si->engine.src_dst;

src/add-ons/accelerants/matrox/engine/mga_acc.c

23

ACCW(YDST,((dst)* (si->fbc.bytes_per_row / (si->engine.depth >> 3))) >> 5); \

src/add-ons/accelerants/matrox/engine/mga_acc.c

231

list[i].src_left + (offset * (list[i].src_top + list[i].height)) + si->engine.src_dst;

src/add-ons/accelerants/matrox/engine/mga_acc.c

288

offset = (si->fbc.bytes_per_row / (si->engine.depth >> 3));

src/add-ons/accelerants/matrox/engine/mga_acc.c

294

list[i].src_left + (offset * list[i].src_top) + si->engine.src_dst;

src/add-ons/accelerants/matrox/engine/mga_acc.c

298

list[i].src_left + (offset * (list[i].src_top + list[i].height)) + si->engine.src_dst;

src/add-ons/accelerants/matrox/engine/mga_acc.c

392

if ((si->dm.space == B_CMAP8) || si->ps.sdram)

src/add-ons/accelerants/matrox/engine/mga_acc.c

428

if ((si->dm.space == B_CMAP8) || si->ps.sdram)

src/add-ons/accelerants/matrox/engine/mga_acc.c

47

if ((si->ps.card_type >= G450) && (si->ps.pins_status == B_OK))

src/add-ons/accelerants/matrox/engine/mga_acc.c

50

maccess |= ((((uint32)si->ps.v5_mem_type) & 0x80) >> 1);

src/add-ons/accelerants/matrox/engine/mga_acc.c

54

si->engine.y_lin = 0x00;

src/add-ons/accelerants/matrox/engine/mga_acc.c

56

si->engine.depth = 0;

src/add-ons/accelerants/matrox/engine/mga_acc.c

65

switch(si->dm.space)

src/add-ons/accelerants/matrox/engine/mga_acc.c

69

si->engine.depth = 8;

src/add-ons/accelerants/matrox/engine/mga_acc.c

73

si->engine.depth = 16;

src/add-ons/accelerants/matrox/engine/mga_acc.c

77

si->engine.depth = 32;

src/add-ons/accelerants/matrox/engine/mga_acc.c

85

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_acc.c

88

switch (si->fbc.bytes_per_row / (si->engine.depth >> 3))

src/add-ons/accelerants/matrox/engine/mga_bes.c

103

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

111

temp2 = ((uint16)(si->overlay.ow.h_start + si->overlay.ow.width - crtc_hstart - 1)) & 0x7ff;

src/add-ons/accelerants/matrox/engine/mga_bes.c

122

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/matrox/engine/mga_bes.c

129

if (si->overlay.ow.v_start >= (crtc_vend - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

137

temp1 = (si->overlay.ow.v_start - crtc_vstart) & 0x7ff;

src/add-ons/accelerants/matrox/engine/mga_bes.c

143

if (si->overlay.ow.height < 2)

src/add-ons/accelerants/matrox/engine/mga_bes.c

150

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) > (crtc_vend - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

157

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

165

temp2 = ((uint16)(si->overlay.ow.v_start + si->overlay.ow.height - crtc_vstart - 1)) & 0x7ff;

src/add-ons/accelerants/matrox/engine/mga_bes.c

187

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/matrox/engine/mga_bes.c

191

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

194

moi->hsrcstv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/matrox/engine/mga_bes.c

199

moi->hsrcstv += (crtc_hstart - si->overlay.ow.h_start);

src/add-ons/accelerants/matrox/engine/mga_bes.c

205

moi->hsrcstv *= si->overlay.h_ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

208

moi->hsrcstv += ((uint32)si->overlay.my_ov.h_start) << 16;

src/add-ons/accelerants/matrox/engine/mga_bes.c

222

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

226

if (si->overlay.ow.h_start > (crtc_hend - 2))

src/add-ons/accelerants/matrox/engine/mga_bes.c

229

moi->hsrcendv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/matrox/engine/mga_bes.c

234

moi->hsrcendv += ((si->overlay.ow.h_start + si->overlay.ow.width - 1) - (crtc_hend - 1));

src/add-ons/accelerants/matrox/engine/mga_bes.c

240

moi->hsrcendv *= si->overlay.h_ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

242

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16) - moi->hsrcendv;

src/add-ons/accelerants/matrox/engine/mga_bes.c

247

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16);

src/add-ons/accelerants/matrox/engine/mga_bes.c

273

moi->a1orgv = (uintptr_t)((vuint32 *)si->overlay.ob.buffer);

src/add-ons/accelerants/matrox/engine/mga_bes.c

274

moi->a1orgv -= (uintptr_t)((vuint32 *)si->framebuffer);

src/add-ons/accelerants/matrox/engine/mga_bes.c

277

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/matrox/engine/mga_bes.c

281

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

286

moi->v1srcstv = (si->overlay.ow.height - 2) * si->overlay.v_ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

287

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/matrox/engine/mga_bes.c

292

moi->v1srcstv = (crtc_vstart - si->overlay.ow.v_start) * si->overlay.v_ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

293

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/matrox/engine/mga_bes.c

298

moi->v1srcstv += (((uint32)si->overlay.my_ov.v_start) << 16);

src/add-ons/accelerants/matrox/engine/mga_bes.c

299

moi->a1orgv += (si->overlay.my_ov.v_start * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/matrox/engine/mga_bes.c

32

if (!si->overlay.active) return;

src/add-ons/accelerants/matrox/engine/mga_bes.c

336

while ((uint16)CR1R(VCOUNT) > (si->dm.timing.v_total - 200)) snooze(4);

src/add-ons/accelerants/matrox/engine/mga_bes.c

390

LOG(4,("Overlay: pixelclock is %dkHz, ", si->dm.timing.pixel_clock));

src/add-ons/accelerants/matrox/engine/mga_bes.c

391

if (si->dm.timing.pixel_clock > BESMAXSPEED)

src/add-ons/accelerants/matrox/engine/mga_bes.c

419

if (my_ov.h_start > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

420

my_ov.h_start = ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1);

src/add-ons/accelerants/matrox/engine/mga_bes.c

421

if (((my_ov.h_start + my_ov.width) - 1) > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

422

my_ov.width = ((((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1) - my_ov.h_start) + 1);

src/add-ons/accelerants/matrox/engine/mga_bes.c

432

si->overlay.ow = *ow;

src/add-ons/accelerants/matrox/engine/mga_bes.c

433

si->overlay.ob = *ob;

src/add-ons/accelerants/matrox/engine/mga_bes.c

434

si->overlay.my_ov = my_ov;

src/add-ons/accelerants/matrox/engine/mga_bes.c

442

(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));

src/add-ons/accelerants/matrox/engine/mga_bes.c

47

crtc_hstart = si->dm.h_display_start;

src/add-ons/accelerants/matrox/engine/mga_bes.c

485

si->overlay.h_ifactor = ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

49

if (si->switched_crtcs)

src/add-ons/accelerants/matrox/engine/mga_bes.c

51

crtc_hstart += si->dm.timing.h_display;

src/add-ons/accelerants/matrox/engine/mga_bes.c

54

crtc_hend = crtc_hstart + si->dm.timing.h_display;

src/add-ons/accelerants/matrox/engine/mga_bes.c

549

si->overlay.v_ifactor = ifactor;

src/add-ons/accelerants/matrox/engine/mga_bes.c

55

crtc_vstart = si->dm.v_display_start;

src/add-ons/accelerants/matrox/engine/mga_bes.c

57

crtc_vend = crtc_vstart + si->dm.timing.v_display;

src/add-ons/accelerants/matrox/engine/mga_bes.c

580

hsrclstv = ((ob->width - 1) - si->overlay.myBufInfo[offset].slopspace) << 16;

src/add-ons/accelerants/matrox/engine/mga_bes.c

68

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/matrox/engine/mga_bes.c

715

while ((uint16)CR1R(VCOUNT) > (si->dm.timing.v_total - 200)) snooze(4);

src/add-ons/accelerants/matrox/engine/mga_bes.c

75

if (si->overlay.ow.h_start >= (crtc_hend - 1))

src/add-ons/accelerants/matrox/engine/mga_bes.c

775

si->overlay.active = true;

src/add-ons/accelerants/matrox/engine/mga_bes.c

786

si->overlay.active = false;

src/add-ons/accelerants/matrox/engine/mga_bes.c

83

temp1 = (si->overlay.ow.h_start - crtc_hstart) & 0x7ff;

src/add-ons/accelerants/matrox/engine/mga_bes.c

89

if (si->overlay.ow.width < 2)

src/add-ons/accelerants/matrox/engine/mga_bes.c

96

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/matrox/engine/mga_crtc.c

236

if (si->ps.card_type < G100) do { // apsed TODO in caller

src/add-ons/accelerants/matrox/engine/mga_crtc.c

237

if (si->ps.memory_size <= 2) { viddelay = 1<<3; break;}

src/add-ons/accelerants/matrox/engine/mga_crtc.c

238

if (si->ps.memory_size <= 4) { viddelay = 0<<3; break;}

src/add-ons/accelerants/matrox/engine/mga_crtc.c

243

if (si->settings.greensync)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

246

if (si->ps.card_type <= MIL2)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

258

if (si->ps.card_type <= MIL2)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

329

if (si->ps.card_type >= G450)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

331

if (si->crossed_conns)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

34

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

354

offset = si->fbc.bytes_per_row / 16;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

374

LOG(2,("CRTC: frameRAM: %x\n",si->framebuffer));

src/add-ons/accelerants/matrox/engine/mga_crtc.c

375

LOG(2,("CRTC: framebuffer: %x\n",si->fbc.frame_buffer));

src/add-ons/accelerants/matrox/engine/mga_crtc.c

379

if (si->ps.card_type < G100)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

400

if (si->ps.card_type>=G200)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

404

if (si->ps.card_type>=G400)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

419

if (si->settings.usebios || (si->ps.pins_status != B_OK))

src/add-ons/accelerants/matrox/engine/mga_crtc.c

426

if (si->ps.card_type != G200)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

439

switch ((si->ps.memrdbk_reg & 0x00c00000) >> 22)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

460

tpixclk = 1000000 / si->dm.timing.pixel_clock;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

463

if (si->ps.v3_option2_reg & 0x08)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

465

tmclk = 1000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

469

if (si->ps.v3_clk_div & 0x02)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

470

tmclk = 3000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

472

tmclk = 2000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

476

refresh = ((si->dm.timing.pixel_clock * 1000) /

src/add-ons/accelerants/matrox/engine/mga_crtc.c

477

((uint32)si->dm.timing.h_total * (uint32)si->dm.timing.v_total));

src/add-ons/accelerants/matrox/engine/mga_crtc.c

487

if ((si->dm.timing.v_display > 768) && (hiprilvl > 3)) hiprilvl = 3;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

488

if ((si->dm.timing.v_display > 864) && (hiprilvl > 2) && (refresh >= 76.0)) hiprilvl = 2;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

489

if ((si->dm.timing.v_display > 1024) && (hiprilvl > 2)) hiprilvl = 2;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

513

if (si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

538

fb = (vuint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

587

if ((si->ps.card_type < G100) && (si->dm.timing.h_total > 2048))

src/add-ons/accelerants/matrox/engine/mga_crtc.c

611

if(si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/engine/mga_crtc.c

616

cursor = (vuint8*) si->framebuffer;

src/add-ons/accelerants/matrox/engine/mga_crtc.c

73

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

166

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

184

if (si->ps.secondary_head) gx00_maven_dpms(display, h, v);

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

19

if ((!(target.flags & TV_BITS)) || (si->ps.card_type <= G400MAX))

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

206

if (si->crossed_conns)

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

277

offset = si->fbc.bytes_per_row;

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

278

if (si->interlaced_tv_mode)

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

299

LOG(2,("CRTC2: frameRAM: $%x\n",si->framebuffer));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

300

LOG(2,("CRTC2: framebuffer: $%x\n",si->fbc.frame_buffer));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

302

if (si->interlaced_tv_mode)

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

308

CR2W(STARTADD0, (startadd + si->fbc.bytes_per_row));

src/add-ons/accelerants/matrox/engine/mga_crtc2.c

59

if ((si->ps.secondary_head) && (!(target.flags & TV_BITS)))

src/add-ons/accelerants/matrox/engine/mga_dac.c

1001

if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))

src/add-ons/accelerants/matrox/engine/mga_dac.c

1007

n = (int)(((f_vco * m) / (si->ps.f_ref * 2)) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1013

error = fabs(req_sclk - ((((si->ps.f_ref * 2)/ m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_dac.c

1050

f_vco = ((si->ps.f_ref * 2) / (m + 1)) * (n + 2);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1080

g100_g400max_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1111

if (si->ps.v3_clk_div & 0x01) temp |= 0x08;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1112

if (si->ps.v3_clk_div & 0x02) temp |= 0x10;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1113

if (si->ps.v3_clk_div & 0x04) temp |= 0x80;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1136

g100_g400max_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1168

if (si->ps.v3_option2_reg & 0x04) temp |= 0x00004000;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1169

if (si->ps.v3_option2_reg & 0x08) temp |= 0x00008000;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1170

if (si->ps.v3_option2_reg & 0x10) temp |= 0x00010000;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1171

if (si->ps.v3_option2_reg & 0x20) temp |= 0x00020000;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1175

if (si->ps.v3_clk_div & 0x01) temp |= 0x08;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1176

if (si->ps.v3_clk_div & 0x02) temp |= 0x10;

src/add-ons/accelerants/matrox/engine/mga_dac.c

1198

g100_g400max_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1230

CFGW(OPTION3, si->ps.option3_reg);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1252

CFGW(OPTION, si->ps.option_reg);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1261

g450_g550_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1283

CFGW(OPTION3, si->ps.option3_reg);

src/add-ons/accelerants/matrox/engine/mga_dac.c

1285

CFGW(OPTION2, si->ps.option2_reg);

src/add-ons/accelerants/matrox/engine/mga_dac.c

30

r=si->color_data;

src/add-ons/accelerants/matrox/engine/mga_dac.c

330

switch (si->ps.card_type) {

src/add-ons/accelerants/matrox/engine/mga_dac.c

358

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_dac.c

362

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/engine/mga_dac.c

365

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/engine/mga_dac.c

368

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

372

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

378

if (req_pclk < (si->ps.min_pixel_vco / 8.0))

src/add-ons/accelerants/matrox/engine/mga_dac.c

381

req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));

src/add-ons/accelerants/matrox/engine/mga_dac.c

382

req_pclk = (si->ps.min_pixel_vco / 8.0);

src/add-ons/accelerants/matrox/engine/mga_dac.c

399

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/matrox/engine/mga_dac.c

405

m = (int)(((f_vco * n) / (8 * si->ps.f_ref)) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_dac.c

410

error = fabs(req_pclk - ((((8 * si->ps.f_ref) / n) * m) / p));

src/add-ons/accelerants/matrox/engine/mga_dac.c

428

f_vco = (((8 * si->ps.f_ref) / n) * m);

src/add-ons/accelerants/matrox/engine/mga_dac.c

474

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_dac.c

505

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_dac.c

509

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/engine/mga_dac.c

512

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/engine/mga_dac.c

515

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

519

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

524

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/matrox/engine/mga_dac.c

528

if (req_pclk < (si->ps.min_pixel_vco / 8.0))

src/add-ons/accelerants/matrox/engine/mga_dac.c

531

req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));

src/add-ons/accelerants/matrox/engine/mga_dac.c

532

req_pclk = (si->ps.min_pixel_vco / 8.0);

src/add-ons/accelerants/matrox/engine/mga_dac.c

549

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/matrox/engine/mga_dac.c

555

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_dac.c

560

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_dac.c

581

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/matrox/engine/mga_dac.c

584

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_dac.c

639

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_dac.c

643

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/engine/mga_dac.c

646

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/engine/mga_dac.c

649

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

653

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_dac.c

658

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/matrox/engine/mga_dac.c

662

if (req_pclk < (si->ps.min_pixel_vco / 16.0))

src/add-ons/accelerants/matrox/engine/mga_dac.c

665

req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));

src/add-ons/accelerants/matrox/engine/mga_dac.c

666

req_pclk = (si->ps.min_pixel_vco / 16.0);

src/add-ons/accelerants/matrox/engine/mga_dac.c

683

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/matrox/engine/mga_dac.c

689

n = (int)(((f_vco * m) / (si->ps.f_ref * 2)) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_dac.c

695

error = fabs(req_pclk - ((((si->ps.f_ref * 2)/ m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_dac.c

732

f_vco = ((si->ps.f_ref * 2) / (m + 1)) * (n + 2);

src/add-ons/accelerants/matrox/engine/mga_dac.c

768

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_dac.c

786

if (req_sclk < (si->ps.min_system_vco / 8.0))

src/add-ons/accelerants/matrox/engine/mga_dac.c

789

req_sclk, (float)(si->ps.min_system_vco / 8.0)));

src/add-ons/accelerants/matrox/engine/mga_dac.c

790

req_sclk = (si->ps.min_system_vco / 8.0);

src/add-ons/accelerants/matrox/engine/mga_dac.c

793

if (req_sclk > si->ps.max_system_vco)

src/add-ons/accelerants/matrox/engine/mga_dac.c

796

req_sclk, (float)si->ps.max_system_vco));

src/add-ons/accelerants/matrox/engine/mga_dac.c

797

req_sclk = si->ps.max_system_vco;

src/add-ons/accelerants/matrox/engine/mga_dac.c

807

if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))

src/add-ons/accelerants/matrox/engine/mga_dac.c

813

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_dac.c

818

error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_dac.c

839

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/matrox/engine/mga_dac.c

842

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_dac.c

88

if (si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/engine/mga_dac.c

980

if (req_sclk < (si->ps.min_system_vco / 16.0))

src/add-ons/accelerants/matrox/engine/mga_dac.c

983

req_sclk, (float)(si->ps.min_system_vco / 16.0)));

src/add-ons/accelerants/matrox/engine/mga_dac.c

984

req_sclk = (si->ps.min_system_vco / 16.0);

src/add-ons/accelerants/matrox/engine/mga_dac.c

987

if (req_sclk > si->ps.max_system_vco)

src/add-ons/accelerants/matrox/engine/mga_dac.c

990

req_sclk, (float)si->ps.max_system_vco));

src/add-ons/accelerants/matrox/engine/mga_dac.c

991

req_sclk = si->ps.max_system_vco;

src/add-ons/accelerants/matrox/engine/mga_general.c

1003

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_general.c

1056

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_general.c

106

si->ps.card_type = G450;

src/add-ons/accelerants/matrox/engine/mga_general.c

107

sprintf(si->adi.name, "Matrox MGA G450");

src/add-ons/accelerants/matrox/engine/mga_general.c

108

sprintf(si->adi.chipset, "G450 revision %x", (card_class & 0x7f));

src/add-ons/accelerants/matrox/engine/mga_general.c

116

si->ps.card_type = G400;

src/add-ons/accelerants/matrox/engine/mga_general.c

117

sprintf(si->adi.name, "Matrox MGA G400");

src/add-ons/accelerants/matrox/engine/mga_general.c

118

sprintf(si->adi.chipset, "G400 revision %x", (card_class & 0x7f));

src/add-ons/accelerants/matrox/engine/mga_general.c

123

si->ps.card_type = G450;

src/add-ons/accelerants/matrox/engine/mga_general.c

124

sprintf(si->adi.name, "Matrox MGA G550");

src/add-ons/accelerants/matrox/engine/mga_general.c

125

sprintf(si->adi.chipset, "G550");

src/add-ons/accelerants/matrox/engine/mga_general.c

134

if (si->settings.memory != 0)

src/add-ons/accelerants/matrox/engine/mga_general.c

135

si->ps.memory_size = si->settings.memory;

src/add-ons/accelerants/matrox/engine/mga_general.c

146

if (si->fbc.frame_buffer == NULL)

src/add-ons/accelerants/matrox/engine/mga_general.c

155

((vuint32 *)si->fbc.frame_buffer)[offset] = value;

src/add-ons/accelerants/matrox/engine/mga_general.c

163

if (((vuint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;

src/add-ons/accelerants/matrox/engine/mga_general.c

187

if (si->ps.pins_status != B_OK)

src/add-ons/accelerants/matrox/engine/mga_general.c

196

switch(si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_general.c

199

if (!si->ps.sdram)

src/add-ons/accelerants/matrox/engine/mga_general.c

208

ACCW(MCTLWTST, ((si->ps.mctlwtst_reg & 0xfffffffc) | (latency - 2)));

src/add-ons/accelerants/matrox/engine/mga_general.c

21

#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \

src/add-ons/accelerants/matrox/engine/mga_general.c

250

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/matrox/engine/mga_general.c

251

if (si->settings.logmask & 0x80000000) mga_dump_configuration_space();

src/add-ons/accelerants/matrox/engine/mga_general.c

297

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/matrox/engine/mga_general.c

298

if (si->settings.logmask & 0x80000000) mga_dump_configuration_space();

src/add-ons/accelerants/matrox/engine/mga_general.c

308

if (si->settings.usebios || (result != B_OK)) return gx00_general_bios_to_powergraphics();

src/add-ons/accelerants/matrox/engine/mga_general.c

315

if (si->ps.tvout) gx00_maven_dpms(false, false, false);

src/add-ons/accelerants/matrox/engine/mga_general.c

355

ACCW(MCTLWTST,si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

360

CFGW(OPTION,(CFGR(OPTION)&0xFFFF8FFF) | ((si->ps.v3_mem_type & 0x04) << 10));

src/add-ons/accelerants/matrox/engine/mga_general.c

365

CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_mem_type & 0x01) << 12));

src/add-ons/accelerants/matrox/engine/mga_general.c

367

CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFFFF0) | ((si->ps.v3_mem_type & 0xf0) >> 4));

src/add-ons/accelerants/matrox/engine/mga_general.c

379

CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));

src/add-ons/accelerants/matrox/engine/mga_general.c

381

ACCW(MCTLWTST,si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

399

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/matrox/engine/mga_general.c

400

if (si->settings.logmask & 0x80000000) mga_dump_configuration_space();

src/add-ons/accelerants/matrox/engine/mga_general.c

410

if (si->settings.usebios || (result != B_OK)) return gx00_general_bios_to_powergraphics();

src/add-ons/accelerants/matrox/engine/mga_general.c

417

if (si->ps.tvout) gx00_maven_dpms(false, false, false);

src/add-ons/accelerants/matrox/engine/mga_general.c

454

if (si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) & 0xffffbfff));

src/add-ons/accelerants/matrox/engine/mga_general.c

459

ACCW(MCTLWTST,si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

462

CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | ((si->ps.v3_mem_type & 0x07) << 10));

src/add-ons/accelerants/matrox/engine/mga_general.c

463

if (!si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) | (0x01 << 14)));

src/add-ons/accelerants/matrox/engine/mga_general.c

465

CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_option2_reg & 0x03) << 12));

src/add-ons/accelerants/matrox/engine/mga_general.c

467

ACCW(MEMRDBK,(ACCR(MEMRDBK)&0x0000FFFF)|(si->ps.memrdbk_reg & 0xffff0000));

src/add-ons/accelerants/matrox/engine/mga_general.c

469

ACCW(MEMRDBK,(ACCR(MEMRDBK)&0xFFFF0000)|(si->ps.memrdbk_reg & 0x0000ffff));

src/add-ons/accelerants/matrox/engine/mga_general.c

479

CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));

src/add-ons/accelerants/matrox/engine/mga_general.c

481

ACCW(MCTLWTST,si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

499

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/matrox/engine/mga_general.c

500

if (si->settings.logmask & 0x80000000) mga_dump_configuration_space();

src/add-ons/accelerants/matrox/engine/mga_general.c

510

if (si->settings.usebios || (result != B_OK)) return gx00_general_bios_to_powergraphics();

src/add-ons/accelerants/matrox/engine/mga_general.c

513

if (si->ps.tvout)

src/add-ons/accelerants/matrox/engine/mga_general.c

562

if (si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) & 0xffffbfff));

src/add-ons/accelerants/matrox/engine/mga_general.c

567

ACCW(MCTLWTST, si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

570

CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | (si->ps.option_reg & 0x00001c00));

src/add-ons/accelerants/matrox/engine/mga_general.c

571

if (!si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) | (0x01 << 14)));

src/add-ons/accelerants/matrox/engine/mga_general.c

573

ACCW(MEMRDBK,(ACCR(MEMRDBK)&0x0000FFFF)|(si->ps.memrdbk_reg & 0xffff0000));

src/add-ons/accelerants/matrox/engine/mga_general.c

575

ACCW(MEMRDBK,(ACCR(MEMRDBK)&0xFFFF0000)|(si->ps.memrdbk_reg & 0x0000ffff));

src/add-ons/accelerants/matrox/engine/mga_general.c

585

CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));

src/add-ons/accelerants/matrox/engine/mga_general.c

587

ACCW(MCTLWTST,si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

591

CFGW(OPTION, ((CFGR(OPTION) & 0xefbfffff) | (si->ps.option_reg & 0x10400000)));

src/add-ons/accelerants/matrox/engine/mga_general.c

595

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/engine/mga_general.c

60

if (si->ps.int_assigned)

src/add-ons/accelerants/matrox/engine/mga_general.c

614

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/matrox/engine/mga_general.c

615

if (si->settings.logmask & 0x80000000) mga_dump_configuration_space();

src/add-ons/accelerants/matrox/engine/mga_general.c

625

if (si->ps.primary_dvi && si->ps.secondary_head &&

src/add-ons/accelerants/matrox/engine/mga_general.c

626

si->ps.tvout && (i2c_sec_tv_adapter() != B_OK))

src/add-ons/accelerants/matrox/engine/mga_general.c

629

si->crossed_conns = true;

src/add-ons/accelerants/matrox/engine/mga_general.c

633

if (si->settings.usebios || (result != B_OK)) return gx00_general_bios_to_powergraphics();

src/add-ons/accelerants/matrox/engine/mga_general.c

684

CFGW(OPTION, ((CFGR(OPTION) & 0xf8400164) | (si->ps.option_reg & 0x00207e00)));

src/add-ons/accelerants/matrox/engine/mga_general.c

686

CFGW(OPTION2, ((CFGR(OPTION2) & 0xffff0200) | (si->ps.option2_reg & 0x0000fc00)));

src/add-ons/accelerants/matrox/engine/mga_general.c

689

ACCW(MCTLWTST, si->ps.mctlwtst_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

691

CFGW(OPTION4, (si->ps.option4_reg & 0x6000000f));

src/add-ons/accelerants/matrox/engine/mga_general.c

693

ACCW(MEMRDBK, si->ps.memrdbk_reg);

src/add-ons/accelerants/matrox/engine/mga_general.c

695

maccess = ((((uint32)si->ps.v5_mem_type) & 0x80) >> 1);

src/add-ons/accelerants/matrox/engine/mga_general.c

698

CFGW(OPTION4, ((si->ps.option4_reg & 0x60000004) | 0x80000000));

src/add-ons/accelerants/matrox/engine/mga_general.c

702

if ((si->ps.v5_mem_type & 0x0060) == 0x0020)

src/add-ons/accelerants/matrox/engine/mga_general.c

705

if (!(si->ps.v5_mem_type & 0x0100))

src/add-ons/accelerants/matrox/engine/mga_general.c

711

ACCW(MEMRDBK, (si->ps.memrdbk_reg & 0xffffefff));

src/add-ons/accelerants/matrox/engine/mga_general.c

715

if (!(si->ps.v5_mem_type & 0x0200))

src/add-ons/accelerants/matrox/engine/mga_general.c

718

ACCW(MEMRDBK, (si->ps.memrdbk_reg & 0xffffefff));

src/add-ons/accelerants/matrox/engine/mga_general.c

72

sprintf(si->adi.name, "Matrox Mystique PCI");

src/add-ons/accelerants/matrox/engine/mga_general.c

724

if (si->ps.card_type == G450) {

src/add-ons/accelerants/matrox/engine/mga_general.c

73

sprintf(si->adi.chipset, "MGA-1064");

src/add-ons/accelerants/matrox/engine/mga_general.c

734

CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));

src/add-ons/accelerants/matrox/engine/mga_general.c

741

if (!(si->ps.v5_mem_type & 0x0400))

src/add-ons/accelerants/matrox/engine/mga_general.c

745

((si->ps.mctlwtst_reg & 0xfffffff8) | pwr_cas[(si->ps.mctlwtst_reg & 0x07)]));

src/add-ons/accelerants/matrox/engine/mga_general.c

752

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/engine/mga_general.c

77

si->ps.card_type = MIL1;

src/add-ons/accelerants/matrox/engine/mga_general.c

771

if ((si->ps.card_type != G450) && (si->ps.card_type != G550)) return B_ERROR;

src/add-ons/accelerants/matrox/engine/mga_general.c

774

if (si->ps.primary_dvi && si->ps.secondary_head && si->ps.tvout)

src/add-ons/accelerants/matrox/engine/mga_general.c

78

sprintf(si->adi.name, "Matrox Millennium I");

src/add-ons/accelerants/matrox/engine/mga_general.c

781

si->crossed_conns = false;

src/add-ons/accelerants/matrox/engine/mga_general.c

788

si->crossed_conns = true;

src/add-ons/accelerants/matrox/engine/mga_general.c

79

sprintf(si->adi.chipset, "MGA-2064");

src/add-ons/accelerants/matrox/engine/mga_general.c

796

si->crossed_conns = false;

src/add-ons/accelerants/matrox/engine/mga_general.c

815

if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0xffe00779)|0xD0000002);

src/add-ons/accelerants/matrox/engine/mga_general.c

827

if (si->ps.secondary_head) CR2W(CTL,(CR2R(CTL)&0x2fe00779)|0x4|(0x1<<20));

src/add-ons/accelerants/matrox/engine/mga_general.c

83

si->ps.card_type = MIL2;

src/add-ons/accelerants/matrox/engine/mga_general.c

836

if (si->ps.card_type < G450) return B_ERROR;

src/add-ons/accelerants/matrox/engine/mga_general.c

84

sprintf(si->adi.name, "Matrox Millennium II");

src/add-ons/accelerants/matrox/engine/mga_general.c

85

sprintf(si->adi.chipset, "MGA-2164");

src/add-ons/accelerants/matrox/engine/mga_general.c

852

si->crossed_conns = false;

src/add-ons/accelerants/matrox/engine/mga_general.c

857

if (si->ps.card_type < G450) return B_ERROR;

src/add-ons/accelerants/matrox/engine/mga_general.c

870

si->crossed_conns = true;

src/add-ons/accelerants/matrox/engine/mga_general.c

89

si->ps.card_type = G100;

src/add-ons/accelerants/matrox/engine/mga_general.c

897

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_general.c

90

sprintf(si->adi.name, "Matrox MGA G100");

src/add-ons/accelerants/matrox/engine/mga_general.c

902

if (si->ps.tvout)

src/add-ons/accelerants/matrox/engine/mga_general.c

91

sprintf(si->adi.chipset, "G100");

src/add-ons/accelerants/matrox/engine/mga_general.c

923

if (si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/engine/mga_general.c

95

si->ps.card_type = G200;

src/add-ons/accelerants/matrox/engine/mga_general.c

96

sprintf(si->adi.name, "Matrox MGA G200");

src/add-ons/accelerants/matrox/engine/mga_general.c

963

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_general.c

97

sprintf(si->adi.chipset, "G200");

src/add-ons/accelerants/matrox/engine/mga_globals.c

12

shared_info *si;

src/add-ons/accelerants/matrox/engine/mga_globals.h

2

extern shared_info *si;

src/add-ons/accelerants/matrox/engine/mga_i2c.c

44

if (!si->ps.secondary_head) return result;

src/add-ons/accelerants/matrox/engine/mga_info.c

107

si->ps.pins_status = B_OK;

src/add-ons/accelerants/matrox/engine/mga_info.c

122

si->ps.f_ref = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

124

si->ps.max_system_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

125

si->ps.min_system_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

126

si->ps.min_pixel_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

127

si->ps.min_video_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

128

si->ps.std_engine_clock_dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

129

si->ps.max_dac1_clock_32 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

130

si->ps.max_dac1_clock_32dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

131

si->ps.memory_size = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

132

si->ps.mctlwtst_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

133

si->ps.memrdbk_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

134

si->ps.option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

135

si->ps.option3_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

136

si->ps.option4_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

138

si->ps.v3_option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

139

si->ps.v3_clk_div = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

140

si->ps.v3_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

142

si->ps.v5_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

144

si->ps.secondary_head = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

145

si->ps.tvout = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

146

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

147

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

148

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

151

si->ps.max_dac1_clock_32 = pins[22];//ramdac

src/add-ons/accelerants/matrox/engine/mga_info.c

152

si->ps.max_pixel_vco = (pins[25] << 8) | pins[24];//PCLK

src/add-ons/accelerants/matrox/engine/mga_info.c

153

si->ps.std_engine_clock = (pins[29] << 8) | pins[28];

src/add-ons/accelerants/matrox/engine/mga_info.c

154

if ((uint32)((pins[31] << 8) | pins[30]) < si->ps.std_engine_clock)

src/add-ons/accelerants/matrox/engine/mga_info.c

155

si->ps.std_engine_clock = (pins[31] << 8) | pins[30];

src/add-ons/accelerants/matrox/engine/mga_info.c

156

if ((uint32)((pins[33] << 8) | pins[32]) < si->ps.std_engine_clock)

src/add-ons/accelerants/matrox/engine/mga_info.c

157

si->ps.std_engine_clock = (pins[33] << 8) | pins[32];

src/add-ons/accelerants/matrox/engine/mga_info.c

160

si->ps.max_video_vco = (pins[27] << 8) | pins[26];//LCLK

src/add-ons/accelerants/matrox/engine/mga_info.c

162

si->ps.option_reg = (pins[53] << 24) | (pins[52] << 16) | (pins[51] << 8) | pins [50];

src/add-ons/accelerants/matrox/engine/mga_info.c

164

si->ps.max_dac2_clock = (pins[35] << 8) | pins[34];//clkmod

src/add-ons/accelerants/matrox/engine/mga_info.c

165

si->ps.max_dac2_clock_8 = (pins[37] << 8) | pins[36];//testclk

src/add-ons/accelerants/matrox/engine/mga_info.c

166

si->ps.max_dac2_clock_16 = (pins[39] << 8) | pins[38];//vgafreq1

src/add-ons/accelerants/matrox/engine/mga_info.c

167

si->ps.max_dac2_clock_24 = (pins[41] << 8) | pins[40];//vgafreq2

src/add-ons/accelerants/matrox/engine/mga_info.c

168

si->ps.max_dac2_clock_32 = (pins[55] << 8) | pins[54];//vga clock

src/add-ons/accelerants/matrox/engine/mga_info.c

169

si->ps.max_dac2_clock_32dh = pins[58];//vid ctrl

src/add-ons/accelerants/matrox/engine/mga_info.c

171

si->ps.max_dac1_clock = (pins[29] << 8) | pins[28];//clkbase

src/add-ons/accelerants/matrox/engine/mga_info.c

172

si->ps.max_dac1_clock_8 = (pins[31] << 8) | pins[30];//4mb

src/add-ons/accelerants/matrox/engine/mga_info.c

173

si->ps.max_dac1_clock_16 = (pins[33] << 8) | pins[32];//8mb

src/add-ons/accelerants/matrox/engine/mga_info.c

174

si->ps.max_dac1_clock_24 = pins[23];//ramdac type

src/add-ons/accelerants/matrox/engine/mga_info.c

206

si->ps.max_pixel_vco = pins[36] + 100;

src/add-ons/accelerants/matrox/engine/mga_info.c

208

si->ps.max_dac1_clock_8 = pins[37] + 100;

src/add-ons/accelerants/matrox/engine/mga_info.c

209

si->ps.max_dac1_clock_16 = pins[38] + 100;

src/add-ons/accelerants/matrox/engine/mga_info.c

210

si->ps.max_dac1_clock_24 = pins[39] + 100;

src/add-ons/accelerants/matrox/engine/mga_info.c

211

si->ps.max_dac1_clock_32 = pins[40] + 100;

src/add-ons/accelerants/matrox/engine/mga_info.c

213

si->ps.std_engine_clock = pins[44];

src/add-ons/accelerants/matrox/engine/mga_info.c

214

if (pins [45] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[45];

src/add-ons/accelerants/matrox/engine/mga_info.c

215

if (pins [46] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[46];

src/add-ons/accelerants/matrox/engine/mga_info.c

216

if (pins [47] < si->ps.std_engine_clock) si->ps.std_engine_clock = pins[47];

src/add-ons/accelerants/matrox/engine/mga_info.c

217

if ((si->ps.card_type == G200) && (pins[58] & 0x04))

src/add-ons/accelerants/matrox/engine/mga_info.c

220

si->ps.std_engine_clock *= 1;

src/add-ons/accelerants/matrox/engine/mga_info.c

225

si->ps.std_engine_clock *= 3;

src/add-ons/accelerants/matrox/engine/mga_info.c

227

si->ps.std_engine_clock *= 2;

src/add-ons/accelerants/matrox/engine/mga_info.c

23

si->ps.pins_status = B_ERROR;

src/add-ons/accelerants/matrox/engine/mga_info.c

230

if (pins[52] & 0x20) si->ps.f_ref = 14.31818;

src/add-ons/accelerants/matrox/engine/mga_info.c

231

else si->ps.f_ref = 27.00000;

src/add-ons/accelerants/matrox/engine/mga_info.c

234

si->ps.memory_size = 2 << ((pins[55] & 0xc0) >> 6);

src/add-ons/accelerants/matrox/engine/mga_info.c

236

si->ps.mctlwtst_reg = (pins[51] << 24) | (pins[50] << 16) | (pins[49] << 8) | pins [48];

src/add-ons/accelerants/matrox/engine/mga_info.c

237

si->ps.memrdbk_reg =

src/add-ons/accelerants/matrox/engine/mga_info.c

242

si->ps.v3_clk_div = pins[52];

src/add-ons/accelerants/matrox/engine/mga_info.c

243

si->ps.v3_mem_type = pins[54];

src/add-ons/accelerants/matrox/engine/mga_info.c

244

si->ps.v3_option2_reg = pins[58];

src/add-ons/accelerants/matrox/engine/mga_info.c

247

si->ps.tvout = !(pins[59] & 0x01);

src/add-ons/accelerants/matrox/engine/mga_info.c

251

si->ps.tvout = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

255

si->ps.secondary_head = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

256

if (si->ps.card_type >= G400) si->ps.secondary_head = !(pins[59] & 0x01);

src/add-ons/accelerants/matrox/engine/mga_info.c

259

si->ps.option_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

262

if ((si->ps.card_type == G200) && (pins[58] & 0x08))

src/add-ons/accelerants/matrox/engine/mga_info.c

265

mclk_period = 1000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

27

rom = (uint8 *) si->rom_mirror;

src/add-ons/accelerants/matrox/engine/mga_info.c

271

mclk_period = 3000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

273

mclk_period = 2000.0 / si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

280

si->ps.option_reg |= (rfhcnt << 15);

src/add-ons/accelerants/matrox/engine/mga_info.c

284

si->ps.primary_dvi = !(pins[59] & 0x40);

src/add-ons/accelerants/matrox/engine/mga_info.c

286

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

289

si->ps.max_system_vco = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

290

si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_info.c

291

si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_info.c

292

si->ps.std_engine_clock_dh = si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

293

si->ps.sdram = (si->ps.v3_clk_div & 0x10);

src/add-ons/accelerants/matrox/engine/mga_info.c

295

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

296

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

298

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

299

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

301

si->ps.max_video_vco = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

302

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

304

si->ps.max_dac2_clock = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

305

si->ps.max_dac2_clock_16 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

306

si->ps.max_dac2_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

307

si->ps.max_dac2_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

310

si->ps.option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

311

si->ps.option3_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

312

si->ps.option4_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

313

si->ps.v5_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

331

if (pins[39] == 0xff) si->ps.max_pixel_vco = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

332

else si->ps.max_pixel_vco = 4 * pins[39];

src/add-ons/accelerants/matrox/engine/mga_info.c

334

if (pins[38] == 0xff) si->ps.max_system_vco = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

335

else si->ps.max_system_vco = 4 * pins[38];

src/add-ons/accelerants/matrox/engine/mga_info.c

337

if (pins[40] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

338

else si->ps.max_dac1_clock_8 = 4 * pins[40];

src/add-ons/accelerants/matrox/engine/mga_info.c

340

if (pins[41] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_info.c

341

else si->ps.max_dac1_clock_16 = 4 * pins[41];

src/add-ons/accelerants/matrox/engine/mga_info.c

343

if (pins[42] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/engine/mga_info.c

344

else si->ps.max_dac1_clock_24 = 4 * pins[42];

src/add-ons/accelerants/matrox/engine/mga_info.c

346

if (pins[43] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/engine/mga_info.c

347

else si->ps.max_dac1_clock_32 = 4 * pins[43];

src/add-ons/accelerants/matrox/engine/mga_info.c

349

if (pins[44] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

350

else si->ps.max_dac2_clock_16 = 4 * pins[44];

src/add-ons/accelerants/matrox/engine/mga_info.c

352

if (pins[45] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/engine/mga_info.c

353

else si->ps.max_dac2_clock_32 = 4 * pins[45];

src/add-ons/accelerants/matrox/engine/mga_info.c

356

si->ps.std_engine_clock = 2 * pins[65];

src/add-ons/accelerants/matrox/engine/mga_info.c

358

if (pins[92] & 0x01) si->ps.f_ref = 14.31818;

src/add-ons/accelerants/matrox/engine/mga_info.c

359

else si->ps.f_ref = 27.00000;

src/add-ons/accelerants/matrox/engine/mga_info.c

361

si->ps.memory_size = 4 << ((pins[92] >> 2) & 0x03);

src/add-ons/accelerants/matrox/engine/mga_info.c

363

si->ps.mctlwtst_reg = (pins[74] << 24) | (pins[73] << 16) | (pins[72] << 8) | pins [71];

src/add-ons/accelerants/matrox/engine/mga_info.c

364

si->ps.option3_reg = (pins[70] << 24) | (pins[69] << 16) | (pins[68] << 8) | pins [67];

src/add-ons/accelerants/matrox/engine/mga_info.c

366

si->ps.memrdbk_reg =

src/add-ons/accelerants/matrox/engine/mga_info.c

368

si->ps.sdram = (pins[92] & 0x10);

src/add-ons/accelerants/matrox/engine/mga_info.c

371

si->ps.option_reg = ((pins[53] & 0x38) << 7) | ((pins[53] & 0x40) << 22) | ((pins[53] & 0x80) << 15);

src/add-ons/accelerants/matrox/engine/mga_info.c

375

switch ((si->ps.option3_reg & 0x0000e000) >> 13)

src/add-ons/accelerants/matrox/engine/mga_info.c

378

mclk_period = 3000.0 / (si->ps.std_engine_clock * 1);

src/add-ons/accelerants/matrox/engine/mga_info.c

381

mclk_period = 5000.0 / (si->ps.std_engine_clock * 2);

src/add-ons/accelerants/matrox/engine/mga_info.c

384

mclk_period = 9000.0 / (si->ps.std_engine_clock * 4);

src/add-ons/accelerants/matrox/engine/mga_info.c

387

mclk_period = 2000.0 / (si->ps.std_engine_clock * 1);

src/add-ons/accelerants/matrox/engine/mga_info.c

390

mclk_period = 3000.0 / (si->ps.std_engine_clock * 2);

src/add-ons/accelerants/matrox/engine/mga_info.c

393

mclk_period = 1000.0 / (si->ps.std_engine_clock * 1);

src/add-ons/accelerants/matrox/engine/mga_info.c

397

mclk_period = 3000.0 / (si->ps.std_engine_clock * 1);

src/add-ons/accelerants/matrox/engine/mga_info.c

406

si->ps.option_reg |= (rfhcnt << 15);

src/add-ons/accelerants/matrox/engine/mga_info.c

409

si->ps.tvout = !(pins[91] & 0x01);

src/add-ons/accelerants/matrox/engine/mga_info.c

413

si->ps.tvout = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

417

si->ps.secondary_head = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

418

if (si->ps.card_type >= G400) si->ps.secondary_head = !(pins[91] & 0x01);

src/add-ons/accelerants/matrox/engine/mga_info.c

421

si->ps.primary_dvi = !(pins[91] & 0x40);

src/add-ons/accelerants/matrox/engine/mga_info.c

423

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

426

si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_info.c

427

si->ps.max_dac2_clock = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/engine/mga_info.c

428

si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_info.c

429

si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_info.c

430

si->ps.std_engine_clock_dh = si->ps.std_engine_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

432

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

433

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

435

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

436

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

438

si->ps.max_video_vco = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

439

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

442

si->ps.option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

443

si->ps.option4_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

444

si->ps.v3_option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

445

si->ps.v3_clk_div = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

446

si->ps.v3_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

447

si->ps.v5_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

451

if (si->ps.max_dac1_clock > 300)

src/add-ons/accelerants/matrox/engine/mga_info.c

453

si->ps.card_type = G400MAX;

src/add-ons/accelerants/matrox/engine/mga_info.c

474

si->ps.max_system_vco = m_factor * pins[36];

src/add-ons/accelerants/matrox/engine/mga_info.c

475

si->ps.max_video_vco = m_factor * pins[37];

src/add-ons/accelerants/matrox/engine/mga_info.c

476

si->ps.max_pixel_vco = m_factor * pins[38];

src/add-ons/accelerants/matrox/engine/mga_info.c

477

si->ps.min_system_vco = m_factor * pins[121];

src/add-ons/accelerants/matrox/engine/mga_info.c

478

si->ps.min_video_vco = m_factor * pins[122];

src/add-ons/accelerants/matrox/engine/mga_info.c

479

si->ps.min_pixel_vco = m_factor * pins[123];

src/add-ons/accelerants/matrox/engine/mga_info.c

481

if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

482

else si->ps.max_dac1_clock_8 = 4 * pins[39];

src/add-ons/accelerants/matrox/engine/mga_info.c

484

if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_info.c

485

else si->ps.max_dac1_clock_16 = 4 * pins[40];

src/add-ons/accelerants/matrox/engine/mga_info.c

487

if (pins[41] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/matrox/engine/mga_info.c

488

else si->ps.max_dac1_clock_24 = 4 * pins[41];

src/add-ons/accelerants/matrox/engine/mga_info.c

490

if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/matrox/engine/mga_info.c

491

else si->ps.max_dac1_clock_32 = 4 * pins[42];

src/add-ons/accelerants/matrox/engine/mga_info.c

493

if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/matrox/engine/mga_info.c

494

else si->ps.max_dac1_clock_32dh = 4 * pins[124];

src/add-ons/accelerants/matrox/engine/mga_info.c

496

if (pins[43] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_video_vco;

src/add-ons/accelerants/matrox/engine/mga_info.c

497

else si->ps.max_dac2_clock_16 = 4 * pins[43];

src/add-ons/accelerants/matrox/engine/mga_info.c

499

if (pins[44] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/engine/mga_info.c

500

else si->ps.max_dac2_clock_32 = 4 * pins[44];

src/add-ons/accelerants/matrox/engine/mga_info.c

502

if (pins[125] == 0xff) si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_info.c

503

else si->ps.max_dac2_clock_32dh = 4 * pins[125];

src/add-ons/accelerants/matrox/engine/mga_info.c

505

if (pins[118] == 0xff) si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/matrox/engine/mga_info.c

506

else si->ps.max_dac1_clock = 4 * pins[118];

src/add-ons/accelerants/matrox/engine/mga_info.c

508

if (pins[119] == 0xff) si->ps.max_dac2_clock = si->ps.max_dac1_clock;

src/add-ons/accelerants/matrox/engine/mga_info.c

509

else si->ps.max_dac2_clock = 4 * pins[119];

src/add-ons/accelerants/matrox/engine/mga_info.c

511

si->ps.std_engine_clock = 4 * pins[74];

src/add-ons/accelerants/matrox/engine/mga_info.c

512

si->ps.std_engine_clock_dh = 4 * pins[92];

src/add-ons/accelerants/matrox/engine/mga_info.c

514

si->ps.memory_size = ((pins[114] & 0x03) + 1) * 8;

src/add-ons/accelerants/matrox/engine/mga_info.c

518

si->ps.memory_size = 8;

src/add-ons/accelerants/matrox/engine/mga_info.c

521

if (pins[110] & 0x01) si->ps.f_ref = 14.31818;

src/add-ons/accelerants/matrox/engine/mga_info.c

522

else si->ps.f_ref = 27.00000;

src/add-ons/accelerants/matrox/engine/mga_info.c

525

if ((pins[114] & 0x18) == 0x08) si->ps.sdram = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

526

else si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

528

si->ps.v5_mem_type = (pins[115] << 8) | pins [114];

src/add-ons/accelerants/matrox/engine/mga_info.c

531

si->ps.option_reg = (pins[51] << 24) | (pins[50] << 16) | (pins[49] << 8) | pins [48];

src/add-ons/accelerants/matrox/engine/mga_info.c

532

si->ps.option2_reg = (pins[55] << 24) | (pins[54] << 16) | (pins[53] << 8) | pins [52];

src/add-ons/accelerants/matrox/engine/mga_info.c

533

si->ps.option3_reg = (pins[79] << 24) | (pins[78] << 16) | (pins[77] << 8) | pins [76];

src/add-ons/accelerants/matrox/engine/mga_info.c

534

si->ps.option4_reg = (pins[87] << 24) | (pins[86] << 16) | (pins[85] << 8) | pins [84];

src/add-ons/accelerants/matrox/engine/mga_info.c

535

si->ps.mctlwtst_reg = (pins[83] << 24) | (pins[82] << 16) | (pins[81] << 8) | pins [80];

src/add-ons/accelerants/matrox/engine/mga_info.c

536

si->ps.memrdbk_reg = (pins[91] << 24) | (pins[90] << 16) | (pins[89] << 8) | pins [88];

src/add-ons/accelerants/matrox/engine/mga_info.c

539

si->ps.secondary_head = (pins[117] & 0x70);

src/add-ons/accelerants/matrox/engine/mga_info.c

540

si->ps.tvout = (pins[117] & 0x40);

src/add-ons/accelerants/matrox/engine/mga_info.c

542

si->ps.primary_dvi = (pins[117] & 0x02);

src/add-ons/accelerants/matrox/engine/mga_info.c

543

si->ps.secondary_dvi = (pins[117] & 0x20);

src/add-ons/accelerants/matrox/engine/mga_info.c

546

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

547

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

550

si->ps.v3_option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

551

si->ps.v3_clk_div = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

552

si->ps.v3_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

561

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_info.c

590

si->ps.tvout = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

591

si->ps.secondary_head = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

593

if (si->ps.card_type >= G100)

src/add-ons/accelerants/matrox/engine/mga_info.c

597

si->ps.tvout = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

599

if (si->ps.card_type >= G400) si->ps.secondary_head = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

604

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

605

si->ps.std_engine_clock_dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

606

si->ps.mctlwtst_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

607

si->ps.memrdbk_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

608

si->ps.option_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

609

si->ps.option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

610

si->ps.option3_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

611

si->ps.option4_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

612

si->ps.v3_option2_reg = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

613

si->ps.v3_clk_div = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

614

si->ps.v3_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

615

si->ps.v5_mem_type = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

622

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/matrox/engine/mga_info.c

624

si->ps.max_system_vco = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

625

si->ps.min_system_vco = 110;

src/add-ons/accelerants/matrox/engine/mga_info.c

626

si->ps.max_pixel_vco = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

627

si->ps.min_pixel_vco = 110;

src/add-ons/accelerants/matrox/engine/mga_info.c

629

si->ps.max_video_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

630

si->ps.min_video_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

632

si->ps.max_dac1_clock = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

633

si->ps.max_dac1_clock_8 = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

634

si->ps.max_dac1_clock_16 = 200;

src/add-ons/accelerants/matrox/engine/mga_info.c

636

si->ps.max_dac1_clock_24 = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

637

si->ps.max_dac1_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

638

si->ps.max_dac1_clock_32dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

640

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

641

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

642

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

643

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

644

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

646

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

647

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

648

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

651

si->ps.memory_size = 2;

src/add-ons/accelerants/matrox/engine/mga_info.c

654

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

661

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/matrox/engine/mga_info.c

663

si->ps.max_system_vco = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

664

si->ps.min_system_vco = 110;

src/add-ons/accelerants/matrox/engine/mga_info.c

665

si->ps.max_pixel_vco = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

666

si->ps.min_pixel_vco = 110;

src/add-ons/accelerants/matrox/engine/mga_info.c

668

si->ps.max_video_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

669

si->ps.min_video_vco = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

671

si->ps.max_dac1_clock = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

672

si->ps.max_dac1_clock_8 = 220;

src/add-ons/accelerants/matrox/engine/mga_info.c

673

si->ps.max_dac1_clock_16 = 200;

src/add-ons/accelerants/matrox/engine/mga_info.c

675

si->ps.max_dac1_clock_24 = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

676

si->ps.max_dac1_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

677

si->ps.max_dac1_clock_32dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

679

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

680

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

681

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

682

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

683

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

685

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

686

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

687

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

690

si->ps.memory_size = 4;

src/add-ons/accelerants/matrox/engine/mga_info.c

693

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

701

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

703

si->ps.max_system_vco = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

704

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

705

si->ps.max_pixel_vco = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

706

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

708

si->ps.max_video_vco = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

709

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

711

si->ps.max_dac1_clock = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

712

si->ps.max_dac1_clock_8 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

713

si->ps.max_dac1_clock_16 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

715

si->ps.max_dac1_clock_24 = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

716

si->ps.max_dac1_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

717

si->ps.max_dac1_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

719

si->ps.max_dac2_clock = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

720

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

721

si->ps.max_dac2_clock_16 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

722

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

723

si->ps.max_dac2_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

725

si->ps.max_dac2_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

728

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

729

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

731

si->ps.memory_size = 2;

src/add-ons/accelerants/matrox/engine/mga_info.c

734

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

742

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

744

si->ps.max_system_vco = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

745

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

746

si->ps.max_pixel_vco = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

747

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

749

si->ps.max_video_vco = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

750

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

752

si->ps.max_dac1_clock = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

753

si->ps.max_dac1_clock_8 = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

754

si->ps.max_dac1_clock_16 = 250;

src/add-ons/accelerants/matrox/engine/mga_info.c

756

si->ps.max_dac1_clock_24 = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

757

si->ps.max_dac1_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

758

si->ps.max_dac1_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

760

si->ps.max_dac2_clock = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

761

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

762

si->ps.max_dac2_clock_16 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

763

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

764

si->ps.max_dac2_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

766

si->ps.max_dac2_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

769

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

770

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

772

si->ps.memory_size = 2;

src/add-ons/accelerants/matrox/engine/mga_info.c

774

si->ps.sdram = !(CFGR(OPTION) & 0x00004000);

src/add-ons/accelerants/matrox/engine/mga_info.c

782

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

784

si->ps.max_system_vco = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

785

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

786

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

787

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

789

si->ps.max_video_vco = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

790

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

792

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

793

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

794

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/matrox/engine/mga_info.c

796

si->ps.max_dac1_clock_24 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

797

si->ps.max_dac1_clock_32 = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

798

si->ps.max_dac1_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

800

si->ps.max_dac2_clock = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

801

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

802

si->ps.max_dac2_clock_16 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

803

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

804

si->ps.max_dac2_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

806

si->ps.max_dac2_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

809

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

810

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

812

si->ps.memory_size = 4;

src/add-ons/accelerants/matrox/engine/mga_info.c

814

si->ps.sdram = !(CFGR(OPTION) & 0x00004000);

src/add-ons/accelerants/matrox/engine/mga_info.c

823

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

825

si->ps.max_system_vco = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

826

si->ps.min_system_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

827

si->ps.max_pixel_vco = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

828

si->ps.min_pixel_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

830

si->ps.max_video_vco = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

831

si->ps.min_video_vco = 50;

src/add-ons/accelerants/matrox/engine/mga_info.c

833

si->ps.max_dac1_clock = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

834

si->ps.max_dac1_clock_8 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

835

si->ps.max_dac1_clock_16 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

837

si->ps.max_dac1_clock_24 = 280;

src/add-ons/accelerants/matrox/engine/mga_info.c

838

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

839

si->ps.max_dac1_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

841

si->ps.max_dac2_clock = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

842

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

843

si->ps.max_dac2_clock_16 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

844

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

845

si->ps.max_dac2_clock_32 = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

847

si->ps.max_dac2_clock_32dh = 136;

src/add-ons/accelerants/matrox/engine/mga_info.c

850

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

851

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

853

si->ps.memory_size = 4;

src/add-ons/accelerants/matrox/engine/mga_info.c

855

si->ps.sdram = !(CFGR(OPTION) & 0x00004000);

src/add-ons/accelerants/matrox/engine/mga_info.c

863

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

866

si->ps.max_system_vco = 640;

src/add-ons/accelerants/matrox/engine/mga_info.c

867

si->ps.min_system_vco = 320;

src/add-ons/accelerants/matrox/engine/mga_info.c

868

si->ps.max_pixel_vco = 640;

src/add-ons/accelerants/matrox/engine/mga_info.c

869

si->ps.min_pixel_vco = 320;

src/add-ons/accelerants/matrox/engine/mga_info.c

870

si->ps.max_video_vco = 640;

src/add-ons/accelerants/matrox/engine/mga_info.c

871

si->ps.min_video_vco = 320;

src/add-ons/accelerants/matrox/engine/mga_info.c

872

si->ps.max_dac1_clock = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

873

si->ps.max_dac1_clock_8 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

874

si->ps.max_dac1_clock_16 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

876

si->ps.max_dac1_clock_24 = 280;

src/add-ons/accelerants/matrox/engine/mga_info.c

877

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

878

si->ps.max_dac1_clock_32dh = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

880

si->ps.max_dac2_clock = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

881

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

882

si->ps.max_dac2_clock_16 = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

883

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

884

si->ps.max_dac2_clock_32 = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

886

si->ps.max_dac2_clock_32dh = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

888

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

889

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

891

si->ps.memory_size = 8;

src/add-ons/accelerants/matrox/engine/mga_info.c

896

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

904

si->ps.f_ref = 27.000;

src/add-ons/accelerants/matrox/engine/mga_info.c

907

si->ps.max_system_vco = 768;

src/add-ons/accelerants/matrox/engine/mga_info.c

908

si->ps.min_system_vco = 384;

src/add-ons/accelerants/matrox/engine/mga_info.c

909

si->ps.max_pixel_vco = 960;

src/add-ons/accelerants/matrox/engine/mga_info.c

910

si->ps.min_pixel_vco = 320;

src/add-ons/accelerants/matrox/engine/mga_info.c

911

si->ps.max_video_vco = 960;

src/add-ons/accelerants/matrox/engine/mga_info.c

912

si->ps.min_video_vco = 320;

src/add-ons/accelerants/matrox/engine/mga_info.c

913

si->ps.max_dac1_clock = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

914

si->ps.max_dac1_clock_8 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

915

si->ps.max_dac1_clock_16 = 360;

src/add-ons/accelerants/matrox/engine/mga_info.c

917

si->ps.max_dac1_clock_24 = 280;

src/add-ons/accelerants/matrox/engine/mga_info.c

918

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/matrox/engine/mga_info.c

919

si->ps.max_dac1_clock_32dh = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

921

si->ps.max_dac2_clock = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

922

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

923

si->ps.max_dac2_clock_16 = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

924

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/matrox/engine/mga_info.c

925

si->ps.max_dac2_clock_32 = 232;

src/add-ons/accelerants/matrox/engine/mga_info.c

927

si->ps.max_dac2_clock_32dh = 180;

src/add-ons/accelerants/matrox/engine/mga_info.c

929

si->ps.primary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

930

si->ps.secondary_dvi = false;

src/add-ons/accelerants/matrox/engine/mga_info.c

932

si->ps.memory_size = 8;

src/add-ons/accelerants/matrox/engine/mga_info.c

937

si->ps.sdram = true;

src/add-ons/accelerants/matrox/engine/mga_info.c

943

LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));

src/add-ons/accelerants/matrox/engine/mga_info.c

944

LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

945

LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

946

LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

947

LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

948

LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

949

LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco));

src/add-ons/accelerants/matrox/engine/mga_info.c

950

LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));

src/add-ons/accelerants/matrox/engine/mga_info.c

951

LOG(2,("std_engine_clock_dh: %dMhz\n", si->ps.std_engine_clock_dh));

src/add-ons/accelerants/matrox/engine/mga_info.c

952

LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));

src/add-ons/accelerants/matrox/engine/mga_info.c

953

LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));

src/add-ons/accelerants/matrox/engine/mga_info.c

954

LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));

src/add-ons/accelerants/matrox/engine/mga_info.c

955

LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));

src/add-ons/accelerants/matrox/engine/mga_info.c

956

LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));

src/add-ons/accelerants/matrox/engine/mga_info.c

957

LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh));

src/add-ons/accelerants/matrox/engine/mga_info.c

958

LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock));

src/add-ons/accelerants/matrox/engine/mga_info.c

959

LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8));

src/add-ons/accelerants/matrox/engine/mga_info.c

960

LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16));

src/add-ons/accelerants/matrox/engine/mga_info.c

961

LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24));

src/add-ons/accelerants/matrox/engine/mga_info.c

962

LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32));

src/add-ons/accelerants/matrox/engine/mga_info.c

963

LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh));

src/add-ons/accelerants/matrox/engine/mga_info.c

965

if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/matrox/engine/mga_info.c

967

if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/matrox/engine/mga_info.c

969

if ((si->ps.tvout) && (si->ps.card_type < G450))

src/add-ons/accelerants/matrox/engine/mga_info.c

971

if (si->ps.card_type < G400)

src/add-ons/accelerants/matrox/engine/mga_info.c

981

if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/matrox/engine/mga_info.c

983

if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/matrox/engine/mga_info.c

984

LOG(2,("card memory_size: %dMb\n", si->ps.memory_size));

src/add-ons/accelerants/matrox/engine/mga_info.c

985

LOG(2,("mctlwtst register: $%08x\n", si->ps.mctlwtst_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

986

LOG(2,("memrdbk register: $%08x\n", si->ps.memrdbk_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

987

LOG(2,("option register: $%08x\n", si->ps.option_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

988

LOG(2,("option2 register: $%08x\n", si->ps.option2_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

989

LOG(2,("option3 register: $%08x\n", si->ps.option3_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

990

LOG(2,("option4 register: $%08x\n", si->ps.option4_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

991

LOG(2,("v3_option2_reg: $%02x\n", si->ps.v3_option2_reg));

src/add-ons/accelerants/matrox/engine/mga_info.c

992

LOG(2,("v3_clock_div: $%02x\n", si->ps.v3_clk_div));

src/add-ons/accelerants/matrox/engine/mga_info.c

993

LOG(2,("v3_mem_type: $%02x\n", si->ps.v3_mem_type));

src/add-ons/accelerants/matrox/engine/mga_info.c

994

LOG(2,("v5_mem_type: $%04x\n", si->ps.v5_mem_type));

src/add-ons/accelerants/matrox/engine/mga_info.c

996

if (si->ps.sdram) LOG(2,("SDRAM card\n")); else LOG(2,("SGRAM card\n"));

src/add-ons/accelerants/matrox/engine/mga_maven.c

116

if (si->ps.card_type > G400MAX) return B_OK;

src/add-ons/accelerants/matrox/engine/mga_maven.c

143

MAVWW(HVIDRSTL, (target.timing.h_total - si->crtc_delay));

src/add-ons/accelerants/matrox/engine/mga_maven.c

178

if ((offset - ((int)si->maven_syncpol_offset)) < 0) cnt = 4;

src/add-ons/accelerants/matrox/engine/mga_maven.c

179

cnt += offset - si->maven_syncpol_offset;

src/add-ons/accelerants/matrox/engine/mga_maven.c

181

si->maven_syncpol_offset = offset;

src/add-ons/accelerants/matrox/engine/mga_maven.c

212

if (si->ps.card_type > G400MAX) return B_OK;

src/add-ons/accelerants/matrox/engine/mga_maven.c

230

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maven.c

249

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maven.c

346

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maven.c

366

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/engine/mga_maven.c

369

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_maven.c

373

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_maven.c

378

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/engine/mga_maven.c

382

if (req_pclk < (si->ps.min_video_vco / 8.0))

src/add-ons/accelerants/matrox/engine/mga_maven.c

385

req_pclk, (float)(si->ps.min_video_vco / 8.0)));

src/add-ons/accelerants/matrox/engine/mga_maven.c

386

req_pclk = (si->ps.min_video_vco / 8.0);

src/add-ons/accelerants/matrox/engine/mga_maven.c

403

if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))

src/add-ons/accelerants/matrox/engine/mga_maven.c

409

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_maven.c

41

if (si->ps.card_type > G400MAX) return B_OK;

src/add-ons/accelerants/matrox/engine/mga_maven.c

414

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_maven.c

434

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/matrox/engine/mga_maven.c

437

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maven.c

46

if ((si->ps.card_type >= G100) && si->settings.hardcursor) pointer_reservation = 1024;

src/add-ons/accelerants/matrox/engine/mga_maven.c

49

screensize = si->fbc.bytes_per_row * si->dm.virtual_height;

src/add-ons/accelerants/matrox/engine/mga_maven.c

52

if ((screensize + si->fbc.bytes_per_row + pointer_reservation) <=

src/add-ons/accelerants/matrox/engine/mga_maven.c

53

(si->ps.memory_size * 1024 * 1024))

src/add-ons/accelerants/matrox/engine/mga_maven.c

58

adr = (uint8*)si->fbc.frame_buffer;

src/add-ons/accelerants/matrox/engine/mga_maven.c

583

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/matrox/engine/mga_maven.c

586

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_maven.c

590

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/matrox/engine/mga_maven.c

595

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/matrox/engine/mga_maven.c

599

if (req_pclk < (si->ps.min_video_vco / 16.0))

src/add-ons/accelerants/matrox/engine/mga_maven.c

602

req_pclk, (float)(si->ps.min_video_vco / 16.0)));

src/add-ons/accelerants/matrox/engine/mga_maven.c

603

req_pclk = (si->ps.min_video_vco / 16.0);

src/add-ons/accelerants/matrox/engine/mga_maven.c

61

for (x = 0; x < si->fbc.bytes_per_row; x++)

src/add-ons/accelerants/matrox/engine/mga_maven.c

620

if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))

src/add-ons/accelerants/matrox/engine/mga_maven.c

626

n = (int)(((f_vco * m) / (si->ps.f_ref * 2)) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_maven.c

632

error = fabs(req_pclk - ((((si->ps.f_ref * 2)/ m) * n) / p));

src/add-ons/accelerants/matrox/engine/mga_maven.c

669

f_vco = ((si->ps.f_ref * 2) / (m + 1)) * (n + 2);

src/add-ons/accelerants/matrox/engine/mga_maven.c

75

if (si->ps.card_type > G400MAX) return B_OK;

src/add-ons/accelerants/matrox/engine/mga_maven.c

80

if (!(si->dm.flags & TV_BITS))

src/add-ons/accelerants/matrox/engine/mga_maventv.c

106

if (req_pclks_field < (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0))

src/add-ons/accelerants/matrox/engine/mga_maventv.c

108

req_pclks_field = (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

125

if ((vco_clks_field >= ((si->ps.min_video_vco * 1000000) / fields_sec)) &&

src/add-ons/accelerants/matrox/engine/mga_maventv.c

126

(vco_clks_field <= ((si->ps.max_video_vco * 1000000) / fields_sec)))

src/add-ons/accelerants/matrox/engine/mga_maventv.c

132

n = (int)(((vco_clks_field * m) / ((si->ps.f_ref * 1000000) / fields_sec)) + 0.5);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

1383

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

139

(((uint32)((si->ps.f_ref * 1000000) / fields_sec)) * n) / ((float)(m * p));

src/add-ons/accelerants/matrox/engine/mga_maventv.c

1395

if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x00);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

1407

if (si->ps.secondary_head)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

1419

if (si->ps.card_type <= G400MAX) MAVW(RESYNC, 0x20);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

166

f_vco = (si->ps.f_ref / m) * n;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

199

if (si->ps.f_ref == 27.000)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

216

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

219

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

321

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

333

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

378

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

392

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

400

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

476

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

488

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

52

switch (si->ps.card_type)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

533

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

547

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

555

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

676

if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x01);

src/add-ons/accelerants/matrox/engine/mga_maventv.c

684

if (si->ps.card_type <= G400MAX)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

710

si->maven_syncpol_offset += 1;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

711

if (si->maven_syncpol_offset > 3) si->maven_syncpol_offset = 0;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

78

max_pclks_field = (si->ps.max_dac2_clock_16 * 1000000) / fields_sec;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

788

if (!si->ps.secondary_head) si->crtc_delay += 12;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

81

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

85

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

858

if (!si->ps.secondary_head)

src/add-ons/accelerants/matrox/engine/mga_maventv.c

889

si->crtc_delay += 1;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

893

si->crtc_delay -= 3;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

90

max_pclks_field = (si->ps.max_dac2_clock_32dh * 1000000) / fields_sec;

src/add-ons/accelerants/matrox/engine/mga_maventv.c

915

MAVWW(HVIDRSTL, (ht_last_line - si->crtc_delay -

src/add-ons/accelerants/matrox/engine/mga_proto.h

14

uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \

src/add-ons/accelerants/matrox/engine/mga_proto.h

15

uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \

src/add-ons/accelerants/matrox/engine/mga_support.c

28

si->vendor_id, si->device_id, si->bus, si->device, si->function,

src/add-ons/accelerants/matrox/global.h

2

extern shared_info *si;

src/add-ons/accelerants/neomagic/Cursor.c

104

si->cursor.is_visible = is_visible;

src/add-ons/accelerants/neomagic/Cursor.c

31

si->cursor.width = width;

src/add-ons/accelerants/neomagic/Cursor.c

32

si->cursor.height = height;

src/add-ons/accelerants/neomagic/Cursor.c

33

si->cursor.hot_x = hot_x;

src/add-ons/accelerants/neomagic/Cursor.c

34

si->cursor.hot_y = hot_y;

src/add-ons/accelerants/neomagic/Cursor.c

43

uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */

src/add-ons/accelerants/neomagic/Cursor.c

44

uint16 vds = si->dm.v_display_start; /* the current vertical starting line */

src/add-ons/accelerants/neomagic/Cursor.c

46

uint16 h_display = si->dm.timing.h_display; /* local copy needed for flatpanel */

src/add-ons/accelerants/neomagic/Cursor.c

47

uint16 v_display = si->dm.timing.v_display; /* local copy needed for flatpanel */

src/add-ons/accelerants/neomagic/Cursor.c

50

if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;

src/add-ons/accelerants/neomagic/Cursor.c

51

if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;

src/add-ons/accelerants/neomagic/Cursor.c

54

si->cursor.x = x;

src/add-ons/accelerants/neomagic/Cursor.c

55

si->cursor.y = y;

src/add-ons/accelerants/neomagic/Cursor.c

64

if (h_display > si->ps.panel_width) h_display = si->ps.panel_width;

src/add-ons/accelerants/neomagic/Cursor.c

65

if (v_display > si->ps.panel_height) v_display = si->ps.panel_height;

src/add-ons/accelerants/neomagic/Cursor.c

73

if ((hds + h_display) > si->dm.virtual_width)

src/add-ons/accelerants/neomagic/Cursor.c

85

if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))

src/add-ons/accelerants/neomagic/Cursor.c

92

if (x > (hds + si->cursor.hot_x)) x -= hds + si->cursor.hot_x;

src/add-ons/accelerants/neomagic/Cursor.c

94

if (y > (vds + si->cursor.hot_y)) y -= vds + si->cursor.hot_y;

src/add-ons/accelerants/neomagic/EngineManagment.c

26

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/neomagic/EngineManagment.c

41

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/neomagic/EngineManagment.c

55

st->counter = si->engine.count;

src/add-ons/accelerants/neomagic/GetAccelerantHook.c

172

if (si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/GetAccelerantHook.c

216

if (si->acc_mode)

src/add-ons/accelerants/neomagic/GetAccelerantHook.c

32

#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0;

src/add-ons/accelerants/neomagic/GetDeviceInfo.c

18

sprintf(adi->name, si->adi.name);

src/add-ons/accelerants/neomagic/GetDeviceInfo.c

19

sprintf(adi->chipset, si->adi.chipset);

src/add-ons/accelerants/neomagic/GetDeviceInfo.c

21

adi->memory = (si->ps.memory_size * 1024);

src/add-ons/accelerants/neomagic/GetDeviceInfo.c

22

adi->dac_speed = si->ps.max_dac1_clock;

src/add-ons/accelerants/neomagic/GetModeInfo.c

22

*current_mode = si->dm;

src/add-ons/accelerants/neomagic/GetModeInfo.c

32

*afb = si->fbc;

src/add-ons/accelerants/neomagic/GetModeInfo.c

49

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/GetModeInfo.c

52

*low = (si->ps.min_pixel_vco * 1000);

src/add-ons/accelerants/neomagic/GetModeInfo.c

59

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/neomagic/GetModeInfo.c

63

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/neomagic/GetModeInfo.c

66

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/neomagic/GetModeInfo.c

70

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/neomagic/GetModeInfo.c

89

if (si->ps.int_assigned)

src/add-ons/accelerants/neomagic/InitAccelerant.c

107

if (si->ps.card_type > NM2093)

src/add-ons/accelerants/neomagic/InitAccelerant.c

118

si = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

150

if (si->accelerant_in_use)

src/add-ons/accelerants/neomagic/InitAccelerant.c

180

si->cursor.width = 16;

src/add-ons/accelerants/neomagic/InitAccelerant.c

181

si->cursor.height = 16;

src/add-ons/accelerants/neomagic/InitAccelerant.c

182

si->cursor.hot_x = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

183

si->cursor.hot_y = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

184

si->cursor.x = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

185

si->cursor.y = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

193

si->fbc.frame_buffer = si->framebuffer;

src/add-ons/accelerants/neomagic/InitAccelerant.c

194

si->fbc.frame_buffer_dma = si->framebuffer_pci;

src/add-ons/accelerants/neomagic/InitAccelerant.c

197

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

198

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/neomagic/InitAccelerant.c

200

INIT_BEN(si->overlay.lock);

src/add-ons/accelerants/neomagic/InitAccelerant.c

204

si->overlay.myBuffer[cnt].buffer = NULL;

src/add-ons/accelerants/neomagic/InitAccelerant.c

205

si->overlay.myBuffer[cnt].buffer_dma = NULL;

src/add-ons/accelerants/neomagic/InitAccelerant.c

208

si->overlay.myToken = NULL;

src/add-ons/accelerants/neomagic/InitAccelerant.c

211

si->overlay.active = false;

src/add-ons/accelerants/neomagic/InitAccelerant.c

223

si->dpms_flags = B_DPMS_ON;

src/add-ons/accelerants/neomagic/InitAccelerant.c

228

si->accelerant_in_use = true;

src/add-ons/accelerants/neomagic/InitAccelerant.c

312

if (!(si->accelerant_in_use))

src/add-ons/accelerants/neomagic/InitAccelerant.c

324

si->mode_area

src/add-ons/accelerants/neomagic/InitAccelerant.c

35

shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS,

src/add-ons/accelerants/neomagic/InitAccelerant.c

355

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/neomagic/InitAccelerant.c

356

DELETE_BEN(si->overlay.lock);

src/add-ons/accelerants/neomagic/InitAccelerant.c

359

si->accelerant_in_use = false;

src/add-ons/accelerants/neomagic/InitAccelerant.c

43

si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios));

src/add-ons/accelerants/neomagic/InitAccelerant.c

46

if (si->regs_in_fb)

src/add-ons/accelerants/neomagic/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/neomagic/InitAccelerant.c

59

if (si->use_clone_bugfix)

src/add-ons/accelerants/neomagic/InitAccelerant.c

63

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/neomagic/InitAccelerant.c

64

regs2 = si->clone_bugfix_regs2;

src/add-ons/accelerants/neomagic/InitAccelerant.c

70

B_READ_AREA | B_WRITE_AREA, si->regs_area);

src/add-ons/accelerants/neomagic/InitAccelerant.c

79

B_READ_AREA | B_WRITE_AREA, si->regs2_area);

src/add-ons/accelerants/neomagic/Overlay.c

103

si->overlay.myBuffer[offset].width = (width & ~0x0007) + 8;

src/add-ons/accelerants/neomagic/Overlay.c

105

si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;

src/add-ons/accelerants/neomagic/Overlay.c

109

if (si->overlay.myBuffer[offset].width > 2048)

src/add-ons/accelerants/neomagic/Overlay.c

114

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

124

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

131

if (si->overlay.myBuffer[offset].width > 1024)

src/add-ons/accelerants/neomagic/Overlay.c

136

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

146

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

152

si->overlay.myBufInfo[offset].slopspace = si->overlay.myBuffer[offset].width - width;

src/add-ons/accelerants/neomagic/Overlay.c

154

si->overlay.myBuffer[offset].space = cs;

src/add-ons/accelerants/neomagic/Overlay.c

155

si->overlay.myBuffer[offset].height = height;

src/add-ons/accelerants/neomagic/Overlay.c

182

adress2 = (((uint32)((uint8*)si->fbc.frame_buffer)) + /* cursor not yet included here */

src/add-ons/accelerants/neomagic/Overlay.c

183

(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */

src/add-ons/accelerants/neomagic/Overlay.c

187

oldsize = si->overlay.myBufInfo[offset].size;

src/add-ons/accelerants/neomagic/Overlay.c

188

si->overlay.myBufInfo[offset].size =

src/add-ons/accelerants/neomagic/Overlay.c

189

si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;

src/add-ons/accelerants/neomagic/Overlay.c

192

adress = (((uint32)((uint8*)si->framebuffer)) + (si->ps.memory_size * 1024));

src/add-ons/accelerants/neomagic/Overlay.c

194

if(si->settings.hardcursor) adress -= si->ps.curmem_size;

src/add-ons/accelerants/neomagic/Overlay.c

198

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/neomagic/Overlay.c

206

temp32 = (adress - ((uint32)((vuint32 *)si->framebuffer)));

src/add-ons/accelerants/neomagic/Overlay.c

211

si->overlay.myBufInfo[offset].size += (temp32 - (temp32 & 0xfffffff0));

src/add-ons/accelerants/neomagic/Overlay.c

232

if (si->overlay.myBuffer[cnt].buffer != NULL)

src/add-ons/accelerants/neomagic/Overlay.c

235

if (si->overlay.myBufInfo[offset].size <= oldsize)

src/add-ons/accelerants/neomagic/Overlay.c

239

adress -= (oldsize - si->overlay.myBufInfo[offset].size);

src/add-ons/accelerants/neomagic/Overlay.c

240

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/neomagic/Overlay.c

253

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/neomagic/Overlay.c

256

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

271

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

276

si->overlay.myBuffer[offset].buffer = (void *) adress;

src/add-ons/accelerants/neomagic/Overlay.c

279

adress = (((uint32)((uint8*)si->framebuffer_pci)) + (si->ps.memory_size * 1024));

src/add-ons/accelerants/neomagic/Overlay.c

281

if(si->settings.hardcursor) adress -= si->ps.curmem_size;

src/add-ons/accelerants/neomagic/Overlay.c

284

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/neomagic/Overlay.c

287

si->overlay.myBuffer[offset].buffer_dma = (void *) adress;

src/add-ons/accelerants/neomagic/Overlay.c

290

(uint32)((uint8*)si->overlay.myBuffer[offset].buffer),

src/add-ons/accelerants/neomagic/Overlay.c

291

(uint32)((uint8*)si->overlay.myBuffer[offset].buffer_dma), cs));

src/add-ons/accelerants/neomagic/Overlay.c

292

LOG(4,("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));

src/add-ons/accelerants/neomagic/Overlay.c

295

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

297

return &si->overlay.myBuffer[offset];

src/add-ons/accelerants/neomagic/Overlay.c

305

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

321

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/neomagic/Overlay.c

327

si->overlay.myBuffer[offset].buffer = NULL;

src/add-ons/accelerants/neomagic/Overlay.c

328

si->overlay.myBuffer[offset].buffer_dma = NULL;

src/add-ons/accelerants/neomagic/Overlay.c

368

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/neomagic/Overlay.c

452

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

455

if (si->overlay.myToken == NULL)

src/add-ons/accelerants/neomagic/Overlay.c

460

si->overlay.myToken = &tmpToken;

src/add-ons/accelerants/neomagic/Overlay.c

463

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

465

return si->overlay.myToken;

src/add-ons/accelerants/neomagic/Overlay.c

473

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

484

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/neomagic/Overlay.c

499

si->overlay.myToken = NULL;

src/add-ons/accelerants/neomagic/Overlay.c

542

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/neomagic/Overlay.c

555

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/neomagic/Overlay.c

76

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/neomagic/Overlay.c

78

LOG(4,("Overlay: cardRAM_start = $%p\n",((uint8*)si->framebuffer)));

src/add-ons/accelerants/neomagic/Overlay.c

79

LOG(4,("Overlay: cardRAM_start_DMA = $%p\n",((uint8*)si->framebuffer_pci)));

src/add-ons/accelerants/neomagic/Overlay.c

80

LOG(4,("Overlay: cardRAM_size = %dKb\n",si->ps.memory_size));

src/add-ons/accelerants/neomagic/Overlay.c

85

if (si->overlay.myBuffer[offset].buffer == NULL) break;

src/add-ons/accelerants/neomagic/Overlay.c

99

si->overlay.myBuffer[offset].width = width;

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

141

if ((si->ps.card_type == NM2070) && (target->space == B_RGB24_LITTLE))

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

246

if (si->settings.hardcursor) pointer_reservation = si->ps.curmem_size;

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

249

((si->ps.memory_size * 1024) - pointer_reservation))

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

252

((si->ps.memory_size * 1024) - pointer_reservation) / row_bytes;

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

302

if (si->settings.hardcursor)

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

306

if (si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

326

LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

328

return si->mode_count;

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

336

memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

358

si->mode_area = my_mode_list_area =

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

366

si->mode_count = 0;

src/add-ons/accelerants/neomagic/ProposeDisplayMode.c

395

si->mode_count++;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

106

nm_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);

src/add-ons/accelerants/neomagic/SetDisplayMode.c

139

si->dm = target;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

145

SET_DPMS_MODE(si->dpms_flags);

src/add-ons/accelerants/neomagic/SetDisplayMode.c

171

uint16 h_display = si->dm.timing.h_display; /* local copy needed for flatpanel */

src/add-ons/accelerants/neomagic/SetDisplayMode.c

172

uint16 v_display = si->dm.timing.v_display; /* local copy needed for flatpanel */

src/add-ons/accelerants/neomagic/SetDisplayMode.c

180

switch(si->dm.space)

src/add-ons/accelerants/neomagic/SetDisplayMode.c

199

if (h_display > si->ps.panel_width) h_display = si->ps.panel_width;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

200

if (v_display > si->ps.panel_height) v_display = si->ps.panel_height;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

204

if ((h_display + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/neomagic/SetDisplayMode.c

206

if ((v_display + v_display_start) > si->dm.virtual_height)

src/add-ons/accelerants/neomagic/SetDisplayMode.c

210

si->dm.h_display_start = h_display_start;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

211

si->dm.v_display_start = v_display_start;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

214

startadd = v_display_start * si->fbc.bytes_per_row;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

216

startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

23

if (si->ps.int_assigned) {

src/add-ons/accelerants/neomagic/SetDisplayMode.c

232

if (si->dm.space != B_CMAP8) return;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

234

r = si->color_data;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

257

si->dpms_flags = dpms_flags;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

285

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/SetDisplayMode.c

297

return si->dpms_flags;

src/add-ons/accelerants/neomagic/SetDisplayMode.c

87

startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/neomagic/engine/nm_acc.c

100

si->engine.control |= (5 << 10);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

103

si->engine.control |= (6 << 10);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

106

si->engine.control |= (7 << 10);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

118

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

122

si->engine.control |= (1 << 27);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

149

switch(si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

160

ACCW(2070_SRCPITCH, si->fbc.bytes_per_row);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

162

ACCW(2070_DSTPITCH, si->fbc.bytes_per_row);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

176

ACCW(STATUS, ((si->engine.control & 0x0000ffff) << 16));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

179

((si->fbc.bytes_per_row << 16) | (si->fbc.bytes_per_row & 0x0000ffff)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

193

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

207

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

211

ACCW(CONTROL, si->engine.control | 0x000c0000);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

214

ACCW(SRCSTARTOFF, ((ys * si->fbc.bytes_per_row) + (xs * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

215

ACCW(2070_DSTSTARTOFF, ((yd * si->fbc.bytes_per_row) + (xd * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

222

ACCW(CONTROL, si->engine.control | 0x830c0000);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

233

ACCW(SRCSTARTOFF, ((ys * si->fbc.bytes_per_row) + (xs * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

234

ACCW(2090_DSTSTARTOFF, ((yd * si->fbc.bytes_per_row) + (xd * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

242

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

246

ACCW(CONTROL, (si->engine.control | 0x000c0013));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

249

ACCW(SRCSTARTOFF, (((ys + h) * si->fbc.bytes_per_row) + ((xs + w) * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

250

ACCW(2070_DSTSTARTOFF, (((yd + h) * si->fbc.bytes_per_row) + ((xd + w) * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

257

ACCW(CONTROL, (si->engine.control | 0x830c0013));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

268

ACCW(SRCSTARTOFF, (((ys + h) * si->fbc.bytes_per_row) + ((xs + w) * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

269

ACCW(2090_DSTSTARTOFF, (((yd + h) * si->fbc.bytes_per_row) + ((xd + w) * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

283

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

294

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

298

ACCW(CONTROL, (si->engine.control | 0x000c0008));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

300

if (si->engine.depth == 1)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

311

ACCW(CONTROL, (si->engine.control | 0x830c0008));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

335

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

347

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

351

ACCW(2070_DSTSTARTOFF, ((ys * si->fbc.bytes_per_row) + (xs * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

366

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

377

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

385

ACCW(CONTROL, (si->engine.control | 0x00050000));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

392

ACCW(CONTROL, (si->engine.control | 0x83050008));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

412

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

424

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

428

ACCW(2070_DSTSTARTOFF, ((ys * si->fbc.bytes_per_row) + (xs * si->engine.depth)));

src/add-ons/accelerants/neomagic/engine/nm_acc.c

61

switch(si->dm.space)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

65

si->engine.control = (1 << 8);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

66

si->engine.depth = 1;

src/add-ons/accelerants/neomagic/engine/nm_acc.c

70

si->engine.control = (2 << 8);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

71

si->engine.depth = 2;

src/add-ons/accelerants/neomagic/engine/nm_acc.c

75

si->engine.control = (3 << 8);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

76

si->engine.depth = 3;

src/add-ons/accelerants/neomagic/engine/nm_acc.c

78

if (si->ps.card_type >= NM2200) break;

src/add-ons/accelerants/neomagic/engine/nm_acc.c

86

if(si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

88

switch(si->fbc.bytes_per_row / si->engine.depth)

src/add-ons/accelerants/neomagic/engine/nm_acc.c

91

si->engine.control |= (2 << 10);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

94

si->engine.control |= (3 << 10);

src/add-ons/accelerants/neomagic/engine/nm_acc.c

97

si->engine.control |= (4 << 10);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

108

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

115

if (si->overlay.ow.v_start >= (crtc_vend - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

123

temp1 = (si->overlay.ow.v_start - crtc_vstart);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

130

if (si->overlay.ow.height < 2)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

137

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) > (crtc_vend - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

144

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

152

temp2 = ((uint16)(si->overlay.ow.v_start + si->overlay.ow.height - crtc_vstart - 1));

src/add-ons/accelerants/neomagic/engine/nm_bes.c

174

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

178

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

181

hsrcstv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

186

hsrcstv += (crtc_hstart - si->overlay.ow.h_start);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

192

hsrcstv *= (si->overlay.h_ifactor << 4);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

195

hsrcstv += ((uint32)si->overlay.my_ov.h_start) << 16;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

20

if (!si->overlay.active) return;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

208

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

212

if (si->overlay.ow.h_start > (crtc_hend - 2))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

215

moi->hsrcendv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

220

moi->hsrcendv += ((si->overlay.ow.h_start + si->overlay.ow.width - 1) - (crtc_hend - 1));

src/add-ons/accelerants/neomagic/engine/nm_bes.c

226

moi->hsrcendv *= (si->overlay.h_ifactor << 4);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

228

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16) - moi->hsrcendv;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

233

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

245

moi->a1orgv = (uintptr_t)((vuint32 *)si->overlay.ob.buffer);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

246

moi->a1orgv -= (uintptr_t)((vuint32 *)si->framebuffer);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

258

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

262

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

269

((((si->overlay.ow.height - 2) * (si->overlay.v_ifactor << 4)) >> 16) *

src/add-ons/accelerants/neomagic/engine/nm_bes.c

270

si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

279

((((crtc_vstart - si->overlay.ow.v_start) * (si->overlay.v_ifactor << 4)) >> 16) *

src/add-ons/accelerants/neomagic/engine/nm_bes.c

280

si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

285

moi->a1orgv += (si->overlay.my_ov.v_start * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

309

if (si->ps.card_type >= NM2097)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

324

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

37

crtc_hstart = si->dm.h_display_start;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

384

bi.card_type = si->ps.card_type;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

39

crtc_hend = crtc_hstart + si->dm.timing.h_display;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

40

crtc_vstart = si->dm.v_display_start;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

42

crtc_vend = crtc_vstart + si->dm.timing.v_display;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

425

if (my_ov.h_start > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

426

my_ov.h_start = ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

427

if (((my_ov.h_start + my_ov.width) - 1) > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

428

my_ov.width = ((((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1) - my_ov.h_start) + 1);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

438

si->overlay.ow = *ow;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

439

si->overlay.ob = *ob;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

440

si->overlay.my_ov = my_ov;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

448

(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));

src/add-ons/accelerants/neomagic/engine/nm_bes.c

458

si->overlay.h_ifactor = ifactor;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

492

si->overlay.v_ifactor = ifactor;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

53

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

568

if (si->ps.card_type >= NM2097)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

591

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

60

if (si->overlay.ow.h_start >= (crtc_hend - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

674

bi.card_type = si->ps.card_type;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

68

temp1 = (si->overlay.ow.h_start - crtc_hstart);

src/add-ons/accelerants/neomagic/engine/nm_bes.c

686

si->overlay.active = true;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

694

if (si->ps.card_type >= NM2097)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

708

si->overlay.active = false;

src/add-ons/accelerants/neomagic/engine/nm_bes.c

75

if (si->overlay.ow.width < 2)

src/add-ons/accelerants/neomagic/engine/nm_bes.c

82

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

89

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/neomagic/engine/nm_bes.c

97

temp2 = ((uint16)(si->overlay.ow.h_start + si->overlay.ow.width - crtc_hstart - 1));

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

1010

cursor = (vuint8*) si->framebuffer;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

1011

cursor += ((si->ps.memory_size * 1024) - si->ps.curmem_size);

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

1054

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

117

if (target.timing.h_display > si->ps.panel_width)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

119

target.timing.h_display = si->ps.panel_width;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

123

if (target.timing.v_display > si->ps.panel_height)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

125

target.timing.v_display = si->ps.panel_height;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

214

if (si->ps.card_type >= NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

272

if (si->ps.card_type >= NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

316

if (si->ps.card_type != NM2070)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

32

if (*hd_e > si->ps.max_crtc_width) *hd_e = si->ps.max_crtc_width;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

341

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

387

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

472

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

52

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

527

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

536

if (si->ps.card_type != NM2070)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

548

LOG(2,("CRTC: frameRAM: $%08x\n",si->framebuffer));

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

549

LOG(2,("CRTC: framebuffer: $%08x\n",si->fbc.frame_buffer));

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

584

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

632

if (target.timing.h_display < si->ps.panel_width)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

634

hoffset = (si->ps.panel_width - target.timing.h_display);

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

642

if (target.timing.v_display < si->ps.panel_height)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

644

voffset = (si->ps.panel_height - target.timing.v_display);

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

689

if (si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

69

if (*vd_e > si->ps.max_crtc_height) *vd_e = si->ps.max_crtc_height;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

696

if (si->ps.card_type >= NM2160)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

700

if (si->ps.card_type >= NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

713

if (si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

734

if (si->ps.card_type > NM2070) return B_OK;

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

736

switch(si->ps.panel_width)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

759

switch(si->ps.panel_height)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

779

if (si->ps.card_type > NM2070)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

827

switch(si->ps.panel_height)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

921

curadd = ((si->ps.memory_size * 1024) - si->ps.curmem_size);

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

930

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

936

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

958

fb = ((vuint32 *)(((uintptr_t)si->framebuffer) + curadd));

src/add-ons/accelerants/neomagic/engine/nm_crtc.c

972

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_dac.c

165

if (si->ps.card_type >= NM2200)

src/add-ons/accelerants/neomagic/engine/nm_dac.c

17

r = si->color_data;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

213

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_dac.c

239

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

243

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

246

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

250

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

256

if (req_pclk < si->ps.min_pixel_vco)

src/add-ons/accelerants/neomagic/engine/nm_dac.c

259

req_pclk, (float)si->ps.min_pixel_vco));

src/add-ons/accelerants/neomagic/engine/nm_dac.c

260

req_pclk = si->ps.min_pixel_vco;

src/add-ons/accelerants/neomagic/engine/nm_dac.c

280

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/neomagic/engine/nm_dac.c

285

error = fabs(req_pclk - ((si->ps.f_ref / m) * n));

src/add-ons/accelerants/neomagic/engine/nm_dac.c

312

*calc_pclk = (si->ps.f_ref / best[0]) * best[1];

src/add-ons/accelerants/neomagic/engine/nm_dac.c

314

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_general.c

106

si->ps.card_type = NM2070;

src/add-ons/accelerants/neomagic/engine/nm_general.c

107

sprintf(si->adi.name, "Neomagic MagicGraph 128");

src/add-ons/accelerants/neomagic/engine/nm_general.c

108

sprintf(si->adi.chipset, "NM2070 (ISA)");

src/add-ons/accelerants/neomagic/engine/nm_general.c

111

si->ps.card_type = NM2090;

src/add-ons/accelerants/neomagic/engine/nm_general.c

112

sprintf(si->adi.name, "Neomagic MagicGraph 128V");

src/add-ons/accelerants/neomagic/engine/nm_general.c

113

sprintf(si->adi.chipset, "NM2090 (ISA)");

src/add-ons/accelerants/neomagic/engine/nm_general.c

116

si->ps.card_type = NM2093;

src/add-ons/accelerants/neomagic/engine/nm_general.c

117

sprintf(si->adi.name, "Neomagic MagicGraph 128ZV");

src/add-ons/accelerants/neomagic/engine/nm_general.c

118

sprintf(si->adi.chipset, "NM2093 (ISA)");

src/add-ons/accelerants/neomagic/engine/nm_general.c

121

si->ps.card_type = NM2097;

src/add-ons/accelerants/neomagic/engine/nm_general.c

122

sprintf(si->adi.name, "Neomagic MagicGraph 128ZV+");

src/add-ons/accelerants/neomagic/engine/nm_general.c

123

sprintf(si->adi.chipset, "NM2097 (PCI)");

src/add-ons/accelerants/neomagic/engine/nm_general.c

126

si->ps.card_type = NM2160;

src/add-ons/accelerants/neomagic/engine/nm_general.c

127

sprintf(si->adi.name, "Neomagic MagicGraph 128XD");

src/add-ons/accelerants/neomagic/engine/nm_general.c

128

sprintf(si->adi.chipset, "NM2160 (PCI)");

src/add-ons/accelerants/neomagic/engine/nm_general.c

131

si->ps.card_type = NM2200;

src/add-ons/accelerants/neomagic/engine/nm_general.c

132

sprintf(si->adi.name, "Neomagic MagicMedia 256AV");

src/add-ons/accelerants/neomagic/engine/nm_general.c

133

sprintf(si->adi.chipset, "NM2200");

src/add-ons/accelerants/neomagic/engine/nm_general.c

136

si->ps.card_type = NM2230;

src/add-ons/accelerants/neomagic/engine/nm_general.c

137

sprintf(si->adi.name, "Neomagic MagicMedia 256AV+");

src/add-ons/accelerants/neomagic/engine/nm_general.c

138

sprintf(si->adi.chipset, "NM2230");

src/add-ons/accelerants/neomagic/engine/nm_general.c

141

si->ps.card_type = NM2360;

src/add-ons/accelerants/neomagic/engine/nm_general.c

142

sprintf(si->adi.name, "Neomagic MagicMedia 256ZX");

src/add-ons/accelerants/neomagic/engine/nm_general.c

143

sprintf(si->adi.chipset, "NM2360");

src/add-ons/accelerants/neomagic/engine/nm_general.c

146

si->ps.card_type = NM2380;

src/add-ons/accelerants/neomagic/engine/nm_general.c

147

sprintf(si->adi.name, "Neomagic MagicMedia 256XL+");

src/add-ons/accelerants/neomagic/engine/nm_general.c

148

sprintf(si->adi.chipset, "NM2380");

src/add-ons/accelerants/neomagic/engine/nm_general.c

15

#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \

src/add-ons/accelerants/neomagic/engine/nm_general.c

159

if (si->settings.memory != 0)

src/add-ons/accelerants/neomagic/engine/nm_general.c

160

si->ps.memory_size = si->settings.memory;

src/add-ons/accelerants/neomagic/engine/nm_general.c

171

if (si->fbc.frame_buffer == NULL)

src/add-ons/accelerants/neomagic/engine/nm_general.c

180

((uint32 *)si->fbc.frame_buffer)[offset] = value;

src/add-ons/accelerants/neomagic/engine/nm_general.c

188

if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;

src/add-ons/accelerants/neomagic/engine/nm_general.c

225

LOG(4, ("INIT: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/neomagic/engine/nm_general.c

226

if (si->settings.logmask & 0x80000000) nm_dump_configuration_space();

src/add-ons/accelerants/neomagic/engine/nm_general.c

304

if (si->ps.card_type < NM2200)

src/add-ons/accelerants/neomagic/engine/nm_general.c

310

if (size_outputs & 0x03) si->ps.outputs = (size_outputs & 0x03);

src/add-ons/accelerants/neomagic/engine/nm_general.c

321

si->ps.outputs = (size_outputs & 0x03);

src/add-ons/accelerants/neomagic/engine/nm_general.c

326

si->ps.outputs = 0x02;

src/add-ons/accelerants/neomagic/engine/nm_general.c

336

si->ps.outputs &= 0xfe;

src/add-ons/accelerants/neomagic/engine/nm_general.c

337

si->ps.outputs |= (size_outputs & 0x01);

src/add-ons/accelerants/neomagic/engine/nm_general.c

339

if (size_outputs & 0x02) si->ps.outputs |= 0x02;

src/add-ons/accelerants/neomagic/engine/nm_general.c

343

return ((size_outputs & 0xfc) | (si->ps.outputs & 0x03));

src/add-ons/accelerants/neomagic/engine/nm_general.c

444

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_general.c

481

if ((si->ps.card_type < NM2200) && (target->space == B_RGB24)) *acc_mode = false;

src/add-ons/accelerants/neomagic/engine/nm_general.c

484

if (si->ps.card_type == NM2070)

src/add-ons/accelerants/neomagic/engine/nm_general.c

530

if (si->ps.card_type == NM2070)

src/add-ons/accelerants/neomagic/engine/nm_general.c

559

mem_avail = (si->ps.memory_size * 1024);

src/add-ons/accelerants/neomagic/engine/nm_general.c

560

if (si->settings.hardcursor) mem_avail -= si->ps.curmem_size;

src/add-ons/accelerants/neomagic/engine/nm_general.c

94

if (si->ps.int_assigned)

src/add-ons/accelerants/neomagic/engine/nm_globals.c

13

shared_info *si;

src/add-ons/accelerants/neomagic/engine/nm_globals.h

2

extern shared_info *si;

src/add-ons/accelerants/neomagic/engine/nm_info.c

100

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

101

si->ps.max_crtc_width = 1280;

src/add-ons/accelerants/neomagic/engine/nm_info.c

102

si->ps.max_crtc_height = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

103

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

109

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

110

si->ps.max_system_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

111

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

112

si->ps.max_pixel_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

113

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

114

si->ps.max_dac1_clock = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

115

si->ps.max_dac1_clock_8 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

116

si->ps.max_dac1_clock_16 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

117

si->ps.max_dac1_clock_24 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

118

si->ps.memory_size = 3008;

src/add-ons/accelerants/neomagic/engine/nm_info.c

119

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

120

si->ps.max_crtc_width = 1280;

src/add-ons/accelerants/neomagic/engine/nm_info.c

121

si->ps.max_crtc_height = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

122

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

128

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

129

si->ps.max_system_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

13

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

130

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

131

si->ps.max_pixel_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

132

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

133

si->ps.max_dac1_clock = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

134

si->ps.max_dac1_clock_8 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

135

si->ps.max_dac1_clock_16 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

136

si->ps.max_dac1_clock_24 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

137

si->ps.memory_size = 4096;

src/add-ons/accelerants/neomagic/engine/nm_info.c

138

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

139

si->ps.max_crtc_width = 1280;

src/add-ons/accelerants/neomagic/engine/nm_info.c

14

si->ps.max_system_vco = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

140

si->ps.max_crtc_height = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

141

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

147

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

148

si->ps.max_system_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

149

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

15

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

150

si->ps.max_pixel_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

151

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

152

si->ps.max_dac1_clock = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

153

si->ps.max_dac1_clock_8 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

154

si->ps.max_dac1_clock_16 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

155

si->ps.max_dac1_clock_24 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

156

si->ps.memory_size = 6144;

src/add-ons/accelerants/neomagic/engine/nm_info.c

157

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

158

si->ps.max_crtc_width = 1280;

src/add-ons/accelerants/neomagic/engine/nm_info.c

159

si->ps.max_crtc_height = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

16

si->ps.max_pixel_vco = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

160

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

169

switch (si->ps.card_type)

src/add-ons/accelerants/neomagic/engine/nm_info.c

17

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

18

si->ps.max_dac1_clock = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

19

si->ps.max_dac1_clock_8 = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

20

si->ps.max_dac1_clock_16 = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

208

si->ps.panel_width = 640;

src/add-ons/accelerants/neomagic/engine/nm_info.c

209

si->ps.panel_height = 480;

src/add-ons/accelerants/neomagic/engine/nm_info.c

212

si->ps.panel_width = 800;

src/add-ons/accelerants/neomagic/engine/nm_info.c

213

si->ps.panel_height = 600;

src/add-ons/accelerants/neomagic/engine/nm_info.c

216

si->ps.panel_width = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

217

si->ps.panel_height = 768;

src/add-ons/accelerants/neomagic/engine/nm_info.c

22

si->ps.max_dac1_clock_24 = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

221

si->ps.panel_width = 1280;

src/add-ons/accelerants/neomagic/engine/nm_info.c

222

si->ps.panel_height = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

225

si->ps.panel_type = (type & 0x12);

src/add-ons/accelerants/neomagic/engine/nm_info.c

227

si->ps.outputs = (size_outputs & 0x03);

src/add-ons/accelerants/neomagic/engine/nm_info.c

229

if (si->ps.outputs == 0)

src/add-ons/accelerants/neomagic/engine/nm_info.c

23

si->ps.memory_size = 896;

src/add-ons/accelerants/neomagic/engine/nm_info.c

232

si->ps.outputs = 2;

src/add-ons/accelerants/neomagic/engine/nm_info.c

239

LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));

src/add-ons/accelerants/neomagic/engine/nm_info.c

24

si->ps.curmem_size = 2048;

src/add-ons/accelerants/neomagic/engine/nm_info.c

240

LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));

src/add-ons/accelerants/neomagic/engine/nm_info.c

241

LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));

src/add-ons/accelerants/neomagic/engine/nm_info.c

242

LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));

src/add-ons/accelerants/neomagic/engine/nm_info.c

243

LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));

src/add-ons/accelerants/neomagic/engine/nm_info.c

244

LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));

src/add-ons/accelerants/neomagic/engine/nm_info.c

245

LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));

src/add-ons/accelerants/neomagic/engine/nm_info.c

246

LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));

src/add-ons/accelerants/neomagic/engine/nm_info.c

247

LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));

src/add-ons/accelerants/neomagic/engine/nm_info.c

248

LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));

src/add-ons/accelerants/neomagic/engine/nm_info.c

249

LOG(2,("card memory_size: %dKbytes\n", si->ps.memory_size));

src/add-ons/accelerants/neomagic/engine/nm_info.c

25

si->ps.max_crtc_width = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

250

LOG(2,("card curmem_size: %dbytes\n", si->ps.curmem_size));

src/add-ons/accelerants/neomagic/engine/nm_info.c

251

LOG(2,("card max_crtc_width: %d\n", si->ps.max_crtc_width));

src/add-ons/accelerants/neomagic/engine/nm_info.c

252

LOG(2,("card max_crtc_height: %d\n", si->ps.max_crtc_height));

src/add-ons/accelerants/neomagic/engine/nm_info.c

253

switch (si->ps.panel_type)

src/add-ons/accelerants/neomagic/engine/nm_info.c

26

si->ps.max_crtc_height = 1000;

src/add-ons/accelerants/neomagic/engine/nm_info.c

268

LOG(2,("internal panel width: %d\n", si->ps.panel_width));

src/add-ons/accelerants/neomagic/engine/nm_info.c

269

LOG(2,("internal panel height: %d\n", si->ps.panel_height));

src/add-ons/accelerants/neomagic/engine/nm_info.c

27

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

270

switch (si->ps.outputs)

src/add-ons/accelerants/neomagic/engine/nm_info.c

33

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

34

si->ps.max_system_vco = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

35

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

36

si->ps.max_pixel_vco = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

37

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

38

si->ps.max_dac1_clock = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

39

si->ps.max_dac1_clock_8 = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

40

si->ps.max_dac1_clock_16 = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

41

si->ps.max_dac1_clock_24 = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

42

si->ps.memory_size = 1152;

src/add-ons/accelerants/neomagic/engine/nm_info.c

43

si->ps.curmem_size = 2048;

src/add-ons/accelerants/neomagic/engine/nm_info.c

44

si->ps.max_crtc_width = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

45

si->ps.max_crtc_height = 1000;

src/add-ons/accelerants/neomagic/engine/nm_info.c

46

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

52

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

53

si->ps.max_system_vco = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

54

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

55

si->ps.max_pixel_vco = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

56

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

57

si->ps.max_dac1_clock = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

58

si->ps.max_dac1_clock_8 = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

59

si->ps.max_dac1_clock_16 = 80;

src/add-ons/accelerants/neomagic/engine/nm_info.c

60

si->ps.max_dac1_clock_24 = 65;

src/add-ons/accelerants/neomagic/engine/nm_info.c

61

si->ps.memory_size = 1152;

src/add-ons/accelerants/neomagic/engine/nm_info.c

62

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

63

si->ps.max_crtc_width = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

64

si->ps.max_crtc_height = 1000;

src/add-ons/accelerants/neomagic/engine/nm_info.c

65

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

71

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

72

si->ps.max_system_vco = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

73

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

74

si->ps.max_pixel_vco = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

75

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

76

si->ps.max_dac1_clock = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

77

si->ps.max_dac1_clock_8 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

78

si->ps.max_dac1_clock_16 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

79

si->ps.max_dac1_clock_24 = 70;

src/add-ons/accelerants/neomagic/engine/nm_info.c

80

si->ps.memory_size = 2048;

src/add-ons/accelerants/neomagic/engine/nm_info.c

81

si->ps.curmem_size = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

82

si->ps.max_crtc_width = 1024;

src/add-ons/accelerants/neomagic/engine/nm_info.c

83

si->ps.max_crtc_height = 1000;

src/add-ons/accelerants/neomagic/engine/nm_info.c

84

si->ps.std_engine_clock = 0;

src/add-ons/accelerants/neomagic/engine/nm_info.c

90

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/neomagic/engine/nm_info.c

91

si->ps.max_system_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

92

si->ps.min_system_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

93

si->ps.max_pixel_vco = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

94

si->ps.min_pixel_vco = 11;

src/add-ons/accelerants/neomagic/engine/nm_info.c

95

si->ps.max_dac1_clock = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

96

si->ps.max_dac1_clock_8 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

97

si->ps.max_dac1_clock_16 = 110;

src/add-ons/accelerants/neomagic/engine/nm_info.c

98

si->ps.max_dac1_clock_24 = 90;

src/add-ons/accelerants/neomagic/engine/nm_info.c

99

si->ps.memory_size = 2560;

src/add-ons/accelerants/neomagic/engine/nm_proto.h

16

uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \

src/add-ons/accelerants/neomagic/engine/nm_proto.h

17

uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \

src/add-ons/accelerants/nvidia/Cursor.c

103

if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x);

src/add-ons/accelerants/nvidia/Cursor.c

105

if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y);

src/add-ons/accelerants/nvidia/Cursor.c

109

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/Cursor.c

117

if (x < si->dm.timing.h_display)

src/add-ons/accelerants/nvidia/Cursor.c

119

if (si->cursor.dh_right)

src/add-ons/accelerants/nvidia/Cursor.c

124

si->cursor.dh_right = false;

src/add-ons/accelerants/nvidia/Cursor.c

130

if (!si->cursor.dh_right)

src/add-ons/accelerants/nvidia/Cursor.c

135

si->cursor.dh_right = true;

src/add-ons/accelerants/nvidia/Cursor.c

137

head2_cursor_position((x - si->dm.timing.h_display), y);

src/add-ons/accelerants/nvidia/Cursor.c

149

si->cursor.is_visible = is_visible;

src/add-ons/accelerants/nvidia/Cursor.c

151

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/Cursor.c

169

if (!si->cursor.dh_right)

src/add-ons/accelerants/nvidia/Cursor.c

30

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)

src/add-ons/accelerants/nvidia/Cursor.c

34

si->cursor.width = width;

src/add-ons/accelerants/nvidia/Cursor.c

35

si->cursor.height = height;

src/add-ons/accelerants/nvidia/Cursor.c

36

si->cursor.hot_x = hot_x;

src/add-ons/accelerants/nvidia/Cursor.c

37

si->cursor.hot_y = hot_y;

src/add-ons/accelerants/nvidia/Cursor.c

46

uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */

src/add-ons/accelerants/nvidia/Cursor.c

47

uint16 vds = si->dm.v_display_start; /* the current vertical starting line */

src/add-ons/accelerants/nvidia/Cursor.c

51

if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;

src/add-ons/accelerants/nvidia/Cursor.c

52

if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;

src/add-ons/accelerants/nvidia/Cursor.c

55

si->cursor.x = x;

src/add-ons/accelerants/nvidia/Cursor.c

56

si->cursor.y = y;

src/add-ons/accelerants/nvidia/Cursor.c

63

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/Cursor.c

67

if (x >= ((si->dm.timing.h_display * 2) + hds))

src/add-ons/accelerants/nvidia/Cursor.c

69

hds = ((x - (si->dm.timing.h_display * 2)) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/nvidia/Cursor.c

71

if ((hds + (si->dm.timing.h_display * 2)) > si->dm.virtual_width)

src/add-ons/accelerants/nvidia/Cursor.c

78

if (x >= (si->dm.timing.h_display + hds))

src/add-ons/accelerants/nvidia/Cursor.c

80

hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/nvidia/Cursor.c

82

if ((hds + si->dm.timing.h_display) > si->dm.virtual_width)

src/add-ons/accelerants/nvidia/Cursor.c

90

if (y >= (si->dm.timing.v_display + vds))

src/add-ons/accelerants/nvidia/Cursor.c

91

vds = y - si->dm.timing.v_display + 1;

src/add-ons/accelerants/nvidia/Cursor.c

96

if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))

src/add-ons/accelerants/nvidia/EngineManagment.c

33

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/nvidia/EngineManagment.c

38

if (!si->settings.block_acc) nv_acc_assert_fifo();

src/add-ons/accelerants/nvidia/EngineManagment.c

48

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/nvidia/EngineManagment.c

53

if (!si->settings.block_acc) nv_acc_assert_fifo_dma();

src/add-ons/accelerants/nvidia/EngineManagment.c

66

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/nvidia/EngineManagment.c

73

if (si->settings.block_acc) return;

src/add-ons/accelerants/nvidia/EngineManagment.c

76

if (!si->settings.dma_acc)

src/add-ons/accelerants/nvidia/EngineManagment.c

86

st->counter = si->engine.count;

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

183

if ((si->ps.card_type <= NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

222

if (!si->settings.dma_acc || (si->dm.space == B_CMAP8))

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

235

if (si->acc_mode && !si->settings.block_acc)

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

31

{if(!si->settings.dma_acc) return (void *)x##_PIO; else return (void *)x##_DMA;} \

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

34

if(!si->settings.dma_acc) return (void *)x##_PIO; else return (void *)x##_DMA

src/add-ons/accelerants/nvidia/GetAccelerantHook.c

37

#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

101

if (si->ps.crtc1_screen.have_native_edid && si->ps.crtc2_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

105

if (si->ps.crtc1_screen.aspect < (si->ps.crtc2_screen.aspect - 0.10)) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

108

if (si->ps.crtc1_screen.aspect > (si->ps.crtc2_screen.aspect + 0.10)) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

113

if (si->ps.crtc1_screen.timing.h_display < si->ps.crtc2_screen.timing.h_display)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

115

if (si->ps.crtc1_screen.timing.h_display > si->ps.crtc2_screen.timing.h_display)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

120

if (si->ps.crtc1_screen.timing.h_display == si->ps.crtc2_screen.timing.h_display) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

121

if (si->ps.crtc2_prim)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

130

if (si->ps.crtc1_screen.have_native_edid)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

18

strcpy(adi->name, si->adi.name);

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

19

strcpy(adi->chipset, si->adi.chipset);

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

21

adi->memory = si->ps.memory_size;

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

22

adi->dac_speed = si->ps.max_dac1_clock;

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

32

if (!si->ps.crtc1_screen.have_full_edid && !si->ps.crtc2_screen.have_full_edid) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

44

if (si->ps.crtc1_screen.have_full_edid && si->ps.crtc2_screen.have_full_edid) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

48

if (si->ps.crtc1_screen.aspect < (si->ps.crtc2_screen.aspect - 0.10)) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

49

memcpy(info, &si->ps.crtc1_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

51

if (si->ps.crtc1_screen.aspect > (si->ps.crtc2_screen.aspect + 0.10)) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

52

memcpy(info, &si->ps.crtc2_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

56

if (si->ps.crtc1_screen.timing.h_display < si->ps.crtc2_screen.timing.h_display)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

57

memcpy(info, &si->ps.crtc1_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

58

if (si->ps.crtc1_screen.timing.h_display > si->ps.crtc2_screen.timing.h_display)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

59

memcpy(info, &si->ps.crtc2_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

63

if (si->ps.crtc1_screen.timing.h_display == si->ps.crtc2_screen.timing.h_display) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

64

if (si->ps.crtc2_prim)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

65

memcpy(info, &si->ps.crtc2_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

67

memcpy(info, &si->ps.crtc1_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

73

if (si->ps.crtc1_screen.have_full_edid)

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

74

memcpy(info, &si->ps.crtc1_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

76

memcpy(info, &si->ps.crtc2_screen.full_edid, sizeof(struct edid1_info));

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

86

if (si->ps.crtc1_screen.have_full_edid || si->ps.crtc2_screen.have_full_edid) {

src/add-ons/accelerants/nvidia/GetDeviceInfo.c

91

if (!si->ps.crtc1_screen.have_native_edid && !si->ps.crtc2_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/GetModeInfo.c

102

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/nvidia/GetModeInfo.c

106

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/nvidia/GetModeInfo.c

109

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/nvidia/GetModeInfo.c

112

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/nvidia/GetModeInfo.c

116

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/nvidia/GetModeInfo.c

125

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/nvidia/GetModeInfo.c

129

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/nvidia/GetModeInfo.c

132

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/nvidia/GetModeInfo.c

135

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/nvidia/GetModeInfo.c

139

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/nvidia/GetModeInfo.c

159

if (si->ps.int_assigned)

src/add-ons/accelerants/nvidia/GetModeInfo.c

160

return si->vblank;

src/add-ons/accelerants/nvidia/GetModeInfo.c

23

*current_mode = si->dm;

src/add-ons/accelerants/nvidia/GetModeInfo.c

33

*afb = si->fbc;

src/add-ons/accelerants/nvidia/GetModeInfo.c

54

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/GetModeInfo.c

57

*low = ((si->ps.min_video_vco * 1000) / 16);

src/add-ons/accelerants/nvidia/GetModeInfo.c

65

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/nvidia/GetModeInfo.c

69

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/nvidia/GetModeInfo.c

72

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/nvidia/GetModeInfo.c

76

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/nvidia/GetModeInfo.c

80

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/nvidia/GetModeInfo.c

90

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/GetModeInfo.c

93

*low = ((si->ps.min_pixel_vco * 1000) / 16);

src/add-ons/accelerants/nvidia/GetModeInfo.c

97

if (!si->ps.crtc2_prim)

src/add-ons/accelerants/nvidia/InitAccelerant.c

121

if (si->accelerant_in_use)

src/add-ons/accelerants/nvidia/InitAccelerant.c

150

si->cursor.width = 16;

src/add-ons/accelerants/nvidia/InitAccelerant.c

151

si->cursor.height = 16;

src/add-ons/accelerants/nvidia/InitAccelerant.c

152

si->cursor.hot_x = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

153

si->cursor.hot_y = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

154

si->cursor.x = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

155

si->cursor.y = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

156

si->cursor.dh_right = false;

src/add-ons/accelerants/nvidia/InitAccelerant.c

165

if (si->settings.hardcursor) pointer_reservation = 2048;

src/add-ons/accelerants/nvidia/InitAccelerant.c

167

si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);

src/add-ons/accelerants/nvidia/InitAccelerant.c

168

si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);

src/add-ons/accelerants/nvidia/InitAccelerant.c

171

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

173

si->engine.threeD.clones = 0;

src/add-ons/accelerants/nvidia/InitAccelerant.c

175

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/InitAccelerant.c

176

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/nvidia/InitAccelerant.c

178

INIT_BEN(si->overlay.lock);

src/add-ons/accelerants/nvidia/InitAccelerant.c

182

si->overlay.myBuffer[cnt].buffer = NULL;

src/add-ons/accelerants/nvidia/InitAccelerant.c

183

si->overlay.myBuffer[cnt].buffer_dma = NULL;

src/add-ons/accelerants/nvidia/InitAccelerant.c

187

si->overlay.myToken = NULL;

src/add-ons/accelerants/nvidia/InitAccelerant.c

190

si->overlay.active = false;

src/add-ons/accelerants/nvidia/InitAccelerant.c

194

if (si->ps.secondary_head) head2_cursor_init();

src/add-ons/accelerants/nvidia/InitAccelerant.c

198

if (si->ps.secondary_head) head2_cursor_hide();

src/add-ons/accelerants/nvidia/InitAccelerant.c

201

si->dpms_flags = B_DPMS_ON;

src/add-ons/accelerants/nvidia/InitAccelerant.c

206

si->dm.flags = TV_PRIMARY;

src/add-ons/accelerants/nvidia/InitAccelerant.c

211

si->engine.threeD.mode_changing = true;

src/add-ons/accelerants/nvidia/InitAccelerant.c

213

si->engine.threeD.newmode = 0xffffffff;

src/add-ons/accelerants/nvidia/InitAccelerant.c

216

si->haiku_prefs_used = false;

src/add-ons/accelerants/nvidia/InitAccelerant.c

217

si->Haiku_switch_head = false;

src/add-ons/accelerants/nvidia/InitAccelerant.c

222

si->accelerant_in_use = true;

src/add-ons/accelerants/nvidia/InitAccelerant.c

305

if (!(si->accelerant_in_use))

src/add-ons/accelerants/nvidia/InitAccelerant.c

314

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/InitAccelerant.c

315

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/nvidia/InitAccelerant.c

317

setup_virtualized_heads(si->ps.crtc2_prim);

src/add-ons/accelerants/nvidia/InitAccelerant.c

325

si->mode_area

src/add-ons/accelerants/nvidia/InitAccelerant.c

35

shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS,

src/add-ons/accelerants/nvidia/InitAccelerant.c

356

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/nvidia/InitAccelerant.c

357

DELETE_BEN(si->overlay.lock);

src/add-ons/accelerants/nvidia/InitAccelerant.c

360

si->accelerant_in_use = false;

src/add-ons/accelerants/nvidia/InitAccelerant.c

43

si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead, si->settings.force_pci));

src/add-ons/accelerants/nvidia/InitAccelerant.c

45

si->settings.dumprom, si->settings.unhide_fw, si->settings.pgm_panel, si->settings.dma_acc, si->settings.tv_output, si->settings.vga_on_tv));

src/add-ons/accelerants/nvidia/InitAccelerant.c

47

si->settings.force_sync, si->settings.gpu_clk, si->settings.ram_clk, si->settings.force_ws, si->settings.block_acc, si->settings.check_edid));

src/add-ons/accelerants/nvidia/InitAccelerant.c

51

if (si->use_clone_bugfix)

src/add-ons/accelerants/nvidia/InitAccelerant.c

55

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/nvidia/InitAccelerant.c

61

B_READ_AREA | B_WRITE_AREA, si->regs_area);

src/add-ons/accelerants/nvidia/InitAccelerant.c

87

si = 0;

src/add-ons/accelerants/nvidia/Overlay.c

101

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/Overlay.c

104

si->overlay.myBuffer[offset].width = ((width + 0x000f) & ~0x000f);

src/add-ons/accelerants/nvidia/Overlay.c

109

si->overlay.myBuffer[offset].width = ((width + 0x001f) & ~0x001f);

src/add-ons/accelerants/nvidia/Overlay.c

111

si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;

src/add-ons/accelerants/nvidia/Overlay.c

115

if (si->overlay.myBuffer[offset].width > 4088)

src/add-ons/accelerants/nvidia/Overlay.c

120

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

130

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

137

switch (si->ps.card_arch) {

src/add-ons/accelerants/nvidia/Overlay.c

143

if (si->overlay.myBuffer[offset].width > 1024) {

src/add-ons/accelerants/nvidia/Overlay.c

147

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

155

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

163

if (si->overlay.myBuffer[offset].width > 1920) {

src/add-ons/accelerants/nvidia/Overlay.c

167

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

175

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

182

si->overlay.myBufInfo[offset].slopspace = si->overlay.myBuffer[offset].width - width;

src/add-ons/accelerants/nvidia/Overlay.c

184

si->overlay.myBuffer[offset].space = cs;

src/add-ons/accelerants/nvidia/Overlay.c

185

si->overlay.myBuffer[offset].height = height;

src/add-ons/accelerants/nvidia/Overlay.c

211

adress2 = (((uintptr_t)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */

src/add-ons/accelerants/nvidia/Overlay.c

212

(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */

src/add-ons/accelerants/nvidia/Overlay.c

216

oldsize = si->overlay.myBufInfo[offset].size;

src/add-ons/accelerants/nvidia/Overlay.c

217

si->overlay.myBufInfo[offset].size

src/add-ons/accelerants/nvidia/Overlay.c

218

= si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;

src/add-ons/accelerants/nvidia/Overlay.c

231

adress = (((uintptr_t)((uint8*)si->framebuffer)) + si->ps.memory_size);

src/add-ons/accelerants/nvidia/Overlay.c

234

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/Overlay.c

241

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/nvidia/Overlay.c

249

temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));

src/add-ons/accelerants/nvidia/Overlay.c

254

si->overlay.myBufInfo[offset].size += (temp32 - (temp32 & 0xfffffff0));

src/add-ons/accelerants/nvidia/Overlay.c

275

if (si->overlay.myBuffer[cnt].buffer != NULL)

src/add-ons/accelerants/nvidia/Overlay.c

278

if (si->overlay.myBufInfo[offset].size <= oldsize)

src/add-ons/accelerants/nvidia/Overlay.c

282

adress -= (oldsize - si->overlay.myBufInfo[offset].size);

src/add-ons/accelerants/nvidia/Overlay.c

283

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/nvidia/Overlay.c

294

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/nvidia/Overlay.c

297

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

312

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

317

si->overlay.myBuffer[offset].buffer = (void *) adress;

src/add-ons/accelerants/nvidia/Overlay.c

320

adress = (((uintptr_t)((uint8*)si->framebuffer_pci)) + si->ps.memory_size);

src/add-ons/accelerants/nvidia/Overlay.c

323

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/Overlay.c

330

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/nvidia/Overlay.c

333

si->overlay.myBuffer[offset].buffer_dma = (void *) adress;

src/add-ons/accelerants/nvidia/Overlay.c

336

(uint8*)si->overlay.myBuffer[offset].buffer,

src/add-ons/accelerants/nvidia/Overlay.c

337

(uint8*)si->overlay.myBuffer[offset].buffer_dma, cs));

src/add-ons/accelerants/nvidia/Overlay.c

338

LOG(4, ("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));

src/add-ons/accelerants/nvidia/Overlay.c

341

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

343

return &si->overlay.myBuffer[offset];

src/add-ons/accelerants/nvidia/Overlay.c

349

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

366

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/nvidia/Overlay.c

372

si->overlay.myBuffer[offset].buffer = NULL;

src/add-ons/accelerants/nvidia/Overlay.c

373

si->overlay.myBuffer[offset].buffer_dma = NULL;

src/add-ons/accelerants/nvidia/Overlay.c

413

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/nvidia/Overlay.c

425

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/Overlay.c

479

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/Overlay.c

493

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/nvidia/Overlay.c

524

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

527

if (si->overlay.myToken == NULL)

src/add-ons/accelerants/nvidia/Overlay.c

532

si->overlay.myToken = &tmpToken;

src/add-ons/accelerants/nvidia/Overlay.c

535

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

537

return si->overlay.myToken;

src/add-ons/accelerants/nvidia/Overlay.c

545

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

556

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/nvidia/Overlay.c

571

si->overlay.myToken = NULL;

src/add-ons/accelerants/nvidia/Overlay.c

614

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/nvidia/Overlay.c

627

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/nvidia/Overlay.c

81

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/nvidia/Overlay.c

83

LOG(4, ("Overlay: cardRAM_start = $%p\n", (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/Overlay.c

84

LOG(4, ("Overlay: cardRAM_start_DMA = $%p\n", (uint8*)si->framebuffer_pci));

src/add-ons/accelerants/nvidia/Overlay.c

85

LOG(4, ("Overlay: cardRAM_size = %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/nvidia/Overlay.c

90

if (si->overlay.myBuffer[offset].buffer == NULL) break;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

106

if (si->Haiku_switch_head)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

153

if (!si->haiku_prefs_used)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

155

si->haiku_prefs_used = true;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

170

if (si->Haiku_switch_head)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

177

si->Haiku_switch_head = mode->timing.flags != 0;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

180

SET_DISPLAY_MODE(&si->dm);

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

254

if (si->haiku_prefs_used) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

274

if (!si->ps.tvout

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

283

switch (si->ps.monitors) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

286

if (target_aspect > 1.34 && !si->settings.force_ws) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

293

if (si->ps.crtc1_screen.aspect < (target_aspect - 0.10)) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

300

if (si->ps.crtc2_screen.aspect < (target_aspect - 0.10)) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

310

if ((si->ps.crtc1_screen.aspect < (target_aspect - 0.10)) ||

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

311

(si->ps.crtc2_screen.aspect < (target_aspect - 0.10))) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

321

if (si->settings.check_edid) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

326

if (si->ps.crtc1_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

327

if ((target->timing.h_display - 2) > si->ps.crtc1_screen.timing.h_display

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

328

|| target->timing.v_display > si->ps.crtc1_screen.timing.v_display) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

333

if (si->ps.crtc2_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

334

if ((target->timing.h_display - 2) > si->ps.crtc2_screen.timing.h_display

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

335

|| target->timing.v_display > si->ps.crtc2_screen.timing.v_display) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

420

if (si->settings.hardcursor)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

425

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

431

if (row_bytes * target->virtual_height > si->ps.memory_size - mem_reservation) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

432

target->virtual_height = (si->ps.memory_size - mem_reservation) / row_bytes;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

466

max_vclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

471

max_vclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

475

max_vclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

479

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

484

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

491

if (si->ps.secondary_head && target->timing.pixel_clock <= (max_vclk * 1000)) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

495

if (si->ps.memory_size - mem_reservation

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

501

if (si->ps.memory_size - mem_reservation

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

506

if (si->ps.memory_size - mem_reservation

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

518

if (si->ps.tvout && BT_check_tvmode(*target))

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

527

if (!si->ps.secondary_head)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

535

if (si->settings.hardcursor)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

539

if (si->ps.card_type <= NV40 || si->ps.card_type == NV45)

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

564

LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

565

return si->mode_count;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

576

memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

601

dst[si->mode_count] = *src;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

603

dst[si->mode_count].space = low.space = high.space = spaces[j];

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

610

if (PROPOSE_DISPLAY_MODE(&dst[si->mode_count], &low, &high) == B_OK) {

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

612

si->mode_count++;

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

633

si->mode_area = my_mode_list_area = create_area("NV accelerant mode info",

src/add-ons/accelerants/nvidia/ProposeDisplayMode.c

642

si->mode_count = 0;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

185

si->interlaced_tv_mode = false;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

215

if (si->ps.tvout && (target2.flags & TV_BITS)) BT_setmode(target2);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

222

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

279

if (si->ps.tvout && (target.flags & TV_BITS)) BT_setmode(target);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

285

si->dm = target;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

289

if (si->ps.secondary_head) nv_crtc2_update_fifo();

src/add-ons/accelerants/nvidia/SetDisplayMode.c

295

if (!si->settings.block_acc) {

src/add-ons/accelerants/nvidia/SetDisplayMode.c

296

if (!si->settings.dma_acc)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

307

si->engine.threeD.mem_low = si->fbc.bytes_per_row * si->dm.virtual_height;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

308

if (si->settings.hardcursor) si->engine.threeD.mem_low += 2048;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

313

si->engine.threeD.mem_high = si->ps.memory_size - 1;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

316

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

317

si->engine.threeD.mem_high -= PRE_NV40_OFFSET;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

319

si->engine.threeD.mem_high -= NV40_PLUS_OFFSET;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

321

si->engine.threeD.mem_high -= (MAXBUFFERS * 1024 * 1024 * 2); /* see overlay.c file */

src/add-ons/accelerants/nvidia/SetDisplayMode.c

324

SET_DPMS_MODE(si->dpms_flags);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

332

si->engine.threeD.mode_changing = false;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

360

switch(si->dm.space)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

380

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

384

if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

388

if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

392

if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

396

si->dm.h_display_start = h_display_start;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

397

si->dm.v_display_start = v_display_start;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

401

startadd = v_display_start * si->fbc.bytes_per_row;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

403

startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

404

startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

408

if (si->ps.secondary_head) head2_interrupt_enable(false);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

410

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

439

if (si->dm.space != B_CMAP8) return;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

441

r=si->color_data;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

454

if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

464

if (si->ps.secondary_head) head2_interrupt_enable(false);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

469

si->dpms_flags = dpms_flags;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

499

if (si->dm.flags & TV_BITS)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

504

if (si->dm.flags & TV_PRIMARY)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

508

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

510

if (!(si->settings.vga_on_tv))

src/add-ons/accelerants/nvidia/SetDisplayMode.c

538

if (!(si->settings.vga_on_tv))

src/add-ons/accelerants/nvidia/SetDisplayMode.c

54

si->engine.threeD.mode_changing = true;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

555

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

557

if (!(si->settings.vga_on_tv))

src/add-ons/accelerants/nvidia/SetDisplayMode.c

56

si->engine.threeD.newmode = 0xffffffff;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

571

if (!(si->settings.vga_on_tv))

src/add-ons/accelerants/nvidia/SetDisplayMode.c

588

if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS))

src/add-ons/accelerants/nvidia/SetDisplayMode.c

59

si->engine.threeD.clones = 0x00000000;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

590

if (si->dm.flags & TV_BITS)

src/add-ons/accelerants/nvidia/SetDisplayMode.c

609

return si->dpms_flags;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

63

if (si->ps.secondary_head) head2_interrupt_enable(false);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

66

if (si->ps.tvout) BT_stop_tvout();

src/add-ons/accelerants/nvidia/SetDisplayMode.c

70

if (si->ps.secondary_head) head2_dpms(false, false, false, true);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

71

if (si->ps.tvout) BT_dpms(false);

src/add-ons/accelerants/nvidia/SetDisplayMode.c

74

startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/nvidia/SetDisplayMode.c

77

nv_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1009

si->engine.fifo.handle[0] = NV_ROP5_SOLID;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1010

si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1011

si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1012

si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1013

si->engine.fifo.handle[4] = NV_IMAGE_BLIT;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1014

si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1015

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1017

si->engine.fifo.handle[6] = NV1_RENDER_SOLID_LIN;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1018

si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1023

si->engine.fifo.ch_ptr[cnt] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1028

si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1032

ACCW(FIFO_CH0, (0x80000000 | si->engine.fifo.handle[0])); /* Raster OPeration */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1033

ACCW(FIFO_CH1, (0x80000000 | si->engine.fifo.handle[1])); /* Clip */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1034

ACCW(FIFO_CH2, (0x80000000 | si->engine.fifo.handle[2])); /* Pattern */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1035

ACCW(FIFO_CH3, (0x80000000 | si->engine.fifo.handle[3])); /* 2D Surface */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1036

ACCW(FIFO_CH4, (0x80000000 | si->engine.fifo.handle[4])); /* Blit */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1037

ACCW(FIFO_CH5, (0x80000000 | si->engine.fifo.handle[5])); /* Bitmap */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1038

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1040

ACCW(FIFO_CH6, (0x80000000 | si->engine.fifo.handle[6])); /* Line (not used) */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1041

ACCW(FIFO_CH7, (0x80000000 | si->engine.fifo.handle[7])); /* Textured Triangle (3D only) */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

105

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1066

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1316

if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] ||

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1317

!si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] ||

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1318

!si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] ||

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1319

!si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] ||

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1320

!si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT])

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1328

si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1329

si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1330

si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1331

si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1332

si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1335

si->engine.fifo.handle[0] = NV_ROP5_SOLID;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1336

si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1337

si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1338

si->engine.fifo.handle[4] = NV_IMAGE_BLIT;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1339

si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1344

si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1349

ACCW(FIFO_CH0, (0x80000000 | si->engine.fifo.handle[0])); /* Raster OPeration */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1350

ACCW(FIFO_CH1, (0x80000000 | si->engine.fifo.handle[1])); /* Clip */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1351

ACCW(FIFO_CH2, (0x80000000 | si->engine.fifo.handle[2])); /* Pattern */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1352

ACCW(FIFO_CH4, (0x80000000 | si->engine.fifo.handle[4])); /* Blit */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1353

ACCW(FIFO_CH5, (0x80000000 | si->engine.fifo.handle[5])); /* Bitmap */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1358

&(regs[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1361

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1364

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1367

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLIT]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1370

&(regs[(si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

204

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

270

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

276

ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

326

ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */

src/add-ons/accelerants/nvidia/engine/nv_acc.c

346

if(si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

368

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

381

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

397

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

429

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

445

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

525

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

531

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

537

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

543

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

550

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

565

ACCW(BLIMIT0, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

566

ACCW(BLIMIT1, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

567

ACCW(BLIMIT2, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

568

ACCW(BLIMIT3, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

569

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

573

ACCW(NV10_BLIMIT4, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

574

ACCW(NV10_BLIMIT5, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

576

if (si->ps.card_arch >= NV20A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

578

if ((si->ps.card_type > NV40) && (si->ps.card_type != NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc.c

580

ACCW(NV40P_BLIMIT6, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

581

ACCW(NV40P_BLIMIT7, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

586

ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

587

ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

588

if (si->ps.card_type < NV40)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

590

ACCW(NV20_BLIMIT8, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

591

ACCW(NV20_BLIMIT9, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

601

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

619

if (si->ps.card_arch != NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

640

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

645

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

653

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

661

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

690

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

713

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

719

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

740

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

766

if (si->ps.card_arch >= NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

775

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

781

ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

783

ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

785

ACCW(OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

787

ACCW(OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

788

ACCW(OFFSET4, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

789

ACCW(OFFSET5, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

793

ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

795

ACCW(PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

797

ACCW(PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

799

ACCW(PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

800

ACCW(PITCH4, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

805

ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

806

ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

807

ACCW(NV20_OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

808

ACCW(NV20_OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

811

ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

812

ACCW(NV20_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

813

ACCW(NV20_PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

814

ACCW(NV20_PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

817

if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc.c

820

ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

821

ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

827

ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

828

ACCW(NV20_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

829

ACCW(NV20_PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

830

ACCW(NV20_PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

835

ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

836

ACCW(NV40P_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

840

ACCW(NV40P_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

841

ACCW(NV40P_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));

src/add-ons/accelerants/nvidia/engine/nv_acc.c

847

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

860

if (si->ps.card_arch >= NV20A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

862

if ((si->ps.card_type > NV40) && (si->ps.card_type != NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc.c

873

if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc.c

903

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

934

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc.c

961

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1027

si->engine.fifo.handle[0] = NV_ROP5_SOLID;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1028

si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1029

si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1030

si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1031

si->engine.fifo.handle[4] = NV_IMAGE_BLIT;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1032

si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1033

si->engine.fifo.handle[6] = NV4_CONTEXT_SURFACES_ARGB_ZS;//NV1_RENDER_SOLID_LIN;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1034

si->engine.fifo.handle[7] = NV4_DX5_TEXTURE_TRIANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1038

si->engine.fifo.ch_ptr[cnt] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1045

si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])]

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1050

if (si->ps.card_arch >= NV40A) //main mem DMA buf on pre-NV40

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1052

si->dma_buffer = (void *)((char *)si->framebuffer

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1053

+ ((si->ps.memory_size - 1) & 0xffff8000));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1055

LOG(4, ("ACC_DMA: command buffer is at adress $%p\n", si->dma_buffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1057

si->engine.dma.put = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1059

si->engine.dma.current = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1066

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1067

si->engine.dma.max = ((1 * 1024 * 1024) >> 2) - 1;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1069

si->engine.dma.max = 8192 - 1;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1071

si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1075

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1084

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1086

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1088

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1090

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1092

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1094

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1095

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1098

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1100

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1104

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1129

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = surf_depth; /* Format */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1131

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1132

((si->fbc.bytes_per_row & 0x0000ffff) | (si->fbc.bytes_per_row << 16)); /* Pitch */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1134

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1135

((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetSource */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1136

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1137

((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1143

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1149

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1156

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* SetShape: 0 = 8x8, 1 = 64x1, 2 = 1x64 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1158

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetColor0 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1159

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetColor1 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1160

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetPattern[0] */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1161

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetPattern[1] */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1172

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

131

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

139

if ((si->ps.card_type <= NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1421

if (si->engine.dma.current != si->engine.dma.put)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1423

si->engine.dma.put = si->engine.dma.current;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1425

if (si->ps.card_arch < NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1435

dummy = *((volatile uint32 *)(si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1445

NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT) = (si->engine.dma.put << 2);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1463

while ((si->engine.dma.free < cmd_size) && (cnt < 10000) && (err < 3))

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1481

if (si->engine.dma.put >= dmaget)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1486

si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1488

if (si->engine.dma.free < cmd_size)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

149

ACCW(NV10_FBTIL0ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1492

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x20000000;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1495

si->engine.dma.current = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

150

ACCW(NV10_FBTIL1ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1504

si->engine.dma.free = dmaget - si->engine.dma.current;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

151

ACCW(NV10_FBTIL2ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1516

if (si->engine.dma.free < 256)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1517

si->engine.dma.free = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1519

si->engine.dma.free -= 256;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

152

ACCW(NV10_FBTIL3ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1528

si->engine.dma.free = dmaget - si->engine.dma.current;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

153

ACCW(NV10_FBTIL4ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

154

ACCW(NV10_FBTIL5ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1540

if (si->engine.dma.free < 256)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1541

si->engine.dma.free = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1543

si->engine.dma.free -= 256;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

155

ACCW(NV10_FBTIL6ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

156

ACCW(NV10_FBTIL7ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1574

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = ((size << 18) |

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1575

((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1578

si->engine.dma.free -= (size + 1);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1584

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = ((1 << 18) | ch);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1586

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = (0x80000000 | handle);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1589

si->engine.dma.free -= 2;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1599

if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1600

!si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1601

!si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1602

!si->engine.fifo.ch_ptr[NV4_SURFACE] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1603

!si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1604

!si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT] ||

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1605

!si->engine.fifo.ch_ptr[NV_SCALED_IMAGE_FROM_MEMORY])

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1610

si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1611

si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1612

si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1613

si->engine.fifo.ch_ptr[si->engine.fifo.handle[3]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1614

si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1615

si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1616

si->engine.fifo.ch_ptr[si->engine.fifo.handle[6]] = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1619

si->engine.fifo.handle[0] = NV_ROP5_SOLID;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1620

si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1621

si->engine.fifo.handle[2] = NV_IMAGE_PATTERN;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1622

si->engine.fifo.handle[3] = NV4_SURFACE;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1623

si->engine.fifo.handle[4] = NV_IMAGE_BLIT;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1624

si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1625

si->engine.fifo.handle[6] = NV_SCALED_IMAGE_FROM_MEMORY;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1632

si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1641

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1643

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1645

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1647

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1649

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1651

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1653

nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1688

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1708

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1710

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1712

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1724

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

173

ACCW(NV41_FBTIL0ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1739

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

174

ACCW(NV41_FBTIL1ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

175

ACCW(NV41_FBTIL2ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

176

ACCW(NV41_FBTIL3ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

177

ACCW(NV41_FBTIL4ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1773

if (si->dm.space == B_RGB15_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1779

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

178

ACCW(NV41_FBTIL5ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1783

if (si->ps.card_type != NV04)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1789

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

179

ACCW(NV41_FBTIL6ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1791

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000003; /* SetOperation */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1799

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

180

ACCW(NV41_FBTIL7ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1804

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

181

ACCW(NV41_FBTIL8ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

182

ACCW(NV41_FBTIL9ED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1823

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0; /* SourceOrg */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1825

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1827

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

183

ACCW(NV41_FBTILAED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1830

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1833

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1835

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

184

ACCW(NV41_FBTILBED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1844

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1849

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1850

(si->fbc.bytes_per_row | (1 << 16) | (1 << 24)); /* SourcePitch */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1852

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1853

((uint32)((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)) +

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1854

(list[i].src_top * si->fbc.bytes_per_row) + (list[i].src_left * bpp); /* Offset */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1859

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

186

if (si->ps.card_type >= G70)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1871

if (si->dm.space == B_RGB15_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1877

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000004; /* Format */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1885

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

191

ACCW(G70_FBTILCED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

192

ACCW(G70_FBTILDED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

193

ACCW(G70_FBTILEED, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1938

if (si->dm.space == B_RGB15_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1944

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1948

if (si->ps.card_type != NV04)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1954

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1956

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000003; /* SetOperation */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1964

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1969

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1988

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1990

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1994

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

1996

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2005

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2010

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2014

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2015

(uint32)((uint8*)config->buffer - (uint8*)si->framebuffer +

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2028

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2030

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2038

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2052

if (si->dm.space == B_RGB15_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2058

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000004; /* Format */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2066

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2081

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2084

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = colorIndex; /* Color1A */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2103

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2105

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2118

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2133

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2136

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = colorIndex; /* Color1A */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2155

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2157

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2169

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2184

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x55; /* SetRop5 */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2187

((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

219

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2206

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2208

((uint32*)(si->dma_buffer))[si->engine.dma.current++] =

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

2221

si->engine.threeD.reload = 0xffffffff;

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

284

if (si->ps.card_type == NV15)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

299

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

305

ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

366

ACCW(PR_CTX2_E, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

377

ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

399

if(si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

413

if (si->ps.card_type >= NV11)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

432

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

446

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

462

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

48

while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET) != (si->engine.dma.put << 2)) &&

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

491

if (si->ps.card_type == NV15)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

501

if (si->engine.agp_mode)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

516

ACCW(PR_CTX2_C, (((uintptr_t)((uint8 *)(si->dma_buffer_pci))) | 0x00000002));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

526

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

529

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

537

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

545

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

554

if (si->ps.card_arch < NV30A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

567

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

596

ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

597

ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

599

ACCW(BLIMIT0, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

600

ACCW(BLIMIT1, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

630

if (si->ps.card_arch == NV10A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

652

ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

653

ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

655

ACCW(BLIMIT0, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

656

ACCW(BLIMIT1, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

665

if (si->ps.card_arch >= NV20A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

667

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

686

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

766

if (si->ps.card_type < NV25)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

800

if ((si->ps.card_type <= NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

816

if (si->ps.card_type >= G70)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

838

if (si->ps.card_type != NV44)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

848

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

850

if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

859

ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

860

ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

862

ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

863

ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

870

if (si->ps.card_type >= G70)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

885

ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

886

ACCW(NV40P_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

888

ACCW(NV40P_BLIMIT6, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

889

ACCW(NV40P_BLIMIT7, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

908

ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

909

ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

911

ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

912

ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

933

if (si->ps.card_type >= NV11)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

935

ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

936

ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1);

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

950

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

964

if (si->ps.card_arch >= NV40A)

src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c

99

if (si->ps.card_arch < NV20A)

src/add-ons/accelerants/nvidia/engine/nv_agp.c

104

if (si->settings.force_pci || !enable_agp) {

src/add-ons/accelerants/nvidia/engine/nv_agp.c

127

si->engine.agp_mode = true;

src/add-ons/accelerants/nvidia/engine/nv_agp.c

24

si->engine.agp_mode = false;

src/add-ons/accelerants/nvidia/engine/nv_agp.c

29

if (si->settings.unhide_fw) {

src/add-ons/accelerants/nvidia/engine/nv_agp.c

73

if (nai.agpi.device_id == si->device_id

src/add-ons/accelerants/nvidia/engine/nv_agp.c

74

&& nai.agpi.vendor_id == si->vendor_id

src/add-ons/accelerants/nvidia/engine/nv_agp.c

75

&& nai.agpi.bus == si->bus

src/add-ons/accelerants/nvidia/engine/nv_agp.c

76

&& nai.agpi.device == si->device

src/add-ons/accelerants/nvidia/engine/nv_agp.c

77

&& nai.agpi.function == si->function) {

src/add-ons/accelerants/nvidia/engine/nv_bes.c

102

temp1 = (si->overlay.ow.h_start - crtc_hstart) & 0x7ff;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

108

if (si->overlay.ow.width < 2)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

115

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

122

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

130

temp2 = ((uint16)(si->overlay.ow.h_start + si->overlay.ow.width - crtc_hstart - 1)) & 0x7ff;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

141

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

148

if (si->overlay.ow.v_start >= (crtc_vend - 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

156

temp1 = (si->overlay.ow.v_start - crtc_vstart) & 0x7ff;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

162

if (si->overlay.ow.height < 2)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

169

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) > (crtc_vend - 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

176

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

184

temp2 = ((uint16)(si->overlay.ow.v_start + si->overlay.ow.height - crtc_vstart - 1)) & 0x7ff;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

206

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

210

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

213

moi->hsrcstv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

218

moi->hsrcstv += (crtc_hstart - si->overlay.ow.h_start);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

224

moi->hsrcstv *= si->overlay.h_ifactor;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

227

moi->hsrcstv += ((uint32)si->overlay.my_ov.h_start) << 16;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

238

moi->a1orgv = (uintptr_t)((vuint32 *)si->overlay.ob.buffer);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

239

moi->a1orgv -= (uintptr_t)((vuint32 *)si->framebuffer);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

252

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

256

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

260

moi->v1srcstv = (si->overlay.ow.height - 2) * si->overlay.v_ifactor;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

263

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

264

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

270

moi->v1srcstv = (crtc_vstart - si->overlay.ow.v_start) * si->overlay.v_ifactor;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

273

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

274

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

279

moi->v1srcstv += (((uint32)si->overlay.my_ov.v_start) << 16);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

280

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

282

moi->a1orgv += (si->overlay.my_ov.v_start * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

306

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

31

if (!si->overlay.active) return;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

354

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

362

si->overlay.crtc = !si->crtc_switch_mode;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

370

si->overlay.crtc = si->crtc_switch_mode;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

382

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

412

BESW(NV10_0MEMMASK, (si->ps.memory_size - 1));

src/add-ons/accelerants/nvidia/engine/nv_bes.c

45

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

463

if (my_ov.h_start > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

464

my_ov.h_start = ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

465

if (((my_ov.h_start + my_ov.width) - 1) > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

466

my_ov.width = ((((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1) - my_ov.h_start) + 1);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

47

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

476

si->overlay.ow = *ow;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

477

si->overlay.ob = *ob;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

478

si->overlay.my_ov = my_ov;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

485

(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));

src/add-ons/accelerants/nvidia/engine/nv_bes.c

51

if ((si->overlay.ow.h_start + (si->overlay.ow.width / 2)) <

src/add-ons/accelerants/nvidia/engine/nv_bes.c

52

(si->dm.h_display_start + si->dm.timing.h_display))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

525

si->overlay.h_ifactor = ifactor;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

53

nv_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

536

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

55

nv_bes_to_crtc(!si->crtc_switch_mode);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

551

if ((hiscalv > (2 << 16)) && (si->ps.card_type != NV31))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

559

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

58

nv_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/nvidia/engine/nv_bes.c

618

si->overlay.v_ifactor = ifactor;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

628

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

643

if ((viscalv > (2 << 16)) && (si->ps.card_type != NV31))

src/add-ons/accelerants/nvidia/engine/nv_bes.c

65

crtc_hstart = si->dm.h_display_start;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

651

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

67

if (si->overlay.crtc)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

69

crtc_hstart += si->dm.timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

702

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

73

crtc_hend = crtc_hstart + si->dm.timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

74

crtc_vstart = si->dm.v_display_start;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

751

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

76

crtc_vend = crtc_vstart + si->dm.timing.v_display;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

822

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

854

si->overlay.active = true;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

861

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

87

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/nvidia/engine/nv_bes.c

873

si->overlay.active = false;

src/add-ons/accelerants/nvidia/engine/nv_bes.c

94

if (si->overlay.ow.h_start >= (crtc_hend - 1))

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1010

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1021

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1046

if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more...

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1051

if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more...

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1058

if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more...

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1063

if (si->ps.tv_encoder.type >= CX25870) hoffset +=8; //if CX shift picture right some more...

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1067

if (si->ps.tv_encoder.type >= CX25870)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1082

if (si->ps.tv_encoder.type >= CX25870)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1097

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1098

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1099

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1119

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1128

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1129

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

113

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1130

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1140

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1146

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1147

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1148

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1163

buffer[0] = si->ps.tv_encoder.adress + RD;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1166

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1167

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 1);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1173

i2c_readbuffer(si->ps.tv_encoder.bus, buffer, 1);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1174

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1187

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1193

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1194

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1195

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

120

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

121

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1218

if (si->ps.tv_encoder.type <= BT869) //BT...

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

122

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1229

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1235

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1236

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1237

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1249

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1255

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1256

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1257

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1268

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1276

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1277

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1278

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1302

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1318

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1319

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, 3);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1320

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1416

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1433

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1441

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1455

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1463

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1477

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1486

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1500

if (si->ps.card_type == NV05M64)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1518

if (si->ps.tv_encoder.type <= BT869)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1540

if (si->ps.tv_encoder.type <= BT869)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1616

if (si->dm.flags & TV_PRIMARY)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1618

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1625

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_SWITCH)

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

169

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

1721

BT_setup_output(monstat, (uint8)(si->settings.tv_output), ffilter);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

178

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

179

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

180

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

186

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

188

i2c_writebyte(si->ps.tv_encoder.bus, si->ps.tv_encoder.adress + RD);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

194

id = i2c_readbyte(si->ps.tv_encoder.bus, true);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

195

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

209

si->ps.tvout = true;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

210

si->ps.tv_encoder.type = BT868 + type;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

211

si->ps.tv_encoder.version = id & 0x1f;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

220

bool *i2c_bus = &(si->ps.i2c_bus0);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

231

si->ps.tv_encoder.adress = PRADR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

232

si->ps.tv_encoder.bus = bus;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

240

si->ps.tv_encoder.adress = SCADR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

241

si->ps.tv_encoder.bus = bus;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

276

si->ps.tv_encoder.bus, si->ps.tv_encoder.adress));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

291

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

330

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

331

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

332

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

349

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

388

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

389

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

390

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

407

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

446

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

447

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

448

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

465

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

504

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

505

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

506

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

523

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

562

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

563

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

564

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

581

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

599

if (si->ps.tv_encoder.type >= CX25870)//set CX value

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

662

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

663

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

664

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

681

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

699

if (si->ps.tv_encoder.type >= CX25870)//set CX value

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

720

if (si->ps.tv_encoder.type >= CX25870)//set CX value

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

730

if (si->ps.tv_encoder.type >= CX25870)//set CX value

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

772

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

773

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

774

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

791

buffer[0] = si->ps.tv_encoder.adress + WR; //issue I2C write command

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

812

if (si->ps.tv_encoder.type >= CX25870)//set CX value

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

866

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

867

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

868

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

885

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

894

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

895

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

896

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

911

buffer[0] = si->ps.tv_encoder.adress + WR;

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

987

i2c_bstart(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

988

i2c_writebuffer(si->ps.tv_encoder.bus, buffer, sizeof(buffer));

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

989

i2c_bstop(si->ps.tv_encoder.bus);

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1000

while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1059

if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1074

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1086

if (si->ps.slaved_tmds1) CRTCW(LCD, (CRTCR(LCD) | 0x01));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1095

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

1119

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

130

if (si->ps.card_type > NV04)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

163

if (si->ps.card_type > NV04)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

19

if (si->ps.int_assigned)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

220

if (si->ps.monitors & CRTC1_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

226

((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

230

((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

234

(((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

239

if (target.timing.h_display == si->ps.p1_timing.h_display)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

242

if (si->ps.card_type == NV11)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

270

((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

274

((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

278

((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

389

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

41

if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV05M64)) return B_OK;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

441

if (!(si->ps.monitors & CRTC1_TMDS)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

444

if (si->ps.monitors & CRTC1_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

449

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display);

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

450

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display);

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

460

DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

463

DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

47

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

516

if ((iscale_x != (1 << 12)) && (si->ps.crtc1_screen.aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

527

diff = ((si->ps.p1_timing.h_display -

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

531

DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

536

if ((iscale_y != (1 << 12)) && (si->ps.crtc1_screen.aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

623

if (do_panel && (si->ps.monitors & CRTC1_TMDS))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

625

if (!si->ps.laptop)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

629

if(si->ps.p1_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

630

if(si->ps.p1_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

632

if(si->ps.p1_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

653

if (!(si->ps.monitors & CRTC2_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

66

drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

671

if (do_panel && (si->ps.monitors & CRTC1_TMDS))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

673

if (!si->ps.laptop)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

69

if (si->dm.space != B_RGB32_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

696

if (!(si->ps.monitors & CRTC2_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

743

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

765

LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

766

LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

770

while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

781

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

826

if ((si->ps.card_arch == NV04A) || (si->ps.laptop))

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

852

fb = (vuint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

863

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

885

if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS)));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

903

if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS)));

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

917

cursor = (vuint16*) si->framebuffer;

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

967

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

983

if (yhigh < (si->dm.timing.v_display - 16))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

19

if (si->ps.int_assigned)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

206

if (si->ps.monitors & CRTC2_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

212

((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

216

((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

220

(((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

225

if (target.timing.h_display == si->ps.p2_timing.h_display)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

228

if (si->ps.card_type == NV11)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

256

((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

260

((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

264

((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

41

if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

424

if (!(si->ps.monitors & CRTC2_TMDS)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

427

if (si->ps.monitors & CRTC2_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

432

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

433

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

443

DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

446

DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

47

switch(si->dm.space)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

499

if ((iscale_x != (1 << 12)) && (si->ps.crtc2_screen.aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

510

diff = ((si->ps.p2_timing.h_display -

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

514

DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

519

if ((iscale_y != (1 << 12)) && (si->ps.crtc2_screen.aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

606

if (do_panel && (si->ps.monitors & CRTC2_TMDS))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

608

if (!si->ps.laptop)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

612

if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

613

if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

615

if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

635

if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

653

if (do_panel && (si->ps.monitors & CRTC2_TMDS))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

655

if (!si->ps.laptop)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

66

drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

677

if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

69

if (si->dm.space != B_RGB32_LITTLE)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

724

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

745

LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

746

LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

750

while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

786

if (si->ps.laptop)

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

812

fb = (vuint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

843

if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS)));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

861

if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS)));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

875

cursor = (vuint16*) si->framebuffer;

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

974

if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03));

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

998

if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

110

if ((si->ps.card_type != NV11) && !si->ps.secondary_head) return B_ERROR;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

115

if (si->ps.card_type == NV11) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

135

if (si->ps.card_type == NV11) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

200

if (si->ps.monitors & CRTC1_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

205

target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

227

if (si->ps.card_arch >= NV30A)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

235

if ((si->ps.monitors & CRTC1_TMDS) && !si->settings.pgm_panel) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

244

if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

256

if (si->ps.secondary_head) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

257

if (si->ps.card_arch < NV40A) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

27

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

285

if (si->ps.ext_pll) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

298

f_phase = si->ps.f_ref / (m1 * m2);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

309

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

320

switch (si->ps.card_type) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

344

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

348

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

351

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

354

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

358

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

368

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

372

if (req_pclk < (si->ps.min_pixel_vco / p_max))

src/add-ons/accelerants/nvidia/engine/nv_dac.c

375

req_pclk, (float)(si->ps.min_pixel_vco / p_max)));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

376

req_pclk = (si->ps.min_pixel_vco / p_max);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

393

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/nvidia/engine/nv_dac.c

396

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

403

if (si->ps.card_type == NV36) {

src/add-ons/accelerants/nvidia/engine/nv_dac.c

404

if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

408

if (((si->ps.f_ref / m) < 1.7) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

410

if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

415

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

421

if (si->ps.ext_pll)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

424

error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

427

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

447

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

449

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

499

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

512

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

543

if (si->ps.card_type == NV36) discr_low = 3.2;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

559

if (req_sclk < (si->ps.min_system_vco / ((float)p_max)))

src/add-ons/accelerants/nvidia/engine/nv_dac.c

562

req_sclk, (si->ps.min_system_vco / ((float)p_max))));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

563

req_sclk = (si->ps.min_system_vco / ((float)p_max));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

566

if (req_sclk > si->ps.max_system_vco)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

569

req_sclk, (float)si->ps.max_system_vco));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

570

req_sclk = si->ps.max_system_vco;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

580

if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))

src/add-ons/accelerants/nvidia/engine/nv_dac.c

583

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

589

if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))

src/add-ons/accelerants/nvidia/engine/nv_dac.c

593

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

599

if (si->ps.ext_pll)

src/add-ons/accelerants/nvidia/engine/nv_dac.c

602

error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

605

error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac.c

625

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/nvidia/engine/nv_dac.c

627

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac.c

83

r = si->color_data;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

165

if (si->ps.monitors & CRTC2_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

170

target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

192

if (si->ps.card_arch >= NV30A)

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

20

switch(si->ps.card_type) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

200

if ((si->ps.monitors & CRTC2_TMDS) && !si->settings.pgm_panel) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

209

if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

221

if (si->ps.card_arch < NV40A) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

246

if (si->ps.ext_pll) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

259

f_phase = si->ps.f_ref / (m1 * m2);

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

277

switch (si->ps.card_type) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

301

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

305

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

308

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

311

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

315

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

325

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

329

if (req_pclk < (si->ps.min_video_vco / p_max))

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

332

req_pclk, (float)(si->ps.min_video_vco / p_max)));

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

333

req_pclk = (si->ps.min_video_vco / p_max);

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

350

if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

353

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

360

if (si->ps.card_type == NV36) {

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

361

if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

365

if (((si->ps.f_ref / m) < 1.7) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

367

if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

372

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

377

if (si->ps.ext_pll)

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

380

error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

383

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

403

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

405

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/nvidia/engine/nv_dac2.c

89

r = si->color_data;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1000

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1004

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1005

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1006

sprintf(si->adi.name, "Nvidia Geforce FX 5600XT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1007

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1012

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1013

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1014

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1015

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1016

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1020

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1021

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1022

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1023

sprintf(si->adi.name, "Nvidia Geforce FX 5600 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1024

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1028

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1029

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1030

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1031

sprintf(si->adi.name, "Nvidia Geforce FX 5650 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1032

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1036

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1037

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1038

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1039

sprintf(si->adi.name, "Nvidia Quadro FX 700 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

104

si->ps.laptop = false;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1040

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1046

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1047

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1048

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1049

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1050

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1057

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1058

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1059

sprintf(si->adi.name, "Nvidia Geforce FX 5200");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1060

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1064

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1065

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1066

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1067

sprintf(si->adi.name, "Nvidia Geforce FX 5200 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1068

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1072

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1073

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1074

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1075

sprintf(si->adi.name, "Nvidia Geforce FX 5250 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1076

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1080

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1081

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1082

sprintf(si->adi.name, "Nvidia Geforce FX 5500");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1083

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1087

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1088

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1089

sprintf(si->adi.name, "Nvidia Geforce FX 5100");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1090

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1094

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1095

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1096

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1097

sprintf(si->adi.name, "Nvidia Geforce FX 5200 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1098

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1102

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1103

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1104

sprintf(si->adi.name, "Nvidia Geforce FX 5200");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1105

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1109

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1110

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1111

sprintf(si->adi.name, "Nvidia Quadro NVS 280 PCI");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1112

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1116

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1117

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1118

sprintf(si->adi.name, "Nvidia Quadro FX 500/600 PCI");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1119

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1124

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1125

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1126

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1127

sprintf(si->adi.name, "Nvidia Geforce FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1128

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1133

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1134

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1135

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1136

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1137

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

114

si->ps.card_type = NV04;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1142

si->ps.card_type = NV35;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1143

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1144

sprintf(si->adi.name, "Nvidia Geforce FX 5900");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1145

sprintf(si->adi.chipset, "NV35");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1149

si->ps.card_type = NV35;

src/add-ons/accelerants/nvidia/engine/nv_general.c

115

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1150

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1151

sprintf(si->adi.name, "Nvidia Geforce FX 5900 XT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1152

sprintf(si->adi.chipset, "NV35");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1156

si->ps.card_type = NV38;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1157

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1158

sprintf(si->adi.name, "Nvidia Geforce FX 5950 Ultra");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1159

sprintf(si->adi.chipset, "NV38");

src/add-ons/accelerants/nvidia/engine/nv_general.c

116

sprintf(si->adi.name, "Nvidia TNT1");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1163

si->ps.card_type = NV38;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1164

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1165

sprintf(si->adi.name, "Nvidia Geforce FX 5900 ZT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1166

sprintf(si->adi.chipset, "NV38(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

117

sprintf(si->adi.chipset, "NV04");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1170

si->ps.card_type = NV35;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1171

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1172

sprintf(si->adi.name, "Nvidia Quadro FX 3000");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1173

sprintf(si->adi.chipset, "NV35");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1177

si->ps.card_type = NV35;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1178

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1179

sprintf(si->adi.name, "Nvidia Quadro FX 700");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1180

sprintf(si->adi.chipset, "NV35");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1187

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1188

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1189

sprintf(si->adi.name, "Nvidia Geforce FX 5700");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1190

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1194

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1195

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1196

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1197

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1202

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1203

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1204

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1205

sprintf(si->adi.name, "Nvidia Geforce FX 5700 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1206

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1211

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1212

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1213

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1214

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1215

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1219

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1220

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1221

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1222

sprintf(si->adi.name, "Nvidia Quadro FX 1000 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1223

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1227

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1228

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1229

sprintf(si->adi.name, "Nvidia Quadro FX 1100");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1230

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1234

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1235

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1236

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1237

sprintf(si->adi.chipset, "NV36(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

124

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1241

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1242

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1243

sprintf(si->adi.name, "Nvidia Geforce 7600 GT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1244

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1248

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1249

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

125

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1250

sprintf(si->adi.name, "Nvidia Geforce 7600 GS");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1251

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1255

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1256

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1257

sprintf(si->adi.name, "Nvidia Geforce 7300 GT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1258

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

126

sprintf(si->adi.name, "Nvidia TNT2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1262

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1263

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1264

sprintf(si->adi.name, "Nvidia Geforce 7600 LE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1265

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1269

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

127

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1270

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1271

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1272

sprintf(si->adi.name, "Nvidia Geforce 7600 GO");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1273

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1280

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1281

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1282

sprintf(si->adi.name, "Nvidia Geforce 6100 nForce, C61");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1283

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1287

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1288

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1289

sprintf(si->adi.name, "Nvidia Geforce 7025 nForce 630a");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1290

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1295

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1296

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1297

sprintf(si->adi.name, "Nvidia Geforce 8400 GS");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1298

sprintf(si->adi.chipset, "G98");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1302

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1303

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1304

sprintf(si->adi.name, "Nvidia Geforce 9200M");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1305

sprintf(si->adi.chipset, "G98");

src/add-ons/accelerants/nvidia/engine/nv_general.c

131

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1310

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1311

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1312

sprintf(si->adi.name, "Nvidia Geforce 7100 nForce 630i");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1313

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1318

si->ps.card_type = NV11;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1319

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

132

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1320

sprintf(si->adi.name, "Elsa Gladiac Geforce2 MX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1321

sprintf(si->adi.chipset, "NV11");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1326

si->ps.card_type = NV04;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1327

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1328

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson TNT1");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1329

sprintf(si->adi.chipset, "NV04");

src/add-ons/accelerants/nvidia/engine/nv_general.c

133

sprintf(si->adi.name, "Nvidia Vanta (Lt)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1336

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1337

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1338

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson TNT2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1339

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

134

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1343

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1344

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1345

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson Vanta");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1346

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1350

si->ps.card_type = NV05M64;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1351

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1352

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson TNT2M64");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1353

sprintf(si->adi.chipset, "NV05 model 64");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1358

si->ps.card_type = NV06;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1359

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1360

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson Vanta");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1361

sprintf(si->adi.chipset, "NV06");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1365

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1366

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1367

sprintf(si->adi.name, "Nvidia STB/SGS-Thompson TNT2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1368

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1373

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1374

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1375

sprintf(si->adi.name, "Varisys Geforce4 MX440");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1376

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

138

si->ps.card_type = NV05M64;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1380

si->ps.card_type = NV25;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1381

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1382

sprintf(si->adi.name, "Varisys Geforce4 Ti 4200");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1383

sprintf(si->adi.chipset, "NV25");

src/add-ons/accelerants/nvidia/engine/nv_general.c

139

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

140

sprintf(si->adi.name, "Nvidia TNT2-M64 (Pro)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1400

if (si->fbc.frame_buffer == NULL)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1409

((uint32 *)si->fbc.frame_buffer)[offset] = value;

src/add-ons/accelerants/nvidia/engine/nv_general.c

141

sprintf(si->adi.chipset, "NV05 model 64");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1417

if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1441

if (si->ps.pins_status != B_OK)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1450

switch(si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_general.c

146

si->ps.card_type = NV06;

src/add-ons/accelerants/nvidia/engine/nv_general.c

147

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

148

sprintf(si->adi.name, "Nvidia Vanta");

src/add-ons/accelerants/nvidia/engine/nv_general.c

149

sprintf(si->adi.chipset, "NV06");

src/add-ons/accelerants/nvidia/engine/nv_general.c

155

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1559

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

156

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

157

sprintf(si->adi.name, "Nvidia Geforce FX 6800");

src/add-ons/accelerants/nvidia/engine/nv_general.c

158

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1589

LOG(4,("POWERUP: Detected %s (%s)\n", si->adi.name, si->adi.chipset));

src/add-ons/accelerants/nvidia/engine/nv_general.c

1601

if (!si->settings.usebios)

src/add-ons/accelerants/nvidia/engine/nv_general.c

162

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

163

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1633

if (si->settings.logmask & 0x80000000) nv_dump_configuration_space();

src/add-ons/accelerants/nvidia/engine/nv_general.c

1636

setup_virtualized_heads(si->ps.crtc2_prim);

src/add-ons/accelerants/nvidia/engine/nv_general.c

164

sprintf(si->adi.name, "Nvidia Geforce 6800 XE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1649

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

165

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1652

if (si->ps.card_type != NV11)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1693

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1699

si->crtc_switch_mode = !si->ps.crtc2_prim;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1704

si->crtc_switch_mode = si->ps.crtc2_prim;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1707

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/nvidia/engine/nv_general.c

172

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

173

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

174

sprintf(si->adi.name, "Nvidia Geforce FX 6800");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1740

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

175

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1764

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1770

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1782

si->overlay.crtc = false;

src/add-ons/accelerants/nvidia/engine/nv_general.c

179

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

180

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

181

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1815

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_general.c

182

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1851

if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);

src/add-ons/accelerants/nvidia/engine/nv_general.c

1863

if ((si->ps.card_type == NV44) || (si->ps.card_type >= G70))

src/add-ons/accelerants/nvidia/engine/nv_general.c

1868

if (si->ps.secondary_head) {

src/add-ons/accelerants/nvidia/engine/nv_general.c

187

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1872

if ((si->ps.card_type == NV44) || (si->ps.card_type >= G70))

src/add-ons/accelerants/nvidia/engine/nv_general.c

188

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

1880

if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45))

src/add-ons/accelerants/nvidia/engine/nv_general.c

189

sprintf(si->adi.name, "Nvidia Quadro FX 4000/4400");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1890

if (si->ps.laptop && (si->ps.monitors & CRTC1_TMDS)) nv_dac_dither(true);

src/add-ons/accelerants/nvidia/engine/nv_general.c

1893

if (si->settings.gpu_clk)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1897

set_pll(NV32_COREPLL, si->settings.gpu_clk);

src/add-ons/accelerants/nvidia/engine/nv_general.c

19

#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \

src/add-ons/accelerants/nvidia/engine/nv_general.c

190

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1900

if (si->settings.ram_clk)

src/add-ons/accelerants/nvidia/engine/nv_general.c

1904

set_pll(NV32_MEMPLL, si->settings.ram_clk);

src/add-ons/accelerants/nvidia/engine/nv_general.c

1935

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_general.c

195

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

196

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

197

sprintf(si->adi.name, "Nvidia Geforce 7800 GT PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

198

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

1982

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_general.c

203

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

2031

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_general.c

204

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

205

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

206

sprintf(si->adi.name, "Nvidia Geforce 7800 GTX Go PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

207

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

2073

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_general.c

211

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

212

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

213

sprintf(si->adi.name, "Nvidia Quadro FX 4500");

src/add-ons/accelerants/nvidia/engine/nv_general.c

214

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

218

si->ps.card_type = NV05;

src/add-ons/accelerants/nvidia/engine/nv_general.c

219

si->ps.card_arch = NV04A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

220

sprintf(si->adi.name, "Nvidia Aladdin TNT2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

221

sprintf(si->adi.chipset, "NV05");

src/add-ons/accelerants/nvidia/engine/nv_general.c

225

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

226

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

227

sprintf(si->adi.name, "Nvidia Geforce 6800 GS");

src/add-ons/accelerants/nvidia/engine/nv_general.c

228

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

234

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

235

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

236

sprintf(si->adi.name, "Nvidia Geforce FX 6800");

src/add-ons/accelerants/nvidia/engine/nv_general.c

237

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

242

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

243

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

244

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

245

sprintf(si->adi.name, "Nvidia Geforce FX 6800 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

246

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

250

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

251

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

252

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

253

sprintf(si->adi.name, "Nvidia Quadro FX 1400 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

254

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

258

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

259

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

260

sprintf(si->adi.name, "Nvidia Quadro FX 3450/4000 SDI");

src/add-ons/accelerants/nvidia/engine/nv_general.c

261

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

265

si->ps.card_type = NV41;

src/add-ons/accelerants/nvidia/engine/nv_general.c

266

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

267

sprintf(si->adi.name, "Nvidia Quadro FX 1400");

src/add-ons/accelerants/nvidia/engine/nv_general.c

268

sprintf(si->adi.chipset, "NV41");

src/add-ons/accelerants/nvidia/engine/nv_general.c

272

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

273

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

274

sprintf(si->adi.name, "Nvidia Geforce FX 6800 AGP(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

275

sprintf(si->adi.chipset, "NV40(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

280

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

281

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

282

sprintf(si->adi.name, "Nvidia Geforce FX 6600 (GT) AGP");

src/add-ons/accelerants/nvidia/engine/nv_general.c

283

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

287

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

288

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

289

sprintf(si->adi.name, "Nvidia Geforce 6200");

src/add-ons/accelerants/nvidia/engine/nv_general.c

290

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

294

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

295

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

296

sprintf(si->adi.name, "Nvidia Geforce 6600 LE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

297

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

301

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

302

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

303

sprintf(si->adi.name, "Nvidia Geforce 7800 GS AGP");

src/add-ons/accelerants/nvidia/engine/nv_general.c

304

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

308

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

309

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

310

sprintf(si->adi.name, "Nvidia Geforce 6800 GS");

src/add-ons/accelerants/nvidia/engine/nv_general.c

311

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

315

si->ps.card_type = NV45;

src/add-ons/accelerants/nvidia/engine/nv_general.c

316

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

317

sprintf(si->adi.name, "Nvidia Quadro FX 3400 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

318

sprintf(si->adi.chipset, "NV45");

src/add-ons/accelerants/nvidia/engine/nv_general.c

322

si->ps.card_type = NV45;

src/add-ons/accelerants/nvidia/engine/nv_general.c

323

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

324

sprintf(si->adi.name, "Nvidia Geforce PCX 6800 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

325

sprintf(si->adi.chipset, "NV45");

src/add-ons/accelerants/nvidia/engine/nv_general.c

329

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

330

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

331

sprintf(si->adi.name, "Nvidia Geforce PCX 5750 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

332

sprintf(si->adi.chipset, "NV36");

src/add-ons/accelerants/nvidia/engine/nv_general.c

336

si->ps.card_type = NV35;

src/add-ons/accelerants/nvidia/engine/nv_general.c

337

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

338

sprintf(si->adi.name, "Nvidia Geforce PCX 5900 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

339

sprintf(si->adi.chipset, "NV35(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

343

si->ps.card_type = NV34;

src/add-ons/accelerants/nvidia/engine/nv_general.c

344

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

345

sprintf(si->adi.name, "Nvidia Geforce PCX 5300 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

346

sprintf(si->adi.chipset, "NV34");

src/add-ons/accelerants/nvidia/engine/nv_general.c

350

si->ps.card_type = NV45;

src/add-ons/accelerants/nvidia/engine/nv_general.c

351

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

352

sprintf(si->adi.name, "Nvidia Quadro PCX PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

353

sprintf(si->adi.chipset, "NV45");

src/add-ons/accelerants/nvidia/engine/nv_general.c

357

si->ps.card_type = NV36;

src/add-ons/accelerants/nvidia/engine/nv_general.c

358

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

359

sprintf(si->adi.name, "Nvidia Quadro FX 1300 PCIe(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

360

sprintf(si->adi.chipset, "NV36(?)");

src/add-ons/accelerants/nvidia/engine/nv_general.c

364

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

365

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

366

sprintf(si->adi.name, "Nvidia Geforce PCX 4300 PCIe");

src/add-ons/accelerants/nvidia/engine/nv_general.c

367

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

373

si->ps.card_type = NV10;

src/add-ons/accelerants/nvidia/engine/nv_general.c

374

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

375

sprintf(si->adi.name, "Nvidia Geforce256");

src/add-ons/accelerants/nvidia/engine/nv_general.c

376

sprintf(si->adi.chipset, "NV10");

src/add-ons/accelerants/nvidia/engine/nv_general.c

380

si->ps.card_type = NV10;

src/add-ons/accelerants/nvidia/engine/nv_general.c

381

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

382

sprintf(si->adi.name, "Nvidia Quadro");

src/add-ons/accelerants/nvidia/engine/nv_general.c

383

sprintf(si->adi.chipset, "NV10");

src/add-ons/accelerants/nvidia/engine/nv_general.c

388

si->ps.card_type = NV11;

src/add-ons/accelerants/nvidia/engine/nv_general.c

389

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

390

sprintf(si->adi.name, "Nvidia Geforce2 MX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

391

sprintf(si->adi.chipset, "NV11");

src/add-ons/accelerants/nvidia/engine/nv_general.c

395

si->ps.card_type = NV11;

src/add-ons/accelerants/nvidia/engine/nv_general.c

396

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

397

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

398

sprintf(si->adi.name, "Nvidia Geforce2 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

399

sprintf(si->adi.chipset, "NV11");

src/add-ons/accelerants/nvidia/engine/nv_general.c

403

si->ps.card_type = NV11;

src/add-ons/accelerants/nvidia/engine/nv_general.c

404

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

405

sprintf(si->adi.name, "Nvidia Quadro2 MXR/EX/Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

406

sprintf(si->adi.chipset, "NV11");

src/add-ons/accelerants/nvidia/engine/nv_general.c

412

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

413

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

414

sprintf(si->adi.name, "Nvidia Geforce FX 6600");

src/add-ons/accelerants/nvidia/engine/nv_general.c

415

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

419

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

420

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

421

sprintf(si->adi.name, "Nvidia Geforce 6600 VE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

422

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

426

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

427

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

428

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

429

sprintf(si->adi.name, "Nvidia Geforce FX 6600 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

430

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

434

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

435

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

436

sprintf(si->adi.name, "Nvidia Geforce FX 6610 XL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

437

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

441

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

442

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

443

sprintf(si->adi.name, "Nvidia Geforce FX 6700 XL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

444

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

450

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

451

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

452

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

453

sprintf(si->adi.name, "Nvidia Geforce FX 6600Go/6200Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

454

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

460

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

461

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

462

sprintf(si->adi.name, "Nvidia Quadro FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

463

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

467

si->ps.card_type = NV43;

src/add-ons/accelerants/nvidia/engine/nv_general.c

468

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

469

sprintf(si->adi.name, "Nvidia Quadro FX 540");

src/add-ons/accelerants/nvidia/engine/nv_general.c

470

sprintf(si->adi.chipset, "NV43");

src/add-ons/accelerants/nvidia/engine/nv_general.c

474

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

475

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

476

sprintf(si->adi.name, "Nvidia Geforce 6200 PCIe 128Mb");

src/add-ons/accelerants/nvidia/engine/nv_general.c

477

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

483

si->ps.card_type = NV15;

src/add-ons/accelerants/nvidia/engine/nv_general.c

484

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

485

sprintf(si->adi.name, "Nvidia Geforce2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

486

sprintf(si->adi.chipset, "NV15");

src/add-ons/accelerants/nvidia/engine/nv_general.c

490

si->ps.card_type = NV15;

src/add-ons/accelerants/nvidia/engine/nv_general.c

491

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

492

sprintf(si->adi.name, "Nvidia Quadro2 Pro");

src/add-ons/accelerants/nvidia/engine/nv_general.c

493

sprintf(si->adi.chipset, "NV15");

src/add-ons/accelerants/nvidia/engine/nv_general.c

497

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

498

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

499

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

500

sprintf(si->adi.name, "Nvidia Geforce 6500 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

501

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

505

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

506

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

507

sprintf(si->adi.name, "Nvidia Geforce 6200 TC");

src/add-ons/accelerants/nvidia/engine/nv_general.c

508

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

512

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

513

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

514

sprintf(si->adi.name, "Nvidia Geforce 6200SE TC");

src/add-ons/accelerants/nvidia/engine/nv_general.c

515

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

519

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

520

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

521

sprintf(si->adi.name, "Nvidia Geforce 6200LE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

522

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

526

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

527

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

528

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

529

sprintf(si->adi.name, "Nvidia Geforce FX 6200 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

530

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

534

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

535

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

536

sprintf(si->adi.name, "Nvidia Quadro FX NVS 285");

src/add-ons/accelerants/nvidia/engine/nv_general.c

537

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

541

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

542

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

543

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

544

sprintf(si->adi.name, "Nvidia Geforce 6400 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

545

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

549

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

550

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

551

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

552

sprintf(si->adi.name, "Nvidia Geforce 6200 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

553

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

557

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

558

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

559

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

560

sprintf(si->adi.name, "Nvidia Geforce 6400 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

561

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

565

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

566

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

567

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

568

sprintf(si->adi.name, "Nvidia Geforce 6250 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

569

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

573

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

574

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

575

sprintf(si->adi.name, "Nvidia Geforce 7100 GS");

src/add-ons/accelerants/nvidia/engine/nv_general.c

576

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

582

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

583

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

584

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

585

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

586

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

590

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

591

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

592

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

593

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

600

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

601

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

602

sprintf(si->adi.name, "Nvidia Geforce4 MX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

603

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

611

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

612

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

613

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

614

sprintf(si->adi.name, "Nvidia Geforce4 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

615

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

620

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

621

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

622

sprintf(si->adi.name, "Nvidia Quadro4");

src/add-ons/accelerants/nvidia/engine/nv_general.c

623

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

627

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

628

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

629

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

630

sprintf(si->adi.name, "Nvidia Quadro4 500 GoGL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

631

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

635

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

636

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

637

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

638

sprintf(si->adi.name, "Nvidia Geforce4 410 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

639

sprintf(si->adi.chipset, "NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

646

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

647

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

648

sprintf(si->adi.name, "Nvidia Geforce4 MX AGP8X");

src/add-ons/accelerants/nvidia/engine/nv_general.c

649

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

654

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

655

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

656

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

657

sprintf(si->adi.name, "Nvidia Geforce4 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

658

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

662

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

663

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

664

sprintf(si->adi.name, "Nvidia Quadro4");

src/add-ons/accelerants/nvidia/engine/nv_general.c

665

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

669

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

670

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

671

sprintf(si->adi.name, "Nvidia Geforce4 MX AGP8X");

src/add-ons/accelerants/nvidia/engine/nv_general.c

672

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

678

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

679

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

680

sprintf(si->adi.name, "Nvidia Quadro4");

src/add-ons/accelerants/nvidia/engine/nv_general.c

681

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

685

si->ps.card_type = NV18;

src/add-ons/accelerants/nvidia/engine/nv_general.c

686

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

687

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

688

sprintf(si->adi.name, "Nvidia Geforce4 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

689

sprintf(si->adi.chipset, "NV18");

src/add-ons/accelerants/nvidia/engine/nv_general.c

693

si->ps.card_type = NV11;

src/add-ons/accelerants/nvidia/engine/nv_general.c

694

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

695

sprintf(si->adi.name, "Nvidia Geforce2 Integrated GPU");

src/add-ons/accelerants/nvidia/engine/nv_general.c

696

sprintf(si->adi.chipset, "CRUSH, NV11");

src/add-ons/accelerants/nvidia/engine/nv_general.c

702

si->ps.card_type = G72;

src/add-ons/accelerants/nvidia/engine/nv_general.c

703

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

704

sprintf(si->adi.name, "Nvidia Geforce 7300");

src/add-ons/accelerants/nvidia/engine/nv_general.c

705

sprintf(si->adi.chipset, "G72");

src/add-ons/accelerants/nvidia/engine/nv_general.c

709

si->ps.card_type = G72;

src/add-ons/accelerants/nvidia/engine/nv_general.c

710

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

711

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

712

sprintf(si->adi.name, "Nvidia Quadro NVS M/GF 7300 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

713

sprintf(si->adi.chipset, "G72");

src/add-ons/accelerants/nvidia/engine/nv_general.c

717

si->ps.card_type = G72;

src/add-ons/accelerants/nvidia/engine/nv_general.c

718

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

719

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

720

sprintf(si->adi.name, "Nvidia Geforce 7400 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

721

sprintf(si->adi.chipset, "G72");

src/add-ons/accelerants/nvidia/engine/nv_general.c

725

si->ps.card_type = G72;

src/add-ons/accelerants/nvidia/engine/nv_general.c

726

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

727

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

728

sprintf(si->adi.name, "Nvidia Quadro NVS 110M");

src/add-ons/accelerants/nvidia/engine/nv_general.c

729

sprintf(si->adi.chipset, "G72");

src/add-ons/accelerants/nvidia/engine/nv_general.c

733

si->ps.card_type = G72;

src/add-ons/accelerants/nvidia/engine/nv_general.c

734

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

735

sprintf(si->adi.name, "Nvidia Geforce 7500 LE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

736

sprintf(si->adi.chipset, "G72");

src/add-ons/accelerants/nvidia/engine/nv_general.c

740

si->ps.card_type = NV17;

src/add-ons/accelerants/nvidia/engine/nv_general.c

741

si->ps.card_arch = NV10A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

742

sprintf(si->adi.name, "Nvidia Geforce4 MX Integr. GPU");

src/add-ons/accelerants/nvidia/engine/nv_general.c

743

sprintf(si->adi.chipset, "NFORCE2, NV17");

src/add-ons/accelerants/nvidia/engine/nv_general.c

749

si->ps.card_type = NV20;

src/add-ons/accelerants/nvidia/engine/nv_general.c

750

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

751

sprintf(si->adi.name, "Nvidia Geforce3");

src/add-ons/accelerants/nvidia/engine/nv_general.c

752

sprintf(si->adi.chipset, "NV20");

src/add-ons/accelerants/nvidia/engine/nv_general.c

756

si->ps.card_type = NV20;

src/add-ons/accelerants/nvidia/engine/nv_general.c

757

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

758

sprintf(si->adi.name, "Nvidia Quadro DCC");

src/add-ons/accelerants/nvidia/engine/nv_general.c

759

sprintf(si->adi.chipset, "NV20");

src/add-ons/accelerants/nvidia/engine/nv_general.c

765

si->ps.card_type = NV45; /* NV48 is NV45 with 512Mb */

src/add-ons/accelerants/nvidia/engine/nv_general.c

766

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

767

sprintf(si->adi.name, "Nvidia Geforce FX 6800");

src/add-ons/accelerants/nvidia/engine/nv_general.c

768

sprintf(si->adi.chipset, "NV48");

src/add-ons/accelerants/nvidia/engine/nv_general.c

772

si->ps.card_type = NV40;

src/add-ons/accelerants/nvidia/engine/nv_general.c

773

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

774

sprintf(si->adi.name, "Nvidia Geforce 6800 XT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

775

sprintf(si->adi.chipset, "NV40");

src/add-ons/accelerants/nvidia/engine/nv_general.c

779

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

780

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

781

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

782

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

786

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

787

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

788

sprintf(si->adi.name, "Nvidia Geforce 6200 AGP 256Mb");

src/add-ons/accelerants/nvidia/engine/nv_general.c

789

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

793

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

794

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

795

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

796

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

800

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

801

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

802

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

803

sprintf(si->adi.name, "Nvidia unknown FX Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

804

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

808

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

809

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

810

sprintf(si->adi.name, "Nvidia Geforce 6150, C51PV");

src/add-ons/accelerants/nvidia/engine/nv_general.c

811

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

815

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

816

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

817

sprintf(si->adi.name, "Nvidia Geforce 6150, C51");

src/add-ons/accelerants/nvidia/engine/nv_general.c

818

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

822

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

823

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

824

sprintf(si->adi.name, "Nvidia Geforce 6100, C51G");

src/add-ons/accelerants/nvidia/engine/nv_general.c

825

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

829

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

830

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

831

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

832

sprintf(si->adi.name, "Nvidia Geforce 6150 Go, C51");

src/add-ons/accelerants/nvidia/engine/nv_general.c

833

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

837

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

838

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

839

sprintf(si->adi.name, "Nvidia Geforce 6150, C51");

src/add-ons/accelerants/nvidia/engine/nv_general.c

840

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

844

si->ps.card_type = NV44;

src/add-ons/accelerants/nvidia/engine/nv_general.c

845

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

846

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

847

sprintf(si->adi.name, "Nvidia Geforce 6100 Go, C51");

src/add-ons/accelerants/nvidia/engine/nv_general.c

848

sprintf(si->adi.chipset, "NV44");

src/add-ons/accelerants/nvidia/engine/nv_general.c

855

si->ps.card_type = NV25;

src/add-ons/accelerants/nvidia/engine/nv_general.c

856

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

857

sprintf(si->adi.name, "Nvidia Geforce4 Ti");

src/add-ons/accelerants/nvidia/engine/nv_general.c

858

sprintf(si->adi.chipset, "NV25");

src/add-ons/accelerants/nvidia/engine/nv_general.c

864

si->ps.card_type = NV25;

src/add-ons/accelerants/nvidia/engine/nv_general.c

865

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

866

sprintf(si->adi.name, "Nvidia Quadro4 XGL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

867

sprintf(si->adi.chipset, "NV25");

src/add-ons/accelerants/nvidia/engine/nv_general.c

872

si->ps.card_type = NV28;

src/add-ons/accelerants/nvidia/engine/nv_general.c

873

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

874

sprintf(si->adi.name, "Nvidia Geforce4 Ti AGP8X");

src/add-ons/accelerants/nvidia/engine/nv_general.c

875

sprintf(si->adi.chipset, "NV28");

src/add-ons/accelerants/nvidia/engine/nv_general.c

879

si->ps.card_type = NV28;

src/add-ons/accelerants/nvidia/engine/nv_general.c

880

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

881

sprintf(si->adi.name, "Nvidia Geforce4 Ti 4800SE");

src/add-ons/accelerants/nvidia/engine/nv_general.c

882

sprintf(si->adi.chipset, "NV28");

src/add-ons/accelerants/nvidia/engine/nv_general.c

886

si->ps.card_type = NV28;

src/add-ons/accelerants/nvidia/engine/nv_general.c

887

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

888

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

889

sprintf(si->adi.name, "Nvidia Geforce4 4200 Go");

src/add-ons/accelerants/nvidia/engine/nv_general.c

890

sprintf(si->adi.chipset, "NV28");

src/add-ons/accelerants/nvidia/engine/nv_general.c

895

si->ps.card_type = NV28;

src/add-ons/accelerants/nvidia/engine/nv_general.c

896

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

897

sprintf(si->adi.name, "Nvidia Quadro4 XGL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

898

sprintf(si->adi.chipset, "NV28");

src/add-ons/accelerants/nvidia/engine/nv_general.c

902

si->ps.card_type = NV28;

src/add-ons/accelerants/nvidia/engine/nv_general.c

903

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

904

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

905

sprintf(si->adi.name, "Nvidia Quadro4 700 GoGL");

src/add-ons/accelerants/nvidia/engine/nv_general.c

906

sprintf(si->adi.chipset, "NV28");

src/add-ons/accelerants/nvidia/engine/nv_general.c

913

si->ps.card_type = G71;

src/add-ons/accelerants/nvidia/engine/nv_general.c

914

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

915

sprintf(si->adi.name, "Nvidia Geforce 7900");

src/add-ons/accelerants/nvidia/engine/nv_general.c

916

sprintf(si->adi.chipset, "G71");

src/add-ons/accelerants/nvidia/engine/nv_general.c

921

si->ps.card_type = G71;

src/add-ons/accelerants/nvidia/engine/nv_general.c

922

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

923

sprintf(si->adi.name, "Nvidia Geforce 7950");

src/add-ons/accelerants/nvidia/engine/nv_general.c

924

sprintf(si->adi.chipset, "G71");

src/add-ons/accelerants/nvidia/engine/nv_general.c

929

si->ps.card_type = G71;

src/add-ons/accelerants/nvidia/engine/nv_general.c

930

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

931

si->ps.laptop = true;

src/add-ons/accelerants/nvidia/engine/nv_general.c

932

sprintf(si->adi.name, "Nvidia Geforce Go 7900");

src/add-ons/accelerants/nvidia/engine/nv_general.c

933

sprintf(si->adi.chipset, "G71");

src/add-ons/accelerants/nvidia/engine/nv_general.c

937

si->ps.card_type = G71;

src/add-ons/accelerants/nvidia/engine/nv_general.c

938

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

939

sprintf(si->adi.name, "Nvidia Quadro FX 5500");

src/add-ons/accelerants/nvidia/engine/nv_general.c

940

sprintf(si->adi.chipset, "G71");

src/add-ons/accelerants/nvidia/engine/nv_general.c

944

si->ps.card_type = G70;

src/add-ons/accelerants/nvidia/engine/nv_general.c

945

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

946

sprintf(si->adi.name, "Nvidia Quadro FX 4500 X2");

src/add-ons/accelerants/nvidia/engine/nv_general.c

947

sprintf(si->adi.chipset, "G70");

src/add-ons/accelerants/nvidia/engine/nv_general.c

951

si->ps.card_type = NV20;

src/add-ons/accelerants/nvidia/engine/nv_general.c

952

si->ps.card_arch = NV20A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

953

sprintf(si->adi.name, "Nvidia Geforce3 Integrated GPU");

src/add-ons/accelerants/nvidia/engine/nv_general.c

954

sprintf(si->adi.chipset, "XBOX, NV20");

src/add-ons/accelerants/nvidia/engine/nv_general.c

959

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

960

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

961

sprintf(si->adi.name, "Nvidia Geforce 7600");

src/add-ons/accelerants/nvidia/engine/nv_general.c

962

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

966

si->ps.card_type = G73;

src/add-ons/accelerants/nvidia/engine/nv_general.c

967

si->ps.card_arch = NV40A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

968

sprintf(si->adi.name, "Nvidia GeForce 7300 GT");

src/add-ons/accelerants/nvidia/engine/nv_general.c

969

sprintf(si->adi.chipset, "G73");

src/add-ons/accelerants/nvidia/engine/nv_general.c

974

si->ps.card_type = NV30;

src/add-ons/accelerants/nvidia/engine/nv_general.c

975

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

976

sprintf(si->adi.name, "Nvidia Geforce FX 5800");

src/add-ons/accelerants/nvidia/engine/nv_general.c

977

sprintf(si->adi.chipset, "NV30");

src/add-ons/accelerants/nvidia/engine/nv_general.c

98

if (si->ps.int_assigned)

src/add-ons/accelerants/nvidia/engine/nv_general.c

982

si->ps.card_type = NV30;

src/add-ons/accelerants/nvidia/engine/nv_general.c

983

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

984

sprintf(si->adi.name, "Nvidia Quadro FX");

src/add-ons/accelerants/nvidia/engine/nv_general.c

985

sprintf(si->adi.chipset, "NV30");

src/add-ons/accelerants/nvidia/engine/nv_general.c

990

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

991

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

992

sprintf(si->adi.name, "Nvidia Geforce FX 5600");

src/add-ons/accelerants/nvidia/engine/nv_general.c

993

sprintf(si->adi.chipset, "NV31");

src/add-ons/accelerants/nvidia/engine/nv_general.c

997

si->ps.card_type = NV31;

src/add-ons/accelerants/nvidia/engine/nv_general.c

998

si->ps.card_arch = NV30A;

src/add-ons/accelerants/nvidia/engine/nv_general.c

999

sprintf(si->adi.name, "Nvidia unknown FX");

src/add-ons/accelerants/nvidia/engine/nv_globals.c

13

shared_info *si;

src/add-ons/accelerants/nvidia/engine/nv_globals.h

2

extern shared_info *si;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

32

if (!si->ps.secondary_head) return;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

375

bool *i2c_bus = &(si->ps.i2c_bus0);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

387

if (si->ps.card_arch == NV40A)

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

391

si->ps.i2c_bus0 = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

392

si->ps.i2c_bus1 = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

393

si->ps.i2c_bus2 = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

399

if (((si->ps.card_arch == NV10A) && (si->ps.card_type >= NV17)) || (si->ps.card_arch >= NV30A))

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

439

i2c_DumpSpecsEDID(&si->ps.con1_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

441

i2c_DumpSpecsEDID(&si->ps.con2_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

671

bool *i2c_bus = &(si->ps.i2c_bus0);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

793

si->ps.con1_screen.have_native_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

794

si->ps.con2_screen.have_native_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

795

si->ps.con1_screen.have_full_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

796

si->ps.con2_screen.have_full_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

797

si->ps.con1_screen.aspect = 0;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

798

si->ps.con2_screen.aspect = 0;

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

801

if (si->ps.i2c_bus0) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

805

switch (si->ps.card_arch) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

807

i2c_ExtractSpecsEDID(&edid, &si->ps.con2_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

810

i2c_ExtractSpecsEDID(&edid, &si->ps.con1_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

817

if (si->ps.i2c_bus1) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

821

switch (si->ps.card_arch) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

823

i2c_ExtractSpecsEDID(&edid, &si->ps.con1_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

826

i2c_ExtractSpecsEDID(&edid, &si->ps.con2_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

833

if (si->ps.i2c_bus2) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

837

switch (si->ps.card_arch) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

839

if (!si->ps.con2_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

840

i2c_ExtractSpecsEDID(&edid, &si->ps.con2_screen);

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

846

if (!si->ps.con2_screen.have_native_edid && si->ps.laptop) {

src/add-ons/accelerants/nvidia/engine/nv_i2c.c

847

i2c_ExtractSpecsEDID(&edid, &si->ps.con2_screen);

src/add-ons/accelerants/nvidia/engine/nv_info.c

131

si->ps.pins_status = B_OK;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1439

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_info.c

1889

((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1891

((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1893

((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1895

((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1898

((volatile uint32 *)si->framebuffer)[0x07] = 0x4e563131;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1901

((volatile uint32 *)si->framebuffer)[0x0f] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1904

if (((volatile uint32 *)si->framebuffer)[0x07] == 0x4e563131) stat = B_OK;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1939

((volatile uint32 *)si->framebuffer)[(data >> 2)] = 0x4e564441;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1942

((volatile uint32 *)si->framebuffer)[0x00] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1945

dummy = ((volatile uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1946

dummy = ((volatile uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1947

dummy = ((volatile uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1948

dummy = ((volatile uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1950

if (((volatile uint32 *)si->framebuffer)[(data >> 2)] == 0x4e564441) stat = B_OK;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1989

((volatile uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441;

src/add-ons/accelerants/nvidia/engine/nv_info.c

199

si->ps.min_system_vco = fvco_min / 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1992

((volatile uint32 *)si->framebuffer)[0x00000000] = 0x00000000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

1995

dummy = ((volatile uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1997

dummy = ((volatile uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/nvidia/engine/nv_info.c

1999

dummy = ((volatile uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/nvidia/engine/nv_info.c

200

si->ps.max_system_vco = fvco_max / 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2001

dummy = ((volatile uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/nvidia/engine/nv_info.c

2004

if (((volatile uint32 *)si->framebuffer)[0x01fc0000] == 0x4e564441) stat = B_OK;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2089

if (si->ps.ext_pll)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2119

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2132

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2153

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2170

switch (si->ps.card_arch)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2181

if (si->settings.memory != 0)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2184

si->ps.memory_size = si->settings.memory * 1024 * 1024;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2188

si->ps.tvout = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2189

si->ps.tv_encoder.type = NONE;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2190

si->ps.tv_encoder.version = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2205

if (si->ps.secondary_head && si->settings.switchhead)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2208

si->ps.crtc2_prim = !si->ps.crtc2_prim;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2268

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2294

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2295

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2296

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2297

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2298

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2299

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2300

si->ps.master_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2301

si->ps.master_tmds2 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2302

si->ps.monitors = 0x00;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2334

si->ps.slaved_tmds1 = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2335

si->ps.monitors |= CRTC1_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2336

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2337

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2341

if (si->ps.secondary_head && slaved_for_dev2 && !tvout2)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2347

si->ps.slaved_tmds2 = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2348

si->ps.monitors |= CRTC2_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2349

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2350

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2354

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2355

!si->ps.slaved_tmds1 && !tvout1)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2361

si->ps.master_tmds1 = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2362

si->ps.monitors |= CRTC1_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2363

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2364

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2368

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2369

si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2375

si->ps.master_tmds2 = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2376

si->ps.monitors |= CRTC2_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2377

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2378

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2385

if (si->ps.laptop &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2386

((si->ps.monitors & (CRTC1_TMDS | CRTC2_TMDS)) == (CRTC1_TMDS | CRTC2_TMDS)) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2388

(si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2389

(si->ps.p1_timing.v_display == si->ps.p2_timing.v_display))

src/add-ons/accelerants/nvidia/engine/nv_info.c

2393

if (si->ps.card_type == NV11)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2396

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2397

si->ps.master_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2398

si->ps.monitors &= ~CRTC1_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2399

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2400

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2407

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2408

si->ps.master_tmds1 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2409

si->ps.monitors &= ~CRTC1_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2410

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2411

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2416

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2417

si->ps.master_tmds2 = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2418

si->ps.monitors &= ~CRTC2_TMDS;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2419

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2420

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2426

if (si->ps.monitors & CRTC1_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2429

si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2430

si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2431

si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2433

si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2434

si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2435

si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2437

si->ps.p1_timing.flags = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2438

if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2439

if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2441

if (DACR(FP_TG_CTRL) & 0x10000000) si->ps.p1_timing.flags |= B_BLANK_PEDESTAL;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2444

si->ps.p1_timing.pixel_clock =

src/add-ons/accelerants/nvidia/engine/nv_info.c

2445

(si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2447

if (si->ps.monitors & CRTC2_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2450

si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2451

si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2452

si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2454

si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2455

si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2456

si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2458

si->ps.p2_timing.flags = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2459

if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2460

if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2462

if (DAC2R(FP_TG_CTRL) & 0x10000000) si->ps.p2_timing.flags |= B_BLANK_PEDESTAL;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2465

si->ps.p2_timing.pixel_clock =

src/add-ons/accelerants/nvidia/engine/nv_info.c

2466

(si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2499

if(si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2541

if ((si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_info.c

2552

if ((si->ps.monitors & CRTC2_TMDS) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_info.c

2572

si->ps.crtc2_prim = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2574

si->ps.crtc1_screen.have_native_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2575

si->ps.crtc1_screen.have_full_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2576

si->ps.crtc1_screen.timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2577

si->ps.crtc1_screen.timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2578

si->ps.crtc2_screen.have_native_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2579

si->ps.crtc2_screen.have_full_edid = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2580

si->ps.crtc2_screen.timing.h_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2581

si->ps.crtc2_screen.timing.v_display = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2584

if ((si->ps.secondary_head) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_info.c

2593

if (si->ps.con1_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2594

if (!si->ps.con1_screen.digital) si->ps.monitors |= CRTC1_VGA;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2597

si->ps.monitors |= CRTC1_VGA;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2599

si->ps.con1_screen.aspect = 1.33;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2609

if(si->ps.monitors & CRTC1_TMDS) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2613

if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2614

(si->ps.p1_timing.h_display == si->ps.con1_screen.timing.h_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2615

(si->ps.p1_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2616

(si->ps.p1_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2617

(si->ps.p1_timing.h_total == si->ps.con1_screen.timing.h_total) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2618

(si->ps.p1_timing.v_display == si->ps.con1_screen.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2619

(si->ps.p1_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2620

(si->ps.p1_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2621

(si->ps.p1_timing.v_total == si->ps.con1_screen.timing.v_total)) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2623

memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2625

if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2626

(si->ps.p1_timing.h_display == si->ps.con2_screen.timing.h_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2627

(si->ps.p1_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2628

(si->ps.p1_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2629

(si->ps.p1_timing.h_total == si->ps.con2_screen.timing.h_total) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2630

(si->ps.p1_timing.v_display == si->ps.con2_screen.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2631

(si->ps.p1_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2632

(si->ps.p1_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2633

(si->ps.p1_timing.v_total == si->ps.con2_screen.timing.v_total)) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2635

memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2638

si->ps.crtc1_screen.timing.pixel_clock = si->ps.p1_timing.pixel_clock;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2639

si->ps.crtc1_screen.timing.h_display = si->ps.p1_timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2640

si->ps.crtc1_screen.timing.h_sync_start = si->ps.p1_timing.h_sync_start;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2641

si->ps.crtc1_screen.timing.h_sync_end = si->ps.p1_timing.h_sync_end;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2642

si->ps.crtc1_screen.timing.h_total = si->ps.p1_timing.h_total;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2643

si->ps.crtc1_screen.timing.v_display = si->ps.p1_timing.v_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2644

si->ps.crtc1_screen.timing.v_sync_start = si->ps.p1_timing.v_sync_start;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2645

si->ps.crtc1_screen.timing.v_sync_end = si->ps.p1_timing.v_sync_end;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2646

si->ps.crtc1_screen.timing.v_total = si->ps.p1_timing.v_total;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2647

si->ps.crtc1_screen.timing.flags = si->ps.p1_timing.flags;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2648

si->ps.crtc1_screen.have_native_edid = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2649

si->ps.crtc1_screen.aspect =

src/add-ons/accelerants/nvidia/engine/nv_info.c

2650

(si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2651

si->ps.crtc1_screen.digital = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2654

} else if(si->ps.monitors & CRTC1_VGA) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2656

memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2660

if (si->settings.force_ws) si->ps.crtc1_screen.aspect = 1.78;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2663

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2669

if(si->ps.monitors & CRTC2_TMDS) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2673

if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2674

(si->ps.p2_timing.h_display == si->ps.con1_screen.timing.h_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2675

(si->ps.p2_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2676

(si->ps.p2_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2677

(si->ps.p2_timing.h_total == si->ps.con1_screen.timing.h_total) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2678

(si->ps.p2_timing.v_display == si->ps.con1_screen.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2679

(si->ps.p2_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

268

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2680

(si->ps.p2_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2681

(si->ps.p2_timing.v_total == si->ps.con1_screen.timing.v_total)) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2683

memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2685

if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2686

(si->ps.p2_timing.h_display == si->ps.con2_screen.timing.h_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2687

(si->ps.p2_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2688

(si->ps.p2_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2689

(si->ps.p2_timing.h_total == si->ps.con2_screen.timing.h_total) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2690

(si->ps.p2_timing.v_display == si->ps.con2_screen.timing.v_display) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2691

(si->ps.p2_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2692

(si->ps.p2_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) &&

src/add-ons/accelerants/nvidia/engine/nv_info.c

2693

(si->ps.p2_timing.v_total == si->ps.con2_screen.timing.v_total)) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2695

memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2698

si->ps.crtc2_screen.timing.pixel_clock = si->ps.p2_timing.pixel_clock;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2699

si->ps.crtc2_screen.timing.h_display = si->ps.p2_timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2700

si->ps.crtc2_screen.timing.h_sync_start = si->ps.p2_timing.h_sync_start;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2701

si->ps.crtc2_screen.timing.h_sync_end = si->ps.p2_timing.h_sync_end;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2702

si->ps.crtc2_screen.timing.h_total = si->ps.p2_timing.h_total;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2703

si->ps.crtc2_screen.timing.v_display = si->ps.p2_timing.v_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2704

si->ps.crtc2_screen.timing.v_sync_start = si->ps.p2_timing.v_sync_start;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2705

si->ps.crtc2_screen.timing.v_sync_end = si->ps.p2_timing.v_sync_end;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2706

si->ps.crtc2_screen.timing.v_total = si->ps.p2_timing.v_total;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2707

si->ps.crtc2_screen.timing.flags = si->ps.p2_timing.flags;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2708

si->ps.crtc2_screen.have_native_edid = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2709

si->ps.crtc2_screen.aspect =

src/add-ons/accelerants/nvidia/engine/nv_info.c

2710

(si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2711

si->ps.crtc2_screen.digital = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2716

if (si->ps.card_type != NV11)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2725

if (si->ps.con2_screen.have_native_edid) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2726

if (!si->ps.con2_screen.digital) si->ps.monitors |= CRTC2_VGA;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2729

si->ps.monitors |= CRTC2_VGA;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2731

si->ps.con2_screen.aspect = 1.33;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2737

if ((si->ps.monitors & (CRTC2_TMDS | CRTC2_VGA)) == CRTC2_VGA) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2739

memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2742

if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2746

switch (si->ps.monitors)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2769

si->ps.monitors = 0x21;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2771

memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2780

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2783

if (si->ps.card_arch < NV40A) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2787

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2789

switch (si->ps.card_type) {

src/add-ons/accelerants/nvidia/engine/nv_info.c

2796

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

280

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2830

si->ps.monitors = 0x12;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2832

memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2836

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2847

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2860

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2864

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2867

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2880

if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2884

switch (si->ps.monitors)

src/add-ons/accelerants/nvidia/engine/nv_info.c

2911

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2922

si->ps.crtc2_prim = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2925

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2939

if (!si->ps.crtc1_screen.have_native_edid) return B_ERROR;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2942

mode->virtual_width = si->ps.crtc1_screen.timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2943

mode->virtual_height = si->ps.crtc1_screen.timing.v_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2947

memcpy(&mode->timing, &si->ps.crtc1_screen.timing, sizeof(mode->timing));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2954

if (!si->ps.crtc2_screen.have_native_edid) return B_ERROR;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2957

mode->virtual_width = si->ps.crtc2_screen.timing.h_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2958

mode->virtual_height = si->ps.crtc2_screen.timing.v_display;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2962

memcpy(&mode->timing, &si->ps.crtc2_screen.timing, sizeof(mode->timing));

src/add-ons/accelerants/nvidia/engine/nv_info.c

2970

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2972

si->ps.max_system_vco = 256;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2973

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2974

si->ps.max_pixel_vco = 256;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2975

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2976

si->ps.max_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2977

si->ps.min_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2978

si->ps.max_dac1_clock = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2979

si->ps.max_dac1_clock_8 = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2980

si->ps.max_dac1_clock_16 = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2982

si->ps.max_dac1_clock_24 = 220;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2983

si->ps.max_dac1_clock_32 = 180;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2984

si->ps.max_dac1_clock_32dh = 180;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2986

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2987

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2988

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2989

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2990

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2992

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2994

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2995

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2997

si->ps.std_engine_clock = 90;

src/add-ons/accelerants/nvidia/engine/nv_info.c

2998

si->ps.std_memory_clock = 110;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3004

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3006

si->ps.max_system_vco = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3007

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3008

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3009

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3010

si->ps.max_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3011

si->ps.min_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3012

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3013

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3014

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3016

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3017

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3018

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3020

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3021

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3022

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3023

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3024

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3026

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3028

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3029

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3031

si->ps.std_engine_clock = 125;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3032

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3038

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3040

si->ps.max_system_vco = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3041

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3042

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3043

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3044

si->ps.max_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3045

si->ps.min_video_vco = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3046

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3047

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3048

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3050

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3051

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3052

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3054

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3055

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3056

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3057

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3058

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3060

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3062

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3063

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3065

si->ps.std_engine_clock = 100;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3066

si->ps.std_memory_clock = 125;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3072

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3074

si->ps.max_system_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3075

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3076

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3077

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3078

si->ps.max_video_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3079

si->ps.min_video_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3080

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3081

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3082

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3084

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3085

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3086

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3088

if (si->ps.card_type < NV17)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3093

si->ps.max_dac2_clock = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3094

si->ps.max_dac2_clock_8 = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3095

si->ps.max_dac2_clock_16 = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3096

si->ps.max_dac2_clock_24 = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3097

si->ps.max_dac2_clock_32 = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3099

si->ps.max_dac2_clock_32dh = 180;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3105

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3106

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3107

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3109

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3110

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3111

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3114

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3115

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3117

si->ps.std_engine_clock = 120;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3118

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3124

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3126

si->ps.max_system_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3127

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3128

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3129

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3130

si->ps.max_video_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3131

si->ps.min_video_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3132

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3133

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3134

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3136

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3137

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3138

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3142

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3143

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3144

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3146

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3147

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3148

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3150

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3151

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3153

si->ps.std_engine_clock = 175;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3154

si->ps.std_memory_clock = 200;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3168

if ((si->ps.card_type == NV31) ||

src/add-ons/accelerants/nvidia/engine/nv_info.c

3169

(si->ps.card_type == NV36) ||

src/add-ons/accelerants/nvidia/engine/nv_info.c

3170

(si->ps.card_type >= NV40))

src/add-ons/accelerants/nvidia/engine/nv_info.c

3173

si->ps.ext_pll = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3178

si->ps.ext_pll = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3181

si->ps.max_system_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3182

si->ps.min_system_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3183

if (si->ps.ext_pll)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3185

si->ps.max_pixel_vco = 600;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3186

si->ps.min_pixel_vco = 220;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3187

si->ps.max_video_vco = 600;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3188

si->ps.min_video_vco = 220;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3192

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3193

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3194

si->ps.max_video_vco = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3195

si->ps.min_video_vco = 128;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3197

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3198

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3199

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3201

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3202

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3203

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3207

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3208

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3209

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3211

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3212

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3213

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3215

si->ps.primary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3216

si->ps.secondary_dvi = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3218

si->ps.std_engine_clock = 190;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3219

si->ps.std_memory_clock = 190;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3223

si->ps.max_system_vco = 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3224

si->ps.min_system_vco = 500;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3225

si->ps.max_pixel_vco = 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3226

si->ps.min_pixel_vco = 500;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3227

si->ps.max_video_vco = 1000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3228

si->ps.min_video_vco = 500;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3239

si->ps.memory_size = 1024 * 1024 *

src/add-ons/accelerants/nvidia/engine/nv_info.c

324

if (si->ps.card_type == NV28)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3250

si->ps.memory_size = 32 * 1024 * 1024;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3253

si->ps.memory_size = 4 * 1024 * 1024;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3256

si->ps.memory_size = 8 * 1024 * 1024;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3259

si->ps.memory_size = 16 * 1024 * 1024;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3271

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3273

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3276

si->ps.secondary_head = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3295

(si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3306

if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3316

si->ps.secondary_head = false;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3317

switch (si->ps.card_type)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3334

si->ps.secondary_head = true;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3339

if ((si->ps.secondary_head) && (si->ps.card_type != NV11))

src/add-ons/accelerants/nvidia/engine/nv_info.c

3346

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3349

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3352

si->ps.f_ref = 27.00000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3355

si->ps.f_ref = 25.00000;

src/add-ons/accelerants/nvidia/engine/nv_info.c

3365

LOG(2,("PLL type: %s\n", si->ps.ext_pll ? "extended" : "standard"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3366

LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3367

LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3368

LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3369

LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3370

LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3371

LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3372

LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3373

LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3374

LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3375

LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3376

LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3377

LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3378

LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3379

LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3380

LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3381

LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3382

LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3383

LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3384

LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3385

LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3386

LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3387

LOG(2,("secondary_head: %s\n", si->ps.secondary_head ? "present" : "absent"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3388

LOG(2,("tvout: %s\n", si->ps.tvout ? "present" : "absent"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3390

switch (si->ps.tv_encoder.type)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3445

msg, si->ps.tv_encoder.version));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3450

LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3452

if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3453

if (si->ps.monitors & CRTC1_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3456

si->ps.slaved_tmds1 ? "slaved" : "master"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3458

si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.crtc1_screen.aspect));

src/add-ons/accelerants/nvidia/engine/nv_info.c

346

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3460

if (si->ps.monitors & CRTC2_TMDS)

src/add-ons/accelerants/nvidia/engine/nv_info.c

3463

si->ps.slaved_tmds2 ? "slaved" : "master"));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3465

si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.crtc2_screen.aspect));

src/add-ons/accelerants/nvidia/engine/nv_info.c

3467

LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors));

src/add-ons/accelerants/nvidia/engine/nv_info.c

358

if (si->ps.secondary_head)

src/add-ons/accelerants/nvidia/engine/nv_info.c

388

if (si->ps.card_type == NV28)

src/add-ons/accelerants/nvidia/engine/nv_info.c

391

ACCW(PT_NUMERATOR, (si->ps.std_engine_clock * 20));

src/add-ons/accelerants/nvidia/engine/nv_info.c

59

si->ps.pins_status = B_ERROR;

src/add-ons/accelerants/nvidia/engine/nv_info.c

63

rom = (uint8 *) si->rom_mirror;

src/add-ons/accelerants/nvidia/engine/nv_info.c

798

if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))

src/add-ons/accelerants/nvidia/engine/nv_info.c

805

si->ps.std_memory_clock = freq;

src/add-ons/accelerants/nvidia/engine/nv_info.c

810

si->ps.std_engine_clock = freq;

src/add-ons/accelerants/nvidia/engine/nv_info.c

905

((volatile uint32 *)si->framebuffer)[cnt] = data;

src/add-ons/accelerants/nvidia/engine/nv_info.c

908

if (((volatile uint32 *)si->framebuffer)[3] != data)

src/add-ons/accelerants/nvidia/engine/nv_info.c

925

((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] = data;

src/add-ons/accelerants/nvidia/engine/nv_info.c

927

if (((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] == data)

src/add-ons/accelerants/nvidia/engine/nv_info.c

931

((volatile uint32 *)si->framebuffer)[0] = data;

src/add-ons/accelerants/nvidia/engine/nv_info.c

932

if (((volatile uint32 *)si->framebuffer)[0] == data)

src/add-ons/accelerants/nvidia/engine/nv_info.c

951

((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] = data;

src/add-ons/accelerants/nvidia/engine/nv_info.c

953

if (((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] == data)

src/add-ons/accelerants/nvidia/engine/nv_info.c

972

((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] = data;

src/add-ons/accelerants/nvidia/engine/nv_info.c

974

if (((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] == data)

src/add-ons/accelerants/nvidia/engine/nv_proto.h

18

uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \

src/add-ons/accelerants/nvidia/engine/nv_proto.h

19

uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \

src/add-ons/accelerants/nvidia/engine/nv_support.c

28

si->vendor_id, si->device_id, si->bus, si->device, si->function,

src/add-ons/accelerants/radeon/Acceleration.c

104

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

148

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

182

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

238

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

265

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

311

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

336

if ( ai->si->asic >= rt_rv200 ) {

src/add-ons/accelerants/radeon/Acceleration.c

357

++ai->si->engine.count;

src/add-ons/accelerants/radeon/Acceleration.c

364

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/Acceleration.c

372

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/Acceleration.c

380

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/Acceleration.c

388

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/Acceleration.c

402

if ( ai->si->acc_dma ) {

src/add-ons/accelerants/radeon/Acceleration.c

423

((ai->si->memory[mt_local].virtual_addr_start + vc->fb_offset) >> 10) |

src/add-ons/accelerants/radeon/Acceleration.c

426

if ( ai->si->acc_dma ) {

src/add-ons/accelerants/radeon/Acceleration.c

491

ai->si->active_vc = vc->id;

src/add-ons/accelerants/radeon/Acceleration.c

56

++ai->si->engine.count;

src/add-ons/accelerants/radeon/CP.c

128

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

171

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

203

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

271

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

363

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

384

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

52

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.c

73

LOG1( si->log, _GetAvailRingBufferQueue, space );

src/add-ons/accelerants/radeon/CP.c

85

CP_info *cp = &ai->si->cp;

src/add-ons/accelerants/radeon/CP.h

67

return (uint32 *)(ai->mapped_memory[ai->si->cp.buffers.mem_type].data + ai->si->cp.buffers.mem_offset)

src/add-ons/accelerants/radeon/Cursor.c

122

RELEASE_BEN( ai->si->engine.lock );

src/add-ons/accelerants/radeon/Cursor.c

133

ACQUIRE_BEN( ai->si->engine.lock );

src/add-ons/accelerants/radeon/Cursor.c

145

RELEASE_BEN( ai->si->engine.lock );

src/add-ons/accelerants/radeon/Cursor.c

154

crtc_info *crtc = &ai->si->crtc[crtc_idx];

src/add-ons/accelerants/radeon/Cursor.c

223

crtc_info *crtc = &ai->si->crtc[crtc_idx];

src/add-ons/accelerants/radeon/Cursor.c

79

ACQUIRE_BEN( ai->si->engine.lock );

src/add-ons/accelerants/radeon/EngineManagment.c

102

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/EngineManagment.c

109

ACQUIRE_BEN( si->engine.lock)

src/add-ons/accelerants/radeon/EngineManagment.c

124

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/EngineManagment.c

133

st->counter = si->engine.count;

src/add-ons/accelerants/radeon/EngineManagment.c

136

RELEASE_BEN( ai->si->engine.lock )

src/add-ons/accelerants/radeon/EngineManagment.c

156

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/EngineManagment.c

163

st->counter = si->engine.count;

src/add-ons/accelerants/radeon/EngineManagment.c

165

SHOW_FLOW( 4, "got counter=%d", si->engine.count );

src/add-ons/accelerants/radeon/EngineManagment.c

185

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/EngineManagment.c

190

if ( !ai->si->acc_dma )

src/add-ons/accelerants/radeon/EngineManagment.c

201

((uint32 *)(ai->mapped_memory[si->cp.feedback.mem_type].data + si->cp.feedback.scratch_mem_offset))[0] );

src/add-ons/accelerants/radeon/EngineManagment.c

207

((uint32 *)(ai->mapped_memory[si->cp.feedback.mem_type].data + si->cp.feedback.scratch_mem_offset))[0]

src/add-ons/accelerants/radeon/EngineManagment.c

217

ACQUIRE_BEN( si->cp.lock );

src/add-ons/accelerants/radeon/EngineManagment.c

219

RELEASE_BEN( si->cp.lock );

src/add-ons/accelerants/radeon/EngineManagment.c

240

((uint32 *)(ai->mapped_memory[si->cp.feedback.mem_type].data + si->cp.feedback.scratch_mem_offset))[0] );

src/add-ons/accelerants/radeon/EngineManagment.c

65

if( ai->si->engine.count == ai->si->engine.written )

src/add-ons/accelerants/radeon/EngineManagment.c

68

if( ai->si->acc_dma ) {

src/add-ons/accelerants/radeon/EngineManagment.c

79

WRITE_IB_REG( RADEON_SCRATCH_REG0, ai->si->engine.count );

src/add-ons/accelerants/radeon/EngineManagment.c

81

ai->si->engine.written = ai->si->engine.count;

src/add-ons/accelerants/radeon/EngineManagment.c

90

ai->si->engine.written = ai->si->engine.count;

src/add-ons/accelerants/radeon/GetModeInfo.c

105

disp_entity* routes = &ai->si->routing;

src/add-ons/accelerants/radeon/GetModeInfo.c

153

return ai->si->crtc[crtcIndex].vblank;

src/add-ons/accelerants/radeon/GetModeInfo.c

56

uint32 clock_limit = ai->si->pll.max_pll_freq * 10;

src/add-ons/accelerants/radeon/GetModeInfo.c

73

fp_info *fpInfo = &ai->si->flatpanels[0];

src/add-ons/accelerants/radeon/GetModeInfo.c

74

disp_entity* routes = &ai->si->routing;

src/add-ons/accelerants/radeon/GetModeInfo.c

87

for (i = 0; i < ai->si->mode_count; ++i) {

src/add-ons/accelerants/radeon/InitAccelerant.c

114

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/InitAccelerant.c

133

ai->si = 0;

src/add-ons/accelerants/radeon/InitAccelerant.c

148

shared_info *si;

src/add-ons/accelerants/radeon/InitAccelerant.c

158

si = ai->si;

src/add-ons/accelerants/radeon/InitAccelerant.c

176

result = Radeon_CreateModeList( si );

src/add-ons/accelerants/radeon/InitAccelerant.c

181

(void)INIT_BEN( si->engine.lock, "Radeon engine" );

src/add-ons/accelerants/radeon/InitAccelerant.c

185

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/radeon/InitAccelerant.c

188

si->engine.written = -1;

src/add-ons/accelerants/radeon/InitAccelerant.c

191

si->overlay_mgr.token = 0;

src/add-ons/accelerants/radeon/InitAccelerant.c

192

si->overlay_mgr.inuse = 0;

src/add-ons/accelerants/radeon/InitAccelerant.c

195

si->active_overlay.crtc_idx = -1;

src/add-ons/accelerants/radeon/InitAccelerant.c

196

si->pending_overlay.crtc_idx = -1;

src/add-ons/accelerants/radeon/InitAccelerant.c

204

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/InitAccelerant.c

271

B_ANY_ADDRESS, B_READ_AREA, ai->si->mode_list_area );

src/add-ons/accelerants/radeon/InitAccelerant.c

316

di->memory = ai->si->memory[mt_local].size;

src/add-ons/accelerants/radeon/InitAccelerant.c

319

di->dac_speed = ai->si->pll.max_pll_freq;

src/add-ons/accelerants/radeon/InitAccelerant.c

56

ai->shared_info_area = clone_area( "Radeon shared info", (void **)&ai->si, B_ANY_ADDRESS,

src/add-ons/accelerants/radeon/InitAccelerant.c

64

B_READ_AREA | B_WRITE_AREA, ai->si->regs_area );

src/add-ons/accelerants/radeon/InitAccelerant.c

71

if( ai->si->memory[mt_PCI].area > 0 ) {

src/add-ons/accelerants/radeon/InitAccelerant.c

74

B_READ_AREA | B_WRITE_AREA, ai->si->memory[mt_PCI].area );

src/add-ons/accelerants/radeon/InitAccelerant.c

81

if( ai->si->memory[mt_AGP].area > 0 ) {

src/add-ons/accelerants/radeon/InitAccelerant.c

84

B_READ_AREA | B_WRITE_AREA, ai->si->memory[mt_AGP].area );

src/add-ons/accelerants/radeon/InitAccelerant.c

91

ai->mapped_memory[mt_nonlocal] = ai->mapped_memory[ai->si->nonlocal_type];

src/add-ons/accelerants/radeon/InitAccelerant.c

92

ai->mapped_memory[mt_local].data = ai->si->local_mem;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

144

Radeon_ProposeDisplayMode(shared_info *si, crtc_info *crtc,

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

155

fp_info *flatpanel = &si->flatpanels[crtc->flatpanel_port];

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

157

SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port );

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

393

if ((row_bytes * target->virtual_height) > si->memory[mt_local].size - 1024 )

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

394

target->virtual_height = (si->memory[mt_local].size - 1024) / row_bytes;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

418

return ai->si->mode_count;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

425

memcpy( dm, ai->mode_list, ai->si->mode_count * sizeof(display_mode) );

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

442

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

450

for( i = 0; i < si->mode_count; ++i ) {

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

482

dst = &ai->mode_list[si->mode_count];

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

490

if( Radeon_ProposeDisplayMode( si, &si->crtc[0],

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

491

&si->pll, dst, &low, &high ) == B_OK )

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

493

si->mode_count++;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

501

if( Radeon_ProposeDisplayMode( si, &si->crtc[1],

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

502

&si->pll, dst, &low, &high ) == B_OK )

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

504

si->mode_count++;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

541

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

543

fp_info *fp_info = &si->flatpanels[0]; //todo fix the hardcoding what about ext dvi?

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

590

status_t Radeon_CreateModeList( shared_info *si )

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

602

si->mode_list_area = create_area("Radeon accelerant mode info",

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

606

if( si->mode_list_area < B_OK )

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

607

return si->mode_list_area;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

609

si->mode_count = 0;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

619

ai->mode_list_area = si->mode_list_area;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

631

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

656

Radeon_VerifyMultiMode( vc, si, target );

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

669

result1 = Radeon_ProposeDisplayMode( si, &si->crtc[0],

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

670

&si->pll, target, low, high );

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

677

result2 = Radeon_ProposeDisplayMode( si, &si->crtc[1],

src/add-ons/accelerants/radeon/ProposeDisplayMode.c

678

&si->pll, target, low, high );

src/add-ons/accelerants/radeon/SetDisplayMode.c

110

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/SetDisplayMode.c

132

fp_info = &si->flatpanels[crtc->flatpanel_port];

src/add-ons/accelerants/radeon/SetDisplayMode.c

179

internal_tv_encoder = IS_INTERNAL_TV_OUT( si->tv_chip );

src/add-ons/accelerants/radeon/SetDisplayMode.c

189

&si->pll, tv_params, vc->tv_standard, internal_tv_encoder,

src/add-ons/accelerants/radeon/SetDisplayMode.c

232

Radeon_CalcCRTPLLDividers( &si->pll, mode, &dividers );

src/add-ons/accelerants/radeon/SetDisplayMode.c

236

if( (disp_devices & dd_lvds) != 0 && si->flatpanels[0].fixed_dividers ) {

src/add-ons/accelerants/radeon/SetDisplayMode.c

238

dividers.feedback = si->flatpanels[0].feedback_div;

src/add-ons/accelerants/radeon/SetDisplayMode.c

239

dividers.post_code = si->flatpanels[0].post_div;

src/add-ons/accelerants/radeon/SetDisplayMode.c

240

dividers.ref = si->flatpanels[0].ref_div;

src/add-ons/accelerants/radeon/SetDisplayMode.c

306

RELEASE_BEN( si->cp.lock );

src/add-ons/accelerants/radeon/SetDisplayMode.c

311

si->active_overlay.crtc_idx = -1;

src/add-ons/accelerants/radeon/SetDisplayMode.c

321

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/SetDisplayMode.c

327

| (si->num_crtc > 1 ? RADEON_CRTC2_VBLANK_MASK : 0);

src/add-ons/accelerants/radeon/SetDisplayMode.c

342

si->enable_virtual_irq = enable;

src/add-ons/accelerants/radeon/SetDisplayMode.c

351

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/SetDisplayMode.c

356

ACQUIRE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/SetDisplayMode.c

365

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/SetDisplayMode.c

377

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/SetDisplayMode.c

414

Radeon_VerifyMultiMode( vc, si, &mode );

src/add-ons/accelerants/radeon/SetDisplayMode.c

417

vc->independant_heads = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/SetDisplayMode.c

419

if( si->num_crtc > 1 )

src/add-ons/accelerants/radeon/SetDisplayMode.c

420

vc->independant_heads += vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/SetDisplayMode.c

450

vc->cursor.data = si->local_mem + vc->cursor.fb_offset;

src/add-ons/accelerants/radeon/SetDisplayMode.c

467

vc->fbc.frame_buffer = si->local_mem + vc->fb_offset;

src/add-ons/accelerants/radeon/SetDisplayMode.c

468

vc->fbc.frame_buffer_dma = (void *)((uintptr_t)si->framebuffer_pci + vc->fb_offset);

src/add-ons/accelerants/radeon/SetDisplayMode.c

490

si->crtc[0].active_displays = vc->controlled_displays;

src/add-ons/accelerants/radeon/SetDisplayMode.c

494

si->crtc[1].active_displays = vc->controlled_displays;

src/add-ons/accelerants/radeon/SetDisplayMode.c

499

vc->used_crtc[0] = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/SetDisplayMode.c

500

vc->used_crtc[1] = vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/SetDisplayMode.c

504

err1 = Radeon_SetMode( ai, &si->crtc[0], &mode, &tv_params );

src/add-ons/accelerants/radeon/SetDisplayMode.c

506

err2 = Radeon_SetMode( ai, &si->crtc[1], &mode, &tv_params );

src/add-ons/accelerants/radeon/SetDisplayMode.c

529

si->dac_cntl2 = INREG( ai->regs, RADEON_DAC_CNTL2 );

src/add-ons/accelerants/radeon/SetDisplayMode.c

537

si->active_vc = -1;

src/add-ons/accelerants/radeon/SetDisplayMode.c

559

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/crtc.c

165

moveOneDisplay( ai, &ai->si->crtc[0] );

src/add-ons/accelerants/radeon/crtc.c

167

moveOneDisplay( ai, &ai->si->crtc[1] );

src/add-ons/accelerants/radeon/crtc.c

178

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/crtc.c

181

ACQUIRE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/crtc.c

188

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/dpms.c

128

if (ai->si->asic >= rt_r200) {

src/add-ons/accelerants/radeon/dpms.c

137

if (ai->si->asic >= rt_r200) {

src/add-ons/accelerants/radeon/dpms.c

280

if( IS_INTERNAL_TV_OUT( ai->si->tv_chip )) {

src/add-ons/accelerants/radeon/dpms.c

284

Radeon_VIPWrite( ai, ai->si->theatre_channel, RADEON_TV_LINEAR_GAIN_SETTINGS,

src/add-ons/accelerants/radeon/dpms.c

293

crtc_info *crtc = &ai->si->crtc[crtc_idx];

src/add-ons/accelerants/radeon/dpms.c

69

snooze( ai->si->panel_pwr_delay * 1000 );

src/add-ons/accelerants/radeon/dpms.c

78

old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);

src/add-ons/accelerants/radeon/dpms.c

81

if( ai->si->is_mobility || ai->si->is_igp )

src/add-ons/accelerants/radeon/dpms.c

82

Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );

src/add-ons/accelerants/radeon/dpms.c

86

if( ai->si->is_mobility || ai->si->is_igp )

src/add-ons/accelerants/radeon/dpms.c

87

Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

135

if (ai->si->asic == rt_rv280) {

src/add-ons/accelerants/radeon/flat_panel.c

187

if (ai->si->tmds_pll[i].freq == 0)

src/add-ons/accelerants/radeon/flat_panel.c

189

if ((uint32)(fp_port->dot_clock) < ai->si->tmds_pll[i].freq) {

src/add-ons/accelerants/radeon/flat_panel.c

190

tmp = ai->si->tmds_pll[i].value ;

src/add-ons/accelerants/radeon/flat_panel.c

195

if (IS_R300_VARIANT || (ai->si->asic == rt_rv280)) {

src/add-ons/accelerants/radeon/flat_panel.c

199

values->tmds_pll_cntl = ai->si->tmds_pll_cntl & 0xfff00000;

src/add-ons/accelerants/radeon/flat_panel.c

206

values->tmds_trans_cntl = ai->si->tmds_transmitter_cntl

src/add-ons/accelerants/radeon/flat_panel.c

209

if (IS_R300_VARIANT || (ai->si->asic == rt_r200) || (ai->si->num_crtc == 1))

src/add-ons/accelerants/radeon/flat_panel.c

238

if( ai->si->asic >= rt_r200 )

src/add-ons/accelerants/radeon/flat_panel.c

253

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/flat_panel.c

276

if( si->asic == rt_r100 ) {

src/add-ons/accelerants/radeon/flat_panel.c

281

if ( ai->si->is_mobility ) {

src/add-ons/accelerants/radeon/flat_panel.c

295

old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);

src/add-ons/accelerants/radeon/flat_panel.c

298

if( ai->si->is_mobility || ai->si->is_igp )

src/add-ons/accelerants/radeon/flat_panel.c

301

Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );

src/add-ons/accelerants/radeon/flat_panel.c

314

snooze( ai->si->panel_pwr_delay * 1000 );

src/add-ons/accelerants/radeon/flat_panel.c

320

snooze( ai->si->panel_pwr_delay * 1000 );

src/add-ons/accelerants/radeon/flat_panel.c

325

if( ai->si->is_mobility || ai->si->is_igp ) {

src/add-ons/accelerants/radeon/flat_panel.c

327

Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );

src/add-ons/accelerants/radeon/impactv.c

530

if( ai->si->asic >= rt_r300 ) {

src/add-ons/accelerants/radeon/internal_tv_out.c

114

Radeon_OUTPLL( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/internal_tv_out.c

253

Radeon_INPLL( ai->regs, ai->si->asic, mapping->address );

src/add-ons/accelerants/radeon/monitor_detection.c

1011

ai->si->flatpanels[i].is_fp2 = true;

src/add-ons/accelerants/radeon/monitor_detection.c

1017

if (INREG(ai->regs, RADEON_FP_GEN_CNTL) & (1 << 7) || (!si->is_mobility)) {

src/add-ons/accelerants/radeon/monitor_detection.c

1031

ai->si->flatpanels[1].is_fp2 = FALSE;

src/add-ons/accelerants/radeon/monitor_detection.c

1038

if (si->num_crtc > 1) {

src/add-ons/accelerants/radeon/monitor_detection.c

1053

if (si->is_mobility && (INREG(ai->regs, RADEON_BIOS_4_SCRATCH) & 4)) {

src/add-ons/accelerants/radeon/monitor_detection.c

1061

if (si->is_mobility && (INREG(ai->regs, RADEON_FP2_GEN_CNTL) & RADEON_FP2_FPON)) {

src/add-ons/accelerants/radeon/monitor_detection.c

1079

panelInfoSwapEntity = ai->si->flatpanels[0];

src/add-ons/accelerants/radeon/monitor_detection.c

1080

ai->si->flatpanels[0] = ai->si->flatpanels[1];

src/add-ons/accelerants/radeon/monitor_detection.c

1081

ai->si->flatpanels[1] = panelInfoSwapEntity;

src/add-ons/accelerants/radeon/monitor_detection.c

1131

RELEASE_BEN(si->cp.lock);

src/add-ons/accelerants/radeon/monitor_detection.c

159

old_vclk_ecp_cntl = Radeon_INPLL(ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_detection.c

164

Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

169

Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

293

if (ai->si->is_mobility)

src/add-ons/accelerants/radeon/monitor_detection.c

296

switch (ai->si->asic) {

src/add-ons/accelerants/radeon/monitor_detection.c

508

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

512

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL, &tmp);

src/add-ons/accelerants/radeon/monitor_detection.c

524

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

527

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

530

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL, &tmp);

src/add-ons/accelerants/radeon/monitor_detection.c

563

if (ai->si->tv_chip != tc_external_rt1)

src/add-ons/accelerants/radeon/monitor_detection.c

567

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

571

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

575

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_PRE_DAC_MUX_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

577

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_MODULATOR_CNTL1,

src/add-ons/accelerants/radeon/monitor_detection.c

579

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

583

Radeon_VIPRead(ai, ai->si->theatre_channel, THEATRE_VIP_UV_ADR, &uv_adr);

src/add-ons/accelerants/radeon/monitor_detection.c

594

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

599

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MODULATOR_CNTL1,

src/add-ons/accelerants/radeon/monitor_detection.c

604

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

607

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL, 0);

src/add-ons/accelerants/radeon/monitor_detection.c

610

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_PRE_DAC_MUX_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

623

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

628

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_PRE_DAC_MUX_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

644

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

646

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_MODULATOR_CNTL1,

src/add-ons/accelerants/radeon/monitor_detection.c

648

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_PRE_DAC_MUX_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

650

Radeon_VIPWrite(ai, ai->si->theatre_channel, THEATRE_VIP_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

664

switch (ai->si->asic) {

src/add-ons/accelerants/radeon/monitor_detection.c

814

fp_info *fp = &ai->si->flatpanels[port];

src/add-ons/accelerants/radeon/monitor_detection.c

864

if (ai->si->is_atombios) {

src/add-ons/accelerants/radeon/monitor_detection.c

909

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/monitor_detection.c

911

disp_entity* routes = &si->routing;

src/add-ons/accelerants/radeon/monitor_detection.c

950

if (si->asic == rt_rs300) {

src/add-ons/accelerants/radeon/monitor_detection.c

961

} else if (si->num_crtc == 1) {

src/add-ons/accelerants/radeon/monitor_routing.c

133

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

224

if( !IS_INTERNAL_TV_OUT( ai->si->tv_chip )) {

src/add-ons/accelerants/radeon/monitor_routing.c

250

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

281

if( IS_INTERNAL_TV_OUT( ai->si->tv_chip )) {

src/add-ons/accelerants/radeon/monitor_routing.c

295

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

344

&& !IS_INTERNAL_TV_OUT( ai->si->tv_chip ))

src/add-ons/accelerants/radeon/monitor_routing.c

36

values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

368

&& !IS_INTERNAL_TV_OUT( ai->si->tv_chip ))

src/add-ons/accelerants/radeon/monitor_routing.c

37

values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

39

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

399

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

430

switch( ai->si->asic ) {

src/add-ons/accelerants/radeon/monitor_routing.c

457

if( ai->si->asic > rt_r100 ) {

src/add-ons/accelerants/radeon/monitor_routing.c

465

if( IS_INTERNAL_TV_OUT( ai->si->tv_chip ))

src/add-ons/accelerants/radeon/monitor_routing.c

485

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

491

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

496

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

606

if( IS_INTERNAL_TV_OUT( ai->si->tv_chip ) && (display_devices & (dd_stv | dd_ctv)) != 0 )

src/add-ons/accelerants/radeon/monitor_routing.c

616

else if( ai->si->num_crtc > 1 && crtc2_displays == 0 && vc->assigned_crtc[1] )

src/add-ons/accelerants/radeon/monitor_routing.c

620

else if( ai->si->num_crtc > 1 && (crtc2_displays & ~(dd_stv | dd_ctv)) == 0 && vc->assigned_crtc[1] )

src/add-ons/accelerants/radeon/monitor_routing.c

630

else if( ai->si->num_crtc > 1 && crtc2_displays == 0 && vc->assigned_crtc[1] )

src/add-ons/accelerants/radeon/monitor_routing.c

634

else if( ai->si->num_crtc > 1 && (crtc2_displays & ~(dd_stv | dd_ctv)) == 0 && vc->assigned_crtc[1] )

src/add-ons/accelerants/radeon/monitor_routing.c

654

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/monitor_routing.c

657

if (ai->si->settings.force_lcd) {

src/add-ons/accelerants/radeon/monitor_routing.c

66

if( ai->si->asic > rt_r100 ) {

src/add-ons/accelerants/radeon/monitor_routing.c

671

&si->crtc[0].chosen_displays, &si->crtc[1].chosen_displays );

src/add-ons/accelerants/radeon/monitor_routing.c

680

si->num_crtc,

src/add-ons/accelerants/radeon/monitor_routing.c

681

vc->assigned_crtc[0] ? "assigned" : "not assigned", si->crtc[0].chosen_displays,

src/add-ons/accelerants/radeon/monitor_routing.c

682

vc->assigned_crtc[0] ? "assigned" : "not assigned", si->crtc[1].chosen_displays );

src/add-ons/accelerants/radeon/monitor_routing.c

71

if( IS_INTERNAL_TV_OUT( ai->si->tv_chip ))

src/add-ons/accelerants/radeon/monitor_routing.c

86

display_devices[0] = ai->si->crtc[0].chosen_displays;

src/add-ons/accelerants/radeon/monitor_routing.c

91

display_devices[1] = ai->si->crtc[1].chosen_displays;

src/add-ons/accelerants/radeon/multimon.c

100

si->crtc[0].rel_y = 0;

src/add-ons/accelerants/radeon/multimon.c

104

si->crtc[1].rel_x = 0;

src/add-ons/accelerants/radeon/multimon.c

105

si->crtc[1].rel_y = 0;

src/add-ons/accelerants/radeon/multimon.c

126

si->crtc[1].rel_x = x;

src/add-ons/accelerants/radeon/multimon.c

127

si->crtc[1].rel_y = y;

src/add-ons/accelerants/radeon/multimon.c

129

si->crtc[0].rel_x = x;

src/add-ons/accelerants/radeon/multimon.c

130

si->crtc[0].rel_y = y;

src/add-ons/accelerants/radeon/multimon.c

54

void Radeon_VerifyMultiMode( virtual_card *vc, shared_info *si, display_mode *mode )

src/add-ons/accelerants/radeon/multimon.c

58

int num_usable_crtcs = vc->assigned_crtc[0] && si->crtc[0].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/multimon.c

60

if( si->num_crtc > 1 )

src/add-ons/accelerants/radeon/multimon.c

61

num_usable_crtcs += vc->assigned_crtc[1] && si->crtc[1].chosen_displays != dd_none;

src/add-ons/accelerants/radeon/multimon.c

91

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/multimon.c

99

si->crtc[0].rel_x = 0;

src/add-ons/accelerants/radeon/overlay.c

1001

ai->si->active_overlay.on = ai->si->pending_overlay.on;

src/add-ons/accelerants/radeon/overlay.c

1003

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

1006

if ( ai->si->acc_dma )

src/add-ons/accelerants/radeon/overlay.c

101

Radeon_OUTPLLP( regs, si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/overlay.c

1010

offset = si->pending_overlay.on->mem_offset + si->active_overlay.rel_offset;

src/add-ons/accelerants/radeon/overlay.c

1014

si->overlay_mgr.auto_flip_reg ^= RADEON_OV0_SOFT_EOF_TOGGLE;

src/add-ons/accelerants/radeon/overlay.c

1015

WRITE_IB_REG( RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

1020

offset = si->pending_overlay.on->mem_offset + si->active_overlay.rel_offset;

src/add-ons/accelerants/radeon/overlay.c

1024

si->overlay_mgr.auto_flip_reg ^= RADEON_OV0_SOFT_EOF_TOGGLE;

src/add-ons/accelerants/radeon/overlay.c

1025

OUTREG( ai->regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

1027

ai->si->active_overlay.on = ai->si->pending_overlay.on;

src/add-ons/accelerants/radeon/overlay.c

105

if ((si->asic == rt_rs100) ||

src/add-ons/accelerants/radeon/overlay.c

106

(si->asic == rt_rs200) ||

src/add-ons/accelerants/radeon/overlay.c

1066

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

107

(si->asic == rt_rs300)) {

src/add-ons/accelerants/radeon/overlay.c

108

Radeon_OUTPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/overlay.c

1082

if ( si->pending_overlay.on == NULL )

src/add-ons/accelerants/radeon/overlay.c

1086

if ((uintptr_t)si->pending_overlay.ot != si->overlay_mgr.token )

src/add-ons/accelerants/radeon/overlay.c

109

(Radeon_INPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL) | (1<<18)));

src/add-ons/accelerants/radeon/overlay.c

1093

area0 = getIntersectArea( ai, &si->pending_overlay.ow, &si->crtc[0] );

src/add-ons/accelerants/radeon/overlay.c

1094

area1 = getIntersectArea( ai, &si->pending_overlay.ow, &si->crtc[0] );

src/add-ons/accelerants/radeon/overlay.c

1118

si->pending_overlay.crtc_idx = crtc_idx;

src/add-ons/accelerants/radeon/overlay.c

112

si->active_overlay.crtc_idx = si->pending_overlay.crtc_idx;

src/add-ons/accelerants/radeon/overlay.c

1121

if( si->active_overlay.crtc_idx != si->pending_overlay.crtc_idx ) {

src/add-ons/accelerants/radeon/overlay.c

1125

if( si->active_overlay.ob.space != si->pending_overlay.ob.space ) {

src/add-ons/accelerants/radeon/overlay.c

1129

if( memcmp( &si->active_overlay.ow, &si->pending_overlay.ow, sizeof( si->active_overlay.ow )) != 0 ||

src/add-ons/accelerants/radeon/overlay.c

1130

memcmp( &si->active_overlay.ov, &si->pending_overlay.ov, sizeof( si->active_overlay.ov )) != 0 ||

src/add-ons/accelerants/radeon/overlay.c

1131

si->active_overlay.h_display_start != vc->mode.h_display_start ||

src/add-ons/accelerants/radeon/overlay.c

1132

si->active_overlay.v_display_start != vc->mode.v_display_start ||

src/add-ons/accelerants/radeon/overlay.c

1133

si->active_overlay.ob.width != si->pending_overlay.ob.width ||

src/add-ons/accelerants/radeon/overlay.c

1134

si->active_overlay.ob.height != si->pending_overlay.ob.height ||

src/add-ons/accelerants/radeon/overlay.c

1135

si->active_overlay.ob.bytes_per_row != si->pending_overlay.ob.bytes_per_row )

src/add-ons/accelerants/radeon/overlay.c

1138

else if( si->active_overlay.on != si->pending_overlay.on )

src/add-ons/accelerants/radeon/overlay.c

115

si->active_overlay.ob.space = -1;

src/add-ons/accelerants/radeon/overlay.c

118

si->active_overlay.ob.width = -1;

src/add-ons/accelerants/radeon/overlay.c

163

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

190

switch( si->pending_overlay.ob.space ) {

src/add-ons/accelerants/radeon/overlay.c

270

si->active_overlay.ob.space = si->pending_overlay.ob.space;

src/add-ons/accelerants/radeon/overlay.c

474

if (ai->si->asic == rt_r200 || ai->si->asic >= rt_r300)

src/add-ons/accelerants/radeon/overlay.c

533

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

535

overlay_info *overlay = &si->pending_overlay;

src/add-ons/accelerants/radeon/overlay.c

537

crtc_info *crtc = &si->crtc[crtc_idx];

src/add-ons/accelerants/radeon/overlay.c

57

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

66

si->overlay_mgr.auto_flip_reg = RADEON_OV0_VID_PORT_SELECT_SOFTWARE;

src/add-ons/accelerants/radeon/overlay.c

69

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

706

si->active_overlay.rel_offset = (src_top >> 16) * node->buffer.bytes_per_row +

src/add-ons/accelerants/radeon/overlay.c

708

offset = node->mem_offset + si->active_overlay.rel_offset;

src/add-ons/accelerants/radeon/overlay.c

710

SHOW_FLOW( 3, "rel_offset=%x", si->active_overlay.rel_offset );

src/add-ons/accelerants/radeon/overlay.c

744

v_ratio = si->flatpanels[crtc->flatpanel_port].v_ratio >> (FIX_SHIFT - 16);

src/add-ons/accelerants/radeon/overlay.c

88

if( !std_gamma[i].r200_or_above || si->asic >= rt_r200 ) {

src/add-ons/accelerants/radeon/overlay.c

907

(( ai->si->asic >= rt_r200) ? R200_SCALER_TEMPORAL_DEINT : 0));

src/add-ons/accelerants/radeon/overlay.c

911

si->overlay_mgr.auto_flip_reg ^= RADEON_OV0_SOFT_EOF_TOGGLE;

src/add-ons/accelerants/radeon/overlay.c

914

si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

919

ai->si->active_overlay.on = ai->si->pending_overlay.on;

src/add-ons/accelerants/radeon/overlay.c

920

ai->si->active_overlay.ow = ai->si->pending_overlay.ow;

src/add-ons/accelerants/radeon/overlay.c

921

ai->si->active_overlay.ov = ai->si->pending_overlay.ov;

src/add-ons/accelerants/radeon/overlay.c

922

ai->si->active_overlay.ob = ai->si->pending_overlay.ob;

src/add-ons/accelerants/radeon/overlay.c

923

ai->si->active_overlay.h_display_start = vc->mode.h_display_start;

src/add-ons/accelerants/radeon/overlay.c

924

ai->si->active_overlay.v_display_start = vc->mode.v_display_start;

src/add-ons/accelerants/radeon/overlay.c

944

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

949

si->active_overlay.on = NULL;

src/add-ons/accelerants/radeon/overlay.c

950

si->active_overlay.prev_on = NULL;

src/add-ons/accelerants/radeon/overlay.c

951

si->pending_overlay.on = NULL;

src/add-ons/accelerants/radeon/overlay.c

955

si->active_overlay.crtc_idx = -1;

src/add-ons/accelerants/radeon/overlay.c

96

if( si->crtc[crtc_idx].mode.timing.pixel_clock < 175000 )

src/add-ons/accelerants/radeon/overlay.c

964

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay.c

969

offset = si->pending_overlay.on->mem_offset + si->active_overlay.rel_offset;

src/add-ons/accelerants/radeon/overlay.c

994

si->overlay_mgr.auto_flip_reg ^= RADEON_OV0_SOFT_EOF_TOGGLE;

src/add-ons/accelerants/radeon/overlay.c

996

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay_management.c

130

ACQUIRE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

151

buffer->buffer = si->local_mem + am.offset;

src/add-ons/accelerants/radeon/overlay_management.c

152

buffer->buffer_dma = (void *) ((unsigned long) si->framebuffer_pci + am.offset);

src/add-ons/accelerants/radeon/overlay_management.c

162

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

171

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

180

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay_management.c

189

if( si->active_overlay.on == node || si->active_overlay.prev_on )

src/add-ons/accelerants/radeon/overlay_management.c

204

ACQUIRE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

215

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

295

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay_management.c

300

if( atomic_or( &si->overlay_mgr.inuse, 1 ) != 0 ) {

src/add-ons/accelerants/radeon/overlay_management.c

309

return (void *)++si->overlay_mgr.token;

src/add-ons/accelerants/radeon/overlay_management.c

317

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay_management.c

321

if( (void *)si->overlay_mgr.token != ot )

src/add-ons/accelerants/radeon/overlay_management.c

324

if( si->overlay_mgr.inuse == 0 )

src/add-ons/accelerants/radeon/overlay_management.c

327

if( si->active_overlay.on )

src/add-ons/accelerants/radeon/overlay_management.c

330

si->overlay_mgr.inuse = 0;

src/add-ons/accelerants/radeon/overlay_management.c

343

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/overlay_management.c

348

if ( (uintptr_t)ot != si->overlay_mgr.token )

src/add-ons/accelerants/radeon/overlay_management.c

351

if ( !si->overlay_mgr.inuse )

src/add-ons/accelerants/radeon/overlay_management.c

363

ACQUIRE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

366

si->pending_overlay.ot = ot;

src/add-ons/accelerants/radeon/overlay_management.c

367

si->pending_overlay.ob = *ob;

src/add-ons/accelerants/radeon/overlay_management.c

368

si->pending_overlay.ow = *ow;

src/add-ons/accelerants/radeon/overlay_management.c

369

si->pending_overlay.ov = *ov;

src/add-ons/accelerants/radeon/overlay_management.c

371

si->pending_overlay.on = (overlay_buffer_node *)((char *)ob - offsetof( overlay_buffer_node, buffer ));

src/add-ons/accelerants/radeon/overlay_management.c

375

RELEASE_BEN( si->engine.lock );

src/add-ons/accelerants/radeon/overlay_management.c

72

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/palette.c

106

(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );

src/add-ons/accelerants/radeon/palette.c

26

if ( ai->si->acc_dma ) {

src/add-ons/accelerants/radeon/palette.c

31

(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );

src/add-ons/accelerants/radeon/palette.c

43

(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );

src/add-ons/accelerants/radeon/palette.c

86

if ( ai->si->acc_dma ) {

src/add-ons/accelerants/radeon/palette.c

91

(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );

src/add-ons/accelerants/radeon/pll.c

29

if( (Radeon_INPLL( ai->regs, ai->si->asic, crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV )

src/add-ons/accelerants/radeon/pll.c

40

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/pll.c

458

radeon_type asic = ai->si->asic;

src/add-ons/accelerants/radeon/pll.c

483

if( ai->si->new_pll && crtc_idx == 0 ) {

src/add-ons/accelerants/radeon/radeon_accelerant.h

42

shared_info *si; // info shared between accelerants

src/add-ons/accelerants/radeon/radeon_accelerant.h

86

void Radeon_VerifyMultiMode( virtual_card *vc, shared_info *si, display_mode *mode );

src/add-ons/accelerants/radeon/radeon_accelerant.h

96

status_t Radeon_CreateModeList( shared_info *si );

src/add-ons/accelerants/radeon/theatre_out.c

110

Radeon_VIPWrite( ai, ai->si->theatre_channel, mapping->address,

src/add-ons/accelerants/radeon/theatre_out.c

128

Radeon_VIPWrite( ai, ai->si->theatre_channel,

src/add-ons/accelerants/radeon/theatre_out.c

136

Radeon_VIPRead( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_RD_WT_CNTL, &status );

src/add-ons/accelerants/radeon/theatre_out.c

142

Radeon_VIPWrite( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_RD_WT_CNTL, 0);

src/add-ons/accelerants/radeon/theatre_out.c

143

Radeon_VIPRead( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_READ_DATA, &res );

src/add-ons/accelerants/radeon/theatre_out.c

159

Radeon_VIPWrite( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_WRITE_DATA, value);

src/add-ons/accelerants/radeon/theatre_out.c

160

Radeon_VIPWrite( ai, ai->si->theatre_channel,

src/add-ons/accelerants/radeon/theatre_out.c

168

Radeon_VIPRead( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_RD_WT_CNTL, &status );

src/add-ons/accelerants/radeon/theatre_out.c

174

Radeon_VIPWrite( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_RD_WT_CNTL, 0 );

src/add-ons/accelerants/radeon/theatre_out.c

200

Radeon_VIPWrite( ai, ai->si->theatre_channel, THEATRE_VIP_MASTER_CNTL,

src/add-ons/accelerants/radeon/theatre_out.c

224

Radeon_VIPRead( ai, ai->si->theatre_channel, mapping->address,

src/add-ons/accelerants/radeon/theatre_out.c

250

shared_info *si = ai->si;

src/add-ons/accelerants/radeon/theatre_out.c

254

switch( si->tv_chip ) {

src/add-ons/accelerants/radeon/theatre_out.c

261

si->tv_chip = tc_none;

src/add-ons/accelerants/radeon/theatre_out.c

264

si->theatre_channel = channel;

src/add-ons/accelerants/s3/accel.cpp

100

result = si.engineLock.Init("ATI engine lock");

src/add-ons/accelerants/s3/accel.cpp

107

si.bAccelerantInUse = true;

src/add-ons/accelerants/s3/accel.cpp

207

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/accel.cpp

211

strcpy(adi->chipset, si.chipName);

src/add-ons/accelerants/s3/accel.cpp

213

adi->memory = si.maxFrameBufferSize;

src/add-ons/accelerants/s3/accel.cpp

89

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/accel.cpp

91

TRACE("Vendor ID: 0x%X, Device ID: 0x%X\n", si.vendorID, si.deviceID);

src/add-ons/accelerants/s3/accel.cpp

95

if (si.bAccelerantInUse) {

src/add-ons/accelerants/s3/cursor.cpp

25

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/cursor.cpp

26

si.cursorHotX = hot_x;

src/add-ons/accelerants/s3/cursor.cpp

27

si.cursorHotY = hot_y;

src/add-ons/accelerants/s3/cursor.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/cursor.cpp

48

DisplayModeEx& dm = si.displayMode;

src/add-ons/accelerants/s3/cursor.cpp

75

x -= (hds + si.cursorHotX);

src/add-ons/accelerants/s3/cursor.cpp

76

y -= (vds + si.cursorHotY);

src/add-ons/accelerants/s3/hooks.cpp

17

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/hooks.cpp

52

return (void*)(si.bDisableHdwCursor ? NULL : SetCursorShape);

src/add-ons/accelerants/s3/hooks.cpp

54

return (void*)(si.bDisableHdwCursor ? NULL : MoveCursor);

src/add-ons/accelerants/s3/hooks.cpp

56

return (void*)(si.bDisableHdwCursor ? NULL : gInfo.ShowCursor);

src/add-ons/accelerants/s3/hooks.cpp

68

return (void*)(si.bDisableAccelDraw ? NULL : gInfo.ScreenToScreenBlit);

src/add-ons/accelerants/s3/hooks.cpp

70

return (void*)(si.bDisableAccelDraw ? NULL : gInfo.FillRectangle);

src/add-ons/accelerants/s3/hooks.cpp

72

return (void*)(si.bDisableAccelDraw ? NULL : gInfo.InvertRectangle);

src/add-ons/accelerants/s3/hooks.cpp

74

return (void*)(si.bDisableAccelDraw ? NULL : gInfo.FillSpan);

src/add-ons/accelerants/s3/mode.cpp

179

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

197

for (uint32 j = 0; j < si.colorSpaceCount; j++) {

src/add-ons/accelerants/s3/mode.cpp

198

if (mode->space == uint32(si.colorSpaces[j])) {

src/add-ons/accelerants/s3/mode.cpp

218

if (si.displayType == MT_LCD && si.panelX > 0 && si.panelY > 0

src/add-ons/accelerants/s3/mode.cpp

219

&& (mode->timing.h_display > si.panelX

src/add-ons/accelerants/s3/mode.cpp

220

|| mode->timing.v_display > si.panelY)) {

src/add-ons/accelerants/s3/mode.cpp

232

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

241

si.bHaveEDID = false;

src/add-ons/accelerants/s3/mode.cpp

243

if (si.displayType != MT_LCD) {

src/add-ons/accelerants/s3/mode.cpp

245

si.bHaveEDID = getEdid(si.edidInfo);

src/add-ons/accelerants/s3/mode.cpp

247

if ( ! si.bHaveEDID) {

src/add-ons/accelerants/s3/mode.cpp

257

edid_decode(&si.edidInfo, &ged.rawEdid); // decode & save EDID info

src/add-ons/accelerants/s3/mode.cpp

258

si.bHaveEDID = true;

src/add-ons/accelerants/s3/mode.cpp

263

if (si.bHaveEDID) {

src/add-ons/accelerants/s3/mode.cpp

265

edid_dump(&(si.edidInfo));

src/add-ons/accelerants/s3/mode.cpp

277

si.bHaveEDID ? &si.edidInfo : NULL,

src/add-ons/accelerants/s3/mode.cpp

278

NULL, 0, si.colorSpaces, si.colorSpaceCount,

src/add-ons/accelerants/s3/mode.cpp

284

si.modeArea = gInfo.modeListArea = listArea;

src/add-ons/accelerants/s3/mode.cpp

285

si.modeCount = count;

src/add-ons/accelerants/s3/mode.cpp

329

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

345

if (mode.timing.h_display == 1400 && (si.chipType == S3_PROSAVAGE

src/add-ons/accelerants/s3/mode.cpp

346

|| si.chipType == S3_PROSAVAGE_DDR

src/add-ons/accelerants/s3/mode.cpp

347

|| si.chipType == S3_TWISTER

src/add-ons/accelerants/s3/mode.cpp

348

|| si.chipType == S3_SUPERSAVAGE

src/add-ons/accelerants/s3/mode.cpp

349

|| si.chipType == S3_SAVAGE2000)) {

src/add-ons/accelerants/s3/mode.cpp

385

si.displayMode = mode;

src/add-ons/accelerants/s3/mode.cpp

445

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

447

pFBC->frame_buffer = (void*)((addr_t)si.videoMemAddr + si.frameBufferOffset);

src/add-ons/accelerants/s3/mode.cpp

448

pFBC->frame_buffer_dma = (void*)((addr_t)si.videoMemPCI + si.frameBufferOffset);

src/add-ons/accelerants/s3/mode.cpp

449

uint32 bytesPerPixel = (si.displayMode.bpp + 7) / 8;

src/add-ons/accelerants/s3/mode.cpp

450

pFBC->bytes_per_row = si.displayMode.virtual_width * bytesPerPixel;

src/add-ons/accelerants/s3/mode.cpp

499

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

501

if (si.displayType == MT_LCD) {

src/add-ons/accelerants/s3/mode.cpp

502

display_mode* mode = FindDisplayMode(si.panelX, si.panelY, 60, 0);

src/add-ons/accelerants/s3/mode.cpp

520

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/mode.cpp

522

if ( ! si.bHaveEDID)

src/add-ons/accelerants/s3/mode.cpp

528

memcpy(info, &si.edidInfo, sizeof(struct edid1_info));

src/add-ons/accelerants/s3/savage_cursor.cpp

108

uint8* fbCursor = (uint8*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/savage_cursor.cpp

117

if (S3_SAVAGE4_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/savage_cursor.cpp

128

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/savage_cursor.cpp

129

WriteCrtcReg(0x4c, (0xff00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/savage_cursor.cpp

47

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_cursor.cpp

49

if (S3_SAVAGE4_SERIES(si.chipType))

src/add-ons/accelerants/s3/savage_cursor.cpp

85

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_cursor.cpp

92

uint16* fbCursor16 = (uint16*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/savage_dpms.cpp

100

} else if (si.displayType == MT_LCD || si.displayType == MT_DFP) {

src/add-ons/accelerants/s3/savage_dpms.cpp

38

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_dpms.cpp

41

if (si.displayType == MT_CRT) {

src/add-ons/accelerants/s3/savage_dpms.cpp

58

} else if (si.displayType == MT_LCD || si.displayType == MT_DFP) {

src/add-ons/accelerants/s3/savage_dpms.cpp

73

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_dpms.cpp

75

TRACE("Savage_SetDPMSMode() mode: %d, display type: %d\n", dpmsMode, si.displayType);

src/add-ons/accelerants/s3/savage_dpms.cpp

77

if (si.displayType == MT_CRT) {

src/add-ons/accelerants/s3/savage_edid.cpp

57

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_edid.cpp

61

switch (si.chipType) {

src/add-ons/accelerants/s3/savage_init.cpp

101

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_init.cpp

139

si.panelX = panelX;

src/add-ons/accelerants/s3/savage_init.cpp

140

si.panelY = panelY;

src/add-ons/accelerants/s3/savage_init.cpp

142

si.displayType = MT_CRT;

src/add-ons/accelerants/s3/savage_init.cpp

152

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_init.cpp

160

if (si.chipType >= S3_SAVAGE4)

src/add-ons/accelerants/s3/savage_init.cpp

181

switch (si.chipType) {

src/add-ons/accelerants/s3/savage_init.cpp

223

if (si.chipType == S3_SAVAGE_MX && ramSizeMB > 8)

src/add-ons/accelerants/s3/savage_init.cpp

231

si.videoMemSize = usableMB * 1024 * 1024;

src/add-ons/accelerants/s3/savage_init.cpp

236

si.cobSizeIndex = 7;

src/add-ons/accelerants/s3/savage_init.cpp

242

si.cobOffset = (si.videoMemSize - cobSize) & ~0x1ffff; // align cob to 128k

src/add-ons/accelerants/s3/savage_init.cpp

243

si.cursorOffset = (si.cobOffset - CURSOR_BYTES) & ~0xfff; // align to 4k boundary

src/add-ons/accelerants/s3/savage_init.cpp

244

si.frameBufferOffset = 0;

src/add-ons/accelerants/s3/savage_init.cpp

245

si.maxFrameBufferSize = si.cursorOffset - si.frameBufferOffset;

src/add-ons/accelerants/s3/savage_init.cpp

247

TRACE("cobSizeIndex: %d cobSize: %d cobOffset: 0x%x\n", si.cobSizeIndex, cobSize, si.cobOffset);

src/add-ons/accelerants/s3/savage_init.cpp

248

TRACE("cursorOffset: 0x%x frameBufferOffset: 0x%x\n", si.cursorOffset, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_init.cpp

260

if (si.chipType == S3_SAVAGE4) {

src/add-ons/accelerants/s3/savage_init.cpp

268

if (S3_SAVAGE_MOBILE_SERIES(si.chipType) || S3_MOBILE_TWISTER_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/savage_init.cpp

269

si.displayType = MT_LCD;

src/add-ons/accelerants/s3/savage_init.cpp

273

si.displayType = MT_DFP;

src/add-ons/accelerants/s3/savage_init.cpp

275

si.displayType = MT_CRT;

src/add-ons/accelerants/s3/savage_init.cpp

277

TRACE("Display Type: %d\n", si.displayType);

src/add-ons/accelerants/s3/savage_init.cpp

287

si.mclk = ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;

src/add-ons/accelerants/s3/savage_init.cpp

289

TRACE("Detected current MCLK value of %1.3f MHz\n", si.mclk / 1000.0);

src/add-ons/accelerants/s3/savage_init.cpp

293

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/s3/savage_init.cpp

294

si.colorSpaces[1] = B_RGB16;

src/add-ons/accelerants/s3/savage_init.cpp

295

si.colorSpaces[2] = B_RGB32;

src/add-ons/accelerants/s3/savage_init.cpp

296

si.colorSpaceCount = 3;

src/add-ons/accelerants/s3/savage_init.cpp

298

si.bDisableHdwCursor = false; // allow use of hardware cursor

src/add-ons/accelerants/s3/savage_init.cpp

299

si.bDisableAccelDraw = false; // allow use of accelerated drawing functions

src/add-ons/accelerants/s3/savage_mode.cpp

137

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

156

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

157

WriteReg32(PRI_STREAM_FBUF_ADDR1, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

158

WriteReg32(PRI_STREAM2_FBUF_ADDR0, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

159

WriteReg32(PRI_STREAM2_FBUF_ADDR1, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

192

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

229

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

231

WriteReg32(PRI_STREAM2_FBUF_ADDR0, (si.frameBufferOffset & 0xfffffffc) | 0x80000000);

src/add-ons/accelerants/s3/savage_mode.cpp

232

WriteReg32(PRI_STREAM2_FBUF_ADDR1, si.frameBufferOffset & 0xfffffffc);

src/add-ons/accelerants/s3/savage_mode.cpp

242

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

246

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

247

WriteReg32(PRI_STREAM2_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

280

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

317

si.globalBitmapDesc = mode.timing.h_display | (mode.bpp << 16)

src/add-ons/accelerants/s3/savage_mode.cpp

325

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

336

switch (si.chipType) {

src/add-ons/accelerants/s3/savage_mode.cpp

346

WriteReg32(0x48C14, (si.cobOffset >> 11) | (si.cobSizeIndex << 29));

src/add-ons/accelerants/s3/savage_mode.cpp

378

WriteReg32(0x48C18, (si.cobOffset >> 7) | (si.cobSizeIndex));

src/add-ons/accelerants/s3/savage_mode.cpp

39

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

42

if (si.chipType == S3_SAVAGE4)

src/add-ons/accelerants/s3/savage_mode.cpp

509

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

518

if ( ! S3_SAVAGE_MOBILE_SERIES(si.chipType))

src/add-ons/accelerants/s3/savage_mode.cpp

532

if (si.chipType == S3_PROSAVAGE || si.chipType == S3_TWISTER) {

src/add-ons/accelerants/s3/savage_mode.cpp

542

if (si.chipType == S3_SAVAGE_MX)

src/add-ons/accelerants/s3/savage_mode.cpp

559

if (S3_SAVAGE_MOBILE_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/savage_mode.cpp

611

if (si.chipType == S3_SAVAGE4)

src/add-ons/accelerants/s3/savage_mode.cpp

616

if ( ! (S3_SAVAGE_MOBILE_SERIES(si.chipType) && si.displayType == MT_LCD)) {

src/add-ons/accelerants/s3/savage_mode.cpp

662

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

667

if (mode.bpp == 16 && si.chipType == S3_SAVAGE_3D)

src/add-ons/accelerants/s3/savage_mode.cpp

679

if ((si.chipType == S3_SAVAGE2000) && (dclk >= 230000))

src/add-ons/accelerants/s3/savage_mode.cpp

686

if (S3_SAVAGE_MOBILE_SERIES(si.chipType)

src/add-ons/accelerants/s3/savage_mode.cpp

687

|| ((si.chipType == S3_SAVAGE2000) && (dclk >= 230000)))

src/add-ons/accelerants/s3/savage_mode.cpp

694

if (S3_SAVAGE_MOBILE_SERIES(si.chipType)

src/add-ons/accelerants/s3/savage_mode.cpp

695

|| ((si.chipType == S3_SAVAGE2000) && (dclk >= 230000)))

src/add-ons/accelerants/s3/savage_mode.cpp

757

if (S3_SAVAGE_MOBILE_SERIES(si.chipType))

src/add-ons/accelerants/s3/savage_mode.cpp

802

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/savage_mode.cpp

807

address += si.frameBufferOffset;

src/add-ons/accelerants/s3/savage_mode.cpp

809

switch (si.chipType) {

src/add-ons/accelerants/s3/trio64_cursor.cpp

62

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/trio64_cursor.cpp

69

uint16* fbCursor16 = (uint16*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/trio64_cursor.cpp

85

uint8* fbCursor = (uint8*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/trio64_cursor.cpp

96

WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/trio64_cursor.cpp

97

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/trio64_init.cpp

101

if (si.chipType == S3_TRIO64_V2) {

src/add-ons/accelerants/s3/trio64_init.cpp

116

si.videoMemSize = ramSizeMB * 1024 * 1024;

src/add-ons/accelerants/s3/trio64_init.cpp

117

si.cursorOffset = si.videoMemSize - CURSOR_BYTES; // put cursor at end of video memory

src/add-ons/accelerants/s3/trio64_init.cpp

118

si.frameBufferOffset = 0;

src/add-ons/accelerants/s3/trio64_init.cpp

119

si.maxFrameBufferSize = si.videoMemSize - CURSOR_BYTES;

src/add-ons/accelerants/s3/trio64_init.cpp

129

si.mclk = ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;

src/add-ons/accelerants/s3/trio64_init.cpp

131

TRACE("MCLK value: %1.3f MHz\n", si.mclk / 1000.0);

src/add-ons/accelerants/s3/trio64_init.cpp

135

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/s3/trio64_init.cpp

136

si.colorSpaces[1] = B_RGB16;

src/add-ons/accelerants/s3/trio64_init.cpp

137

si.colorSpaceCount = 2;

src/add-ons/accelerants/s3/trio64_init.cpp

139

si.bDisableHdwCursor = false; // allow use of hardware cursor

src/add-ons/accelerants/s3/trio64_init.cpp

140

si.bDisableAccelDraw = false; // allow use of accelerated drawing functions

src/add-ons/accelerants/s3/trio64_init.cpp

69

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/trio64_init.cpp

71

if (si.chipType == S3_TRIO64 && mode->timing.h_display >= 1600)

src/add-ons/accelerants/s3/trio64_init.cpp

83

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/trio64_mode.cpp

111

if (si.chipType == S3_TRIO64_V2)

src/add-ons/accelerants/s3/trio64_mode.cpp

170

si.bDisableAccelDraw = bDisableAccelFuncs;

src/add-ons/accelerants/s3/trio64_mode.cpp

255

WriteReg16(MULTIFUNC_CNTL, SCISSORS_B | ((si.maxFrameBufferSize / mode.bytesPerRow) - 1));

src/add-ons/accelerants/s3/trio64_mode.cpp

78

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/trio64_mode.cpp

83

uint32 videoRamMB = si.videoMemSize / (1024 * 1024); // MB's of video RAM

src/add-ons/accelerants/s3/virge_cursor.cpp

62

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_cursor.cpp

69

uint16* fbCursor16 = (uint16*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/virge_cursor.cpp

85

uint8* fbCursor = (uint8*)((addr_t)si.videoMemAddr + si.cursorOffset);

src/add-ons/accelerants/s3/virge_cursor.cpp

96

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/virge_cursor.cpp

97

WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/virge_edid.cpp

87

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_edid.cpp

91

if (si.chipType == S3_TRIO_3D_2X) {

src/add-ons/accelerants/s3/virge_init.cpp

101

if (si.chipType == S3_TRIO_3D)

src/add-ons/accelerants/s3/virge_init.cpp

114

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_init.cpp

140

} else if (si.chipType == S3_TRIO_3D_2X) {

src/add-ons/accelerants/s3/virge_init.cpp

155

} else if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_init.cpp

165

} else if (si.chipType == S3_VIRGE_GX2 || S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_init.cpp

193

si.videoMemSize = ramSizeMB * 1024 * 1024;

src/add-ons/accelerants/s3/virge_init.cpp

194

si.cursorOffset = si.videoMemSize - CURSOR_BYTES; // put cursor at end of video memory

src/add-ons/accelerants/s3/virge_init.cpp

195

si.frameBufferOffset = 0;

src/add-ons/accelerants/s3/virge_init.cpp

196

si.maxFrameBufferSize = si.videoMemSize - CURSOR_BYTES;

src/add-ons/accelerants/s3/virge_init.cpp

206

si.mclk = ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;

src/add-ons/accelerants/s3/virge_init.cpp

208

TRACE("Detected current MCLK value of %1.3f MHz\n", si.mclk / 1000.0);

src/add-ons/accelerants/s3/virge_init.cpp

210

if (S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_init.cpp

211

si.displayType = ((ReadSeqReg(0x31) & 0x10) ? MT_LCD : MT_CRT);

src/add-ons/accelerants/s3/virge_init.cpp

212

si.panelX = (ReadSeqReg(0x61) + ((ReadSeqReg(0x66) & 0x02) << 7) + 1) * 8;

src/add-ons/accelerants/s3/virge_init.cpp

213

si.panelY = ReadSeqReg(0x69) + ((ReadSeqReg(0x6e) & 0x70) << 4) + 1;

src/add-ons/accelerants/s3/virge_init.cpp

215

TRACE("%dx%d LCD panel detected %s\n", si.panelX, si.panelY,

src/add-ons/accelerants/s3/virge_init.cpp

216

si.displayType == MT_LCD ? "and active" : "but not active");

src/add-ons/accelerants/s3/virge_init.cpp

218

si.displayType = MT_CRT;

src/add-ons/accelerants/s3/virge_init.cpp

219

si.panelX = 0;

src/add-ons/accelerants/s3/virge_init.cpp

220

si.panelY = 0;

src/add-ons/accelerants/s3/virge_init.cpp

225

si.colorSpaces[0] = B_CMAP8;

src/add-ons/accelerants/s3/virge_init.cpp

226

si.colorSpaces[1] = B_RGB16;

src/add-ons/accelerants/s3/virge_init.cpp

227

si.colorSpaceCount = 2;

src/add-ons/accelerants/s3/virge_init.cpp

229

si.bDisableHdwCursor = false; // allow use of hardware cursor

src/add-ons/accelerants/s3/virge_init.cpp

230

si.bDisableAccelDraw = false; // allow use of accelerated drawing functions

src/add-ons/accelerants/s3/virge_init.cpp

81

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_init.cpp

92

WritePIO_8(CRTC_DATA, (uint8)((uint32)(si.videoMemPCI) >> 24));

src/add-ons/accelerants/s3/virge_init.cpp

94

WritePIO_8(CRTC_DATA, (uint8)((uint32)(si.videoMemPCI) >> 16));

src/add-ons/accelerants/s3/virge_mode.cpp

147

uint8 regIndex = (si.chipType == S3_VIRGE_VX ? 0x63 : 0x66);

src/add-ons/accelerants/s3/virge_mode.cpp

180

if (si.chipType == S3_TRIO_3D)

src/add-ons/accelerants/s3/virge_mode.cpp

252

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_mode.cpp

256

if (ReadCrtcReg(si.chipType == S3_VIRGE_VX ? 0x63 : 0x66) & 0x01)

src/add-ons/accelerants/s3/virge_mode.cpp

295

if (si.chipType != S3_TRIO_3D && si.chipType != S3_VIRGE_MX) {

src/add-ons/accelerants/s3/virge_mode.cpp

299

if (S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

313

if (si.chipType == S3_TRIO_3D_2X || S3_VIRGE_GX2_SERIES(si.chipType)

src/add-ons/accelerants/s3/virge_mode.cpp

314

/* MXTESTME */ || S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

318

if (si.chipType == S3_VIRGE_DXGX) {

src/add-ons/accelerants/s3/virge_mode.cpp

322

if ( (si.chipType == S3_VIRGE_GX2) || S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

330

if (si.chipType == S3_VIRGE_DXGX || S3_VIRGE_GX2_SERIES(si.chipType) ||

src/add-ons/accelerants/s3/virge_mode.cpp

331

S3_VIRGE_MX_SERIES(si.chipType) || si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

343

if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

346

if (S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

362

if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

382

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_mode.cpp

391

if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

426

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_mode.cpp

43

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_mode.cpp

436

if (si.chipType == S3_VIRGE_VX || S3_VIRGE_GX2_SERIES(si.chipType) ||

src/add-ons/accelerants/s3/virge_mode.cpp

437

S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

442

if (si.chipType == S3_TRIO_3D && mode.timing.pixel_clock > 115000)

src/add-ons/accelerants/s3/virge_mode.cpp

457

if ( S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) )

src/add-ons/accelerants/s3/virge_mode.cpp

464

if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

47

si.commonCmd = DRAW | DST_8BPP;

src/add-ons/accelerants/s3/virge_mode.cpp

472

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_mode.cpp

478

if ( S3_VIRGE_GX2_SERIES(si.chipType) ||

src/add-ons/accelerants/s3/virge_mode.cpp

479

S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

492

if (si.videoMemSize == 1 * 1024 * 1024)

src/add-ons/accelerants/s3/virge_mode.cpp

494

else if (si.videoMemSize == 2 * 1024 * 1024)

src/add-ons/accelerants/s3/virge_mode.cpp

497

if (si.chipType == S3_TRIO_3D_2X && si.videoMemSize == 8 * 1024 * 1024)

src/add-ons/accelerants/s3/virge_mode.cpp

50

si.commonCmd = DRAW | DST_16BPP;

src/add-ons/accelerants/s3/virge_mode.cpp

503

if (si.chipType == S3_VIRGE_VX)

src/add-ons/accelerants/s3/virge_mode.cpp

513

if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

526

if (si.chipType != S3_TRIO_3D && si.chipType != S3_VIRGE_MX) {

src/add-ons/accelerants/s3/virge_mode.cpp

53

si.commonCmd = DRAW | DST_24BPP;

src/add-ons/accelerants/s3/virge_mode.cpp

530

if (S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

546

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_mode.cpp

562

else if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType)) {

src/add-ons/accelerants/s3/virge_mode.cpp

580

else if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

619

if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

630

if (si.chipType == S3_TRIO_3D_2X || S3_VIRGE_GX2_SERIES(si.chipType)

src/add-ons/accelerants/s3/virge_mode.cpp

631

/* MXTESTME */ || S3_VIRGE_MX_SERIES(si.chipType) ) {

src/add-ons/accelerants/s3/virge_mode.cpp

646

if (si.chipType == S3_VIRGE_DXGX || si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

650

if (si.chipType == S3_VIRGE_DXGX || S3_VIRGE_GX2_SERIES(si.chipType) ||

src/add-ons/accelerants/s3/virge_mode.cpp

651

S3_VIRGE_MX_SERIES(si.chipType) || si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/s3/virge_mode.cpp

661

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_mode.cpp

679

if (si.chipType == S3_VIRGE_VX) {

src/add-ons/accelerants/s3/virge_mode.cpp

701

si.bDisableHdwCursor = (si.chipType == S3_VIRGE_VX

src/add-ons/accelerants/s3/virge_mode.cpp

738

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_mode.cpp

744

if (si.chipType == S3_TRIO_3D && mode.timing.pixel_clock > 115000)

src/add-ons/accelerants/s3/virge_mode.cpp

747

base += si.frameBufferOffset;

src/add-ons/accelerants/s3/virge_mode.cpp

90

SharedInfo& si = *gInfo.sharedInfo;

src/add-ons/accelerants/s3/virge_mode.cpp

92

if (si.chipType == S3_TRIO_3D)

src/add-ons/accelerants/s3/virge_mode.cpp

97

if (si.chipType == S3_TRIO_3D) {

src/add-ons/accelerants/skeleton/Cursor.c

103

if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x);

src/add-ons/accelerants/skeleton/Cursor.c

105

if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y);

src/add-ons/accelerants/skeleton/Cursor.c

109

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/Cursor.c

117

if (x < si->dm.timing.h_display)

src/add-ons/accelerants/skeleton/Cursor.c

119

if (si->cursor.dh_right)

src/add-ons/accelerants/skeleton/Cursor.c

124

si->cursor.dh_right = false;

src/add-ons/accelerants/skeleton/Cursor.c

130

if (!si->cursor.dh_right)

src/add-ons/accelerants/skeleton/Cursor.c

135

si->cursor.dh_right = true;

src/add-ons/accelerants/skeleton/Cursor.c

137

head2_cursor_position((x - si->dm.timing.h_display), y);

src/add-ons/accelerants/skeleton/Cursor.c

149

si->cursor.is_visible = is_visible;

src/add-ons/accelerants/skeleton/Cursor.c

151

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/Cursor.c

169

if (!si->cursor.dh_right)

src/add-ons/accelerants/skeleton/Cursor.c

30

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)

src/add-ons/accelerants/skeleton/Cursor.c

34

si->cursor.width = width;

src/add-ons/accelerants/skeleton/Cursor.c

35

si->cursor.height = height;

src/add-ons/accelerants/skeleton/Cursor.c

36

si->cursor.hot_x = hot_x;

src/add-ons/accelerants/skeleton/Cursor.c

37

si->cursor.hot_y = hot_y;

src/add-ons/accelerants/skeleton/Cursor.c

46

uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */

src/add-ons/accelerants/skeleton/Cursor.c

47

uint16 vds = si->dm.v_display_start; /* the current vertical starting line */

src/add-ons/accelerants/skeleton/Cursor.c

51

if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;

src/add-ons/accelerants/skeleton/Cursor.c

52

if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;

src/add-ons/accelerants/skeleton/Cursor.c

55

si->cursor.x = x;

src/add-ons/accelerants/skeleton/Cursor.c

56

si->cursor.y = y;

src/add-ons/accelerants/skeleton/Cursor.c

63

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/Cursor.c

67

if (x >= ((si->dm.timing.h_display * 2) + hds))

src/add-ons/accelerants/skeleton/Cursor.c

69

hds = ((x - (si->dm.timing.h_display * 2)) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/skeleton/Cursor.c

71

if ((hds + (si->dm.timing.h_display * 2)) > si->dm.virtual_width)

src/add-ons/accelerants/skeleton/Cursor.c

78

if (x >= (si->dm.timing.h_display + hds))

src/add-ons/accelerants/skeleton/Cursor.c

80

hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/skeleton/Cursor.c

82

if ((hds + si->dm.timing.h_display) > si->dm.virtual_width)

src/add-ons/accelerants/skeleton/Cursor.c

90

if (y >= (si->dm.timing.v_display + vds))

src/add-ons/accelerants/skeleton/Cursor.c

91

vds = y - si->dm.timing.v_display + 1;

src/add-ons/accelerants/skeleton/Cursor.c

96

if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))

src/add-ons/accelerants/skeleton/EngineManagement.c

26

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/skeleton/EngineManagement.c

41

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/skeleton/EngineManagement.c

55

st->counter = si->engine.count;

src/add-ons/accelerants/skeleton/GetAccelerantHook.c

211

if (si->acc_mode)

src/add-ons/accelerants/skeleton/GetAccelerantHook.c

33

#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed

src/add-ons/accelerants/skeleton/GetDeviceInfo.c

19

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/GetDeviceInfo.c

95

adi->memory = si->ps.memory_size;

src/add-ons/accelerants/skeleton/GetDeviceInfo.c

96

adi->dac_speed = si->ps.max_dac1_clock;

src/add-ons/accelerants/skeleton/GetModeInfo.c

102

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/skeleton/GetModeInfo.c

106

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/skeleton/GetModeInfo.c

109

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/skeleton/GetModeInfo.c

112

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/skeleton/GetModeInfo.c

116

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/skeleton/GetModeInfo.c

125

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/skeleton/GetModeInfo.c

129

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/skeleton/GetModeInfo.c

132

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/skeleton/GetModeInfo.c

135

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/skeleton/GetModeInfo.c

139

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/skeleton/GetModeInfo.c

23

*current_mode = si->dm;

src/add-ons/accelerants/skeleton/GetModeInfo.c

33

*afb = si->fbc;

src/add-ons/accelerants/skeleton/GetModeInfo.c

54

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/GetModeInfo.c

57

*low = ((si->ps.min_video_vco * 1000) / 16);

src/add-ons/accelerants/skeleton/GetModeInfo.c

65

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/skeleton/GetModeInfo.c

69

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/skeleton/GetModeInfo.c

72

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/skeleton/GetModeInfo.c

76

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/skeleton/GetModeInfo.c

80

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/skeleton/GetModeInfo.c

90

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/GetModeInfo.c

93

*low = ((si->ps.min_pixel_vco * 1000) / 16);

src/add-ons/accelerants/skeleton/GetModeInfo.c

97

if (!si->ps.crtc2_prim)

src/add-ons/accelerants/skeleton/InitAccelerant.c

142

si->cursor.width = 16;

src/add-ons/accelerants/skeleton/InitAccelerant.c

143

si->cursor.height = 16;

src/add-ons/accelerants/skeleton/InitAccelerant.c

144

si->cursor.hot_x = 0;

src/add-ons/accelerants/skeleton/InitAccelerant.c

145

si->cursor.hot_y = 0;

src/add-ons/accelerants/skeleton/InitAccelerant.c

146

si->cursor.x = 0;

src/add-ons/accelerants/skeleton/InitAccelerant.c

147

si->cursor.y = 0;

src/add-ons/accelerants/skeleton/InitAccelerant.c

148

si->cursor.dh_right = false;

src/add-ons/accelerants/skeleton/InitAccelerant.c

157

if (si->settings.hardcursor) pointer_reservation = 2048;

src/add-ons/accelerants/skeleton/InitAccelerant.c

159

si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);

src/add-ons/accelerants/skeleton/InitAccelerant.c

160

si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);

src/add-ons/accelerants/skeleton/InitAccelerant.c

163

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/skeleton/InitAccelerant.c

164

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/skeleton/InitAccelerant.c

166

INIT_BEN(si->overlay.lock);

src/add-ons/accelerants/skeleton/InitAccelerant.c

170

si->overlay.myBuffer[cnt].buffer = NULL;

src/add-ons/accelerants/skeleton/InitAccelerant.c

171

si->overlay.myBuffer[cnt].buffer_dma = NULL;

src/add-ons/accelerants/skeleton/InitAccelerant.c

174

si->overlay.myToken = NULL;

src/add-ons/accelerants/skeleton/InitAccelerant.c

177

si->overlay.active = false;

src/add-ons/accelerants/skeleton/InitAccelerant.c

184

if (si->ps.secondary_head) head2_cursor_init();

src/add-ons/accelerants/skeleton/InitAccelerant.c

188

if (si->ps.secondary_head) head2_cursor_hide();

src/add-ons/accelerants/skeleton/InitAccelerant.c

270

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/skeleton/InitAccelerant.c

281

si->mode_area

src/add-ons/accelerants/skeleton/InitAccelerant.c

312

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/skeleton/InitAccelerant.c

313

DELETE_BEN(si->overlay.lock);

src/add-ons/accelerants/skeleton/InitAccelerant.c

34

shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS,

src/add-ons/accelerants/skeleton/InitAccelerant.c

42

si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead, si->settings.force_pci));

src/add-ons/accelerants/skeleton/InitAccelerant.c

44

si->settings.dumprom, si->settings.unhide_fw, si->settings.pgm_panel));

src/add-ons/accelerants/skeleton/InitAccelerant.c

48

if (si->use_clone_bugfix)

src/add-ons/accelerants/skeleton/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/skeleton/InitAccelerant.c

58

B_READ_AREA | B_WRITE_AREA, si->regs_area);

src/add-ons/accelerants/skeleton/InitAccelerant.c

87

si = 0;

src/add-ons/accelerants/skeleton/Overlay.c

102

si->overlay.myBuffer[offset].width = ((width + 0x000f) & ~0x000f);

src/add-ons/accelerants/skeleton/Overlay.c

109

si->overlay.myBuffer[offset].width = ((width + 0x001f) & ~0x001f);

src/add-ons/accelerants/skeleton/Overlay.c

111

si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;

src/add-ons/accelerants/skeleton/Overlay.c

115

if (si->overlay.myBuffer[offset].width > 4088)

src/add-ons/accelerants/skeleton/Overlay.c

120

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

130

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

137

if (si->overlay.myBuffer[offset].width > 1024)

src/add-ons/accelerants/skeleton/Overlay.c

142

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

152

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

158

si->overlay.myBufInfo[offset].slopspace = si->overlay.myBuffer[offset].width - width;

src/add-ons/accelerants/skeleton/Overlay.c

160

si->overlay.myBuffer[offset].space = cs;

src/add-ons/accelerants/skeleton/Overlay.c

161

si->overlay.myBuffer[offset].height = height;

src/add-ons/accelerants/skeleton/Overlay.c

187

adress2 = (((uint32)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */

src/add-ons/accelerants/skeleton/Overlay.c

188

(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */

src/add-ons/accelerants/skeleton/Overlay.c

192

oldsize = si->overlay.myBufInfo[offset].size;

src/add-ons/accelerants/skeleton/Overlay.c

193

si->overlay.myBufInfo[offset].size =

src/add-ons/accelerants/skeleton/Overlay.c

194

si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;

src/add-ons/accelerants/skeleton/Overlay.c

207

adress = (((uint32)((uint8*)si->framebuffer)) + si->ps.memory_size);

src/add-ons/accelerants/skeleton/Overlay.c

210

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/skeleton/Overlay.c

218

temp32 = (adress - ((uint32)((vuint32 *)si->framebuffer)));

src/add-ons/accelerants/skeleton/Overlay.c

223

si->overlay.myBufInfo[offset].size += (temp32 - (temp32 & 0xfffffff0));

src/add-ons/accelerants/skeleton/Overlay.c

244

if (si->overlay.myBuffer[cnt].buffer != NULL)

src/add-ons/accelerants/skeleton/Overlay.c

247

if (si->overlay.myBufInfo[offset].size <= oldsize)

src/add-ons/accelerants/skeleton/Overlay.c

251

adress -= (oldsize - si->overlay.myBufInfo[offset].size);

src/add-ons/accelerants/skeleton/Overlay.c

252

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/skeleton/Overlay.c

265

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/skeleton/Overlay.c

268

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

283

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

288

si->overlay.myBuffer[offset].buffer = (void *) adress;

src/add-ons/accelerants/skeleton/Overlay.c

291

adress = (((uint32)((uint8*)si->framebuffer_pci)) + si->ps.memory_size);

src/add-ons/accelerants/skeleton/Overlay.c

294

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/skeleton/Overlay.c

297

si->overlay.myBuffer[offset].buffer_dma = (void *) adress;

src/add-ons/accelerants/skeleton/Overlay.c

300

(uint32)((uint8*)si->overlay.myBuffer[offset].buffer),

src/add-ons/accelerants/skeleton/Overlay.c

301

(uint32)((uint8*)si->overlay.myBuffer[offset].buffer_dma), cs));

src/add-ons/accelerants/skeleton/Overlay.c

302

LOG(4,("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));

src/add-ons/accelerants/skeleton/Overlay.c

305

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

307

return &si->overlay.myBuffer[offset];

src/add-ons/accelerants/skeleton/Overlay.c

315

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

331

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/skeleton/Overlay.c

337

si->overlay.myBuffer[offset].buffer = NULL;

src/add-ons/accelerants/skeleton/Overlay.c

338

si->overlay.myBuffer[offset].buffer_dma = NULL;

src/add-ons/accelerants/skeleton/Overlay.c

378

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/skeleton/Overlay.c

390

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/Overlay.c

444

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/Overlay.c

458

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/skeleton/Overlay.c

489

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

492

if (si->overlay.myToken == NULL)

src/add-ons/accelerants/skeleton/Overlay.c

497

si->overlay.myToken = &tmpToken;

src/add-ons/accelerants/skeleton/Overlay.c

500

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

502

return si->overlay.myToken;

src/add-ons/accelerants/skeleton/Overlay.c

510

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

521

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/skeleton/Overlay.c

536

si->overlay.myToken = NULL;

src/add-ons/accelerants/skeleton/Overlay.c

579

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/skeleton/Overlay.c

592

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/skeleton/Overlay.c

79

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/skeleton/Overlay.c

81

LOG(4,("Overlay: cardRAM_start = $%08x\n",(uint32)((uint8*)si->framebuffer)));

src/add-ons/accelerants/skeleton/Overlay.c

82

LOG(4,("Overlay: cardRAM_start_DMA = $%08x\n",(uint32)((uint8*)si->framebuffer_pci)));

src/add-ons/accelerants/skeleton/Overlay.c

83

LOG(4,("Overlay: cardRAM_size = %3.3fMb\n",(si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/skeleton/Overlay.c

88

if (si->overlay.myBuffer[offset].buffer == NULL) break;

src/add-ons/accelerants/skeleton/Overlay.c

99

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

204

switch (si->ps.monitors)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

207

if (si->ps.panel1_aspect < (target_aspect - 0.10))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

214

if (si->ps.panel2_aspect < (target_aspect - 0.10))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

221

if ((si->ps.panel1_aspect < (target_aspect - 0.10)) ||

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

222

(si->ps.panel2_aspect < (target_aspect - 0.10)))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

243

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

245

if ((target->timing.h_display == si->ps.p1_timing.h_display) &&

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

246

(target->timing.v_display == si->ps.p1_timing.v_display))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

251

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

253

if ((target->timing.h_display == si->ps.p2_timing.h_display) &&

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

254

(target->timing.v_display == si->ps.p2_timing.v_display))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

267

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

269

if ((target->timing.h_display > si->ps.p1_timing.h_display) ||

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

270

(target->timing.v_display > si->ps.p1_timing.v_display))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

276

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

278

if ((target->timing.h_display > si->ps.p2_timing.h_display) ||

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

279

(target->timing.v_display > si->ps.p2_timing.v_display))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

374

if (si->settings.hardcursor) pointer_reservation = 2048;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

377

(si->ps.memory_size - pointer_reservation))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

380

(si->ps.memory_size - pointer_reservation) / row_bytes;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

416

max_vclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

421

max_vclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

425

max_vclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

429

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

434

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

441

if (si->ps.secondary_head && (target->timing.pixel_clock <= (max_vclk * 1000)))

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

447

if (((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

455

if ((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

462

if ((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

475

if (si->ps.tvout &&

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

484

if (si->settings.hardcursor)

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

507

LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

509

return si->mode_count;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

517

memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

540

si->mode_area = my_mode_list_area =

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

548

si->mode_count = 0;

src/add-ons/accelerants/skeleton/ProposeDisplayMode.c

578

si->mode_count++;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

202

si->interlaced_tv_mode = false;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

243

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

306

si->dm = target;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

347

switch(si->dm.space)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

367

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

371

if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

375

if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

379

if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

383

si->dm.h_display_start = h_display_start;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

384

si->dm.v_display_start = v_display_start;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

388

startadd = v_display_start * si->fbc.bytes_per_row;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

390

startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

391

startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);

src/add-ons/accelerants/skeleton/SetDisplayMode.c

395

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/SetDisplayMode.c

421

if (si->dm.space != B_CMAP8) return;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

423

r=si->color_data;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

436

if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b);

src/add-ons/accelerants/skeleton/SetDisplayMode.c

445

if (si->dm.flags & DUALHEAD_BITS) /*dualhead*/

src/add-ons/accelerants/skeleton/SetDisplayMode.c

89

startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/skeleton/SetDisplayMode.c

92

eng_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);

src/add-ons/accelerants/skeleton/engine/acc.c

37

switch(si->dm.space)

src/add-ons/accelerants/skeleton/engine/acc.c

53

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/agp.c

105

if (si->settings.force_pci)

src/add-ons/accelerants/skeleton/engine/agp.c

72

if ((nai.agpi.device_id == si->device_id) &&

src/add-ons/accelerants/skeleton/engine/agp.c

73

(nai.agpi.vendor_id == si->vendor_id) &&

src/add-ons/accelerants/skeleton/engine/agp.c

74

(nai.agpi.bus == si->bus) &&

src/add-ons/accelerants/skeleton/engine/agp.c

75

(nai.agpi.device == si->device) &&

src/add-ons/accelerants/skeleton/engine/agp.c

76

(nai.agpi.function == si->function))

src/add-ons/accelerants/skeleton/engine/bes.c

102

temp1 = (si->overlay.ow.h_start - crtc_hstart) & 0x7ff;

src/add-ons/accelerants/skeleton/engine/bes.c

108

if (si->overlay.ow.width < 2)

src/add-ons/accelerants/skeleton/engine/bes.c

115

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/skeleton/engine/bes.c

122

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/skeleton/engine/bes.c

130

temp2 = ((uint16)(si->overlay.ow.h_start + si->overlay.ow.width - crtc_hstart - 1)) & 0x7ff;

src/add-ons/accelerants/skeleton/engine/bes.c

141

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/skeleton/engine/bes.c

148

if (si->overlay.ow.v_start >= (crtc_vend - 1))

src/add-ons/accelerants/skeleton/engine/bes.c

156

temp1 = (si->overlay.ow.v_start - crtc_vstart) & 0x7ff;

src/add-ons/accelerants/skeleton/engine/bes.c

162

if (si->overlay.ow.height < 2)

src/add-ons/accelerants/skeleton/engine/bes.c

169

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) > (crtc_vend - 1))

src/add-ons/accelerants/skeleton/engine/bes.c

176

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/skeleton/engine/bes.c

184

temp2 = ((uint16)(si->overlay.ow.v_start + si->overlay.ow.height - crtc_vstart - 1)) & 0x7ff;

src/add-ons/accelerants/skeleton/engine/bes.c

206

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/skeleton/engine/bes.c

210

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/skeleton/engine/bes.c

213

moi->hsrcstv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/skeleton/engine/bes.c

218

moi->hsrcstv += (crtc_hstart - si->overlay.ow.h_start);

src/add-ons/accelerants/skeleton/engine/bes.c

224

moi->hsrcstv *= si->overlay.h_ifactor;

src/add-ons/accelerants/skeleton/engine/bes.c

227

moi->hsrcstv += ((uint32)si->overlay.my_ov.h_start) << 16;

src/add-ons/accelerants/skeleton/engine/bes.c

238

moi->a1orgv = (uint32)((vuint32 *)si->overlay.ob.buffer);

src/add-ons/accelerants/skeleton/engine/bes.c

239

moi->a1orgv -= (uint32)((vuint32 *)si->framebuffer);

src/add-ons/accelerants/skeleton/engine/bes.c

252

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/skeleton/engine/bes.c

256

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/skeleton/engine/bes.c

260

moi->v1srcstv = (si->overlay.ow.height - 2) * si->overlay.v_ifactor;

src/add-ons/accelerants/skeleton/engine/bes.c

263

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

264

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/skeleton/engine/bes.c

270

moi->v1srcstv = (crtc_vstart - si->overlay.ow.v_start) * si->overlay.v_ifactor;

src/add-ons/accelerants/skeleton/engine/bes.c

273

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

274

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/skeleton/engine/bes.c

279

moi->v1srcstv += (((uint32)si->overlay.my_ov.v_start) << 16);

src/add-ons/accelerants/skeleton/engine/bes.c

280

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

282

moi->a1orgv += (si->overlay.my_ov.v_start * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/skeleton/engine/bes.c

306

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

31

if (!si->overlay.active) return;

src/add-ons/accelerants/skeleton/engine/bes.c

354

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/bes.c

362

si->overlay.crtc = !si->crtc_switch_mode;

src/add-ons/accelerants/skeleton/engine/bes.c

370

si->overlay.crtc = si->crtc_switch_mode;

src/add-ons/accelerants/skeleton/engine/bes.c

382

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

412

BESW(NV10_0MEMMASK, (si->ps.memory_size - 1));

src/add-ons/accelerants/skeleton/engine/bes.c

45

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/bes.c

460

if (my_ov.h_start > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/skeleton/engine/bes.c

461

my_ov.h_start = ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1);

src/add-ons/accelerants/skeleton/engine/bes.c

462

if (((my_ov.h_start + my_ov.width) - 1) > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/skeleton/engine/bes.c

463

my_ov.width = ((((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1) - my_ov.h_start) + 1);

src/add-ons/accelerants/skeleton/engine/bes.c

47

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/skeleton/engine/bes.c

473

si->overlay.ow = *ow;

src/add-ons/accelerants/skeleton/engine/bes.c

474

si->overlay.ob = *ob;

src/add-ons/accelerants/skeleton/engine/bes.c

475

si->overlay.my_ov = my_ov;

src/add-ons/accelerants/skeleton/engine/bes.c

482

(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));

src/add-ons/accelerants/skeleton/engine/bes.c

51

if ((si->overlay.ow.h_start + (si->overlay.ow.width / 2)) <

src/add-ons/accelerants/skeleton/engine/bes.c

52

(si->dm.h_display_start + si->dm.timing.h_display))

src/add-ons/accelerants/skeleton/engine/bes.c

522

si->overlay.h_ifactor = ifactor;

src/add-ons/accelerants/skeleton/engine/bes.c

53

eng_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/skeleton/engine/bes.c

533

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/bes.c

548

if ((hiscalv > (2 << 16)) && (si->ps.card_type != NV31))

src/add-ons/accelerants/skeleton/engine/bes.c

55

eng_bes_to_crtc(!si->crtc_switch_mode);

src/add-ons/accelerants/skeleton/engine/bes.c

556

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/skeleton/engine/bes.c

58

eng_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/skeleton/engine/bes.c

615

si->overlay.v_ifactor = ifactor;

src/add-ons/accelerants/skeleton/engine/bes.c

625

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/bes.c

640

if ((viscalv > (2 << 16)) && (si->ps.card_type != NV31))

src/add-ons/accelerants/skeleton/engine/bes.c

648

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/skeleton/engine/bes.c

65

crtc_hstart = si->dm.h_display_start;

src/add-ons/accelerants/skeleton/engine/bes.c

67

if (si->overlay.crtc)

src/add-ons/accelerants/skeleton/engine/bes.c

69

crtc_hstart += si->dm.timing.h_display;

src/add-ons/accelerants/skeleton/engine/bes.c

699

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

73

crtc_hend = crtc_hstart + si->dm.timing.h_display;

src/add-ons/accelerants/skeleton/engine/bes.c

74

crtc_vstart = si->dm.v_display_start;

src/add-ons/accelerants/skeleton/engine/bes.c

746

switch(si->dm.space)

src/add-ons/accelerants/skeleton/engine/bes.c

76

crtc_vend = crtc_vstart + si->dm.timing.v_display;

src/add-ons/accelerants/skeleton/engine/bes.c

814

switch(si->dm.space)

src/add-ons/accelerants/skeleton/engine/bes.c

846

si->overlay.active = true;

src/add-ons/accelerants/skeleton/engine/bes.c

853

if (si->ps.card_arch < NV10A)

src/add-ons/accelerants/skeleton/engine/bes.c

865

si->overlay.active = false;

src/add-ons/accelerants/skeleton/engine/bes.c

87

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/skeleton/engine/bes.c

94

if (si->overlay.ow.h_start >= (crtc_hend - 1))

src/add-ons/accelerants/skeleton/engine/crtc.c

122

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/crtc.c

128

((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

132

((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

136

(((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

141

if (target.timing.h_display == si->ps.p1_timing.h_display)

src/add-ons/accelerants/skeleton/engine/crtc.c

144

if (si->ps.card_type == NV11)

src/add-ons/accelerants/skeleton/engine/crtc.c

158

((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

162

((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

166

((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc.c

263

if (si->ps.card_arch >= NV10A)

src/add-ons/accelerants/skeleton/engine/crtc.c

315

if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f));

src/add-ons/accelerants/skeleton/engine/crtc.c

318

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/crtc.c

32

if (si->ps.card_type > NV04)

src/add-ons/accelerants/skeleton/engine/crtc.c

323

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display);

src/add-ons/accelerants/skeleton/engine/crtc.c

324

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display);

src/add-ons/accelerants/skeleton/engine/crtc.c

334

DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1));

src/add-ons/accelerants/skeleton/engine/crtc.c

337

DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1));

src/add-ons/accelerants/skeleton/engine/crtc.c

390

if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/skeleton/engine/crtc.c

401

diff = ((si->ps.p1_timing.h_display -

src/add-ons/accelerants/skeleton/engine/crtc.c

405

DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1));

src/add-ons/accelerants/skeleton/engine/crtc.c

410

if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/skeleton/engine/crtc.c

586

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/skeleton/engine/crtc.c

608

LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/skeleton/engine/crtc.c

609

LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/skeleton/engine/crtc.c

613

while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/skeleton/engine/crtc.c

624

if (si->ps.card_arch == NV04A)

src/add-ons/accelerants/skeleton/engine/crtc.c

65

if (si->ps.card_type > NV04)

src/add-ons/accelerants/skeleton/engine/crtc.c

669

if ((si->ps.card_arch == NV04A) || (si->ps.laptop))

src/add-ons/accelerants/skeleton/engine/crtc.c

695

fb = (uint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/skeleton/engine/crtc.c

745

cursor = (uint16*) si->framebuffer;

src/add-ons/accelerants/skeleton/engine/crtc.c

806

if (yhigh < (si->dm.timing.v_display - 16))

src/add-ons/accelerants/skeleton/engine/crtc.c

818

while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)

src/add-ons/accelerants/skeleton/engine/crtc2.c

108

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/crtc2.c

114

((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

118

((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

122

(((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

127

if (target.timing.h_display == si->ps.p2_timing.h_display)

src/add-ons/accelerants/skeleton/engine/crtc2.c

130

if (si->ps.card_type == NV11)

src/add-ons/accelerants/skeleton/engine/crtc2.c

144

((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

148

((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

152

((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/skeleton/engine/crtc2.c

298

if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));

src/add-ons/accelerants/skeleton/engine/crtc2.c

301

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/crtc2.c

306

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);

src/add-ons/accelerants/skeleton/engine/crtc2.c

307

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);

src/add-ons/accelerants/skeleton/engine/crtc2.c

317

DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));

src/add-ons/accelerants/skeleton/engine/crtc2.c

320

DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));

src/add-ons/accelerants/skeleton/engine/crtc2.c

373

if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/skeleton/engine/crtc2.c

384

diff = ((si->ps.p2_timing.h_display -

src/add-ons/accelerants/skeleton/engine/crtc2.c

388

DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));

src/add-ons/accelerants/skeleton/engine/crtc2.c

393

if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/skeleton/engine/crtc2.c

569

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/skeleton/engine/crtc2.c

590

LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/skeleton/engine/crtc2.c

591

LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/skeleton/engine/crtc2.c

595

while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/skeleton/engine/crtc2.c

631

if (si->ps.laptop)

src/add-ons/accelerants/skeleton/engine/crtc2.c

657

fb = (uint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/skeleton/engine/crtc2.c

707

cursor = (uint16*) si->framebuffer;

src/add-ons/accelerants/skeleton/engine/crtc2.c

768

if (yhigh < (si->dm.timing.v_display - 16))

src/add-ons/accelerants/skeleton/engine/crtc2.c

780

while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)

src/add-ons/accelerants/skeleton/engine/dac.c

149

if (si->ps.tmds1_active && !si->settings.pgm_panel)

src/add-ons/accelerants/skeleton/engine/dac.c

158

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/dac.c

163

target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;

src/add-ons/accelerants/skeleton/engine/dac.c

184

if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);

src/add-ons/accelerants/skeleton/engine/dac.c

213

switch (si->ps.card_type) {

src/add-ons/accelerants/skeleton/engine/dac.c

253

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/skeleton/engine/dac.c

257

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/skeleton/engine/dac.c

260

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/skeleton/engine/dac.c

263

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/skeleton/engine/dac.c

267

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/skeleton/engine/dac.c

272

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/skeleton/engine/dac.c

276

if (req_pclk < (si->ps.min_pixel_vco / 16.0))

src/add-ons/accelerants/skeleton/engine/dac.c

279

req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));

src/add-ons/accelerants/skeleton/engine/dac.c

280

req_pclk = (si->ps.min_pixel_vco / 16.0);

src/add-ons/accelerants/skeleton/engine/dac.c

297

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/skeleton/engine/dac.c

300

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/skeleton/engine/dac.c

307

if (si->ps.card_type == NV36)

src/add-ons/accelerants/skeleton/engine/dac.c

309

if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/skeleton/engine/dac.c

313

if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;

src/add-ons/accelerants/skeleton/engine/dac.c

317

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/skeleton/engine/dac.c

323

if (si->ps.ext_pll)

src/add-ons/accelerants/skeleton/engine/dac.c

326

error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac.c

329

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac.c

349

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/skeleton/engine/dac.c

351

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/skeleton/engine/dac.c

397

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/dac.c

410

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/dac.c

441

if (si->ps.card_type == NV36) discr_low = 3.2;

src/add-ons/accelerants/skeleton/engine/dac.c

457

if (req_sclk < (si->ps.min_system_vco / ((float)p_max)))

src/add-ons/accelerants/skeleton/engine/dac.c

460

req_sclk, (si->ps.min_system_vco / ((float)p_max))));

src/add-ons/accelerants/skeleton/engine/dac.c

461

req_sclk = (si->ps.min_system_vco / ((float)p_max));

src/add-ons/accelerants/skeleton/engine/dac.c

464

if (req_sclk > si->ps.max_system_vco)

src/add-ons/accelerants/skeleton/engine/dac.c

467

req_sclk, (float)si->ps.max_system_vco));

src/add-ons/accelerants/skeleton/engine/dac.c

468

req_sclk = si->ps.max_system_vco;

src/add-ons/accelerants/skeleton/engine/dac.c

478

if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))

src/add-ons/accelerants/skeleton/engine/dac.c

481

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/skeleton/engine/dac.c

487

if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))

src/add-ons/accelerants/skeleton/engine/dac.c

491

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/skeleton/engine/dac.c

497

if (si->ps.ext_pll)

src/add-ons/accelerants/skeleton/engine/dac.c

500

error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac.c

503

error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac.c

523

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/skeleton/engine/dac.c

525

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/skeleton/engine/dac.c

70

r = si->color_data;

src/add-ons/accelerants/skeleton/engine/dac2.c

157

if (si->ps.tmds2_active && !si->settings.pgm_panel)

src/add-ons/accelerants/skeleton/engine/dac2.c

166

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/dac2.c

171

target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;

src/add-ons/accelerants/skeleton/engine/dac2.c

192

if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);

src/add-ons/accelerants/skeleton/engine/dac2.c

221

switch (si->ps.card_type) {

src/add-ons/accelerants/skeleton/engine/dac2.c

261

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/skeleton/engine/dac2.c

265

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/skeleton/engine/dac2.c

268

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/skeleton/engine/dac2.c

271

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/skeleton/engine/dac2.c

275

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/skeleton/engine/dac2.c

280

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/skeleton/engine/dac2.c

284

if (req_pclk < (si->ps.min_video_vco / 16.0))

src/add-ons/accelerants/skeleton/engine/dac2.c

287

req_pclk, (float)(si->ps.min_video_vco / 16.0)));

src/add-ons/accelerants/skeleton/engine/dac2.c

288

req_pclk = (si->ps.min_video_vco / 16.0);

src/add-ons/accelerants/skeleton/engine/dac2.c

305

if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))

src/add-ons/accelerants/skeleton/engine/dac2.c

308

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/skeleton/engine/dac2.c

315

if (si->ps.card_type == NV36)

src/add-ons/accelerants/skeleton/engine/dac2.c

317

if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/skeleton/engine/dac2.c

321

if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;

src/add-ons/accelerants/skeleton/engine/dac2.c

325

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/skeleton/engine/dac2.c

330

if (si->ps.ext_pll)

src/add-ons/accelerants/skeleton/engine/dac2.c

333

error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac2.c

336

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/skeleton/engine/dac2.c

356

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/skeleton/engine/dac2.c

358

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/skeleton/engine/dac2.c

78

r = si->color_data;

src/add-ons/accelerants/skeleton/engine/general.c

122

if (si->fbc.frame_buffer == NULL)

src/add-ons/accelerants/skeleton/engine/general.c

131

((uint32 *)si->fbc.frame_buffer)[offset] = value;

src/add-ons/accelerants/skeleton/engine/general.c

139

if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;

src/add-ons/accelerants/skeleton/engine/general.c

163

if (si->ps.pins_status != B_OK)

src/add-ons/accelerants/skeleton/engine/general.c

17

#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \

src/add-ons/accelerants/skeleton/engine/general.c

172

switch(si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/general.c

269

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/general.c

310

if (!si->settings.usebios)

src/add-ons/accelerants/skeleton/engine/general.c

330

if (si->settings.logmask & 0x80000000) eng_dump_configuration_space();

src/add-ons/accelerants/skeleton/engine/general.c

333

setup_virtualized_heads(si->ps.crtc2_prim);

src/add-ons/accelerants/skeleton/engine/general.c

346

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/general.c

349

if (si->ps.card_type != NV11)

src/add-ons/accelerants/skeleton/engine/general.c

390

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/general.c

396

si->crtc_switch_mode = !si->ps.crtc2_prim;

src/add-ons/accelerants/skeleton/engine/general.c

401

si->crtc_switch_mode = si->ps.crtc2_prim;

src/add-ons/accelerants/skeleton/engine/general.c

404

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/skeleton/engine/general.c

475

si->overlay.crtc = false;

src/add-ons/accelerants/skeleton/engine/general.c

586

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/general.c

604

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/skeleton/engine/general.c

628

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/general.c

674

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/general.c

707

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/skeleton/engine/general.c

726

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/general.c

96

si->ps.laptop = false;

src/add-ons/accelerants/skeleton/engine/globals.c

13

shared_info *si;

src/add-ons/accelerants/skeleton/engine/globals.h

2

extern shared_info *si;

src/add-ons/accelerants/skeleton/engine/i2c.c

55

if (!si->ps.secondary_head) return result;

src/add-ons/accelerants/skeleton/engine/info.c

131

si->ps.pins_status = B_OK;

src/add-ons/accelerants/skeleton/engine/info.c

1352

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/info.c

1796

((uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1797

((uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1798

((uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1799

((uint32 *)si->framebuffer)[0x07] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1801

((uint32 *)si->framebuffer)[0x07] = 0x4e563131;

src/add-ons/accelerants/skeleton/engine/info.c

1803

((uint32 *)si->framebuffer)[0x0f] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1805

if (((uint32 *)si->framebuffer)[0x07] == 0x4e563131) stat = B_OK;

src/add-ons/accelerants/skeleton/engine/info.c

1840

((uint32 *)si->framebuffer)[(data >> 2)] = 0x4e564441;

src/add-ons/accelerants/skeleton/engine/info.c

1842

((uint32 *)si->framebuffer)[0x00] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1844

dummy = ((uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/skeleton/engine/info.c

1845

dummy = ((uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/skeleton/engine/info.c

1846

dummy = ((uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/skeleton/engine/info.c

1847

dummy = ((uint32 *)si->framebuffer)[0x00];

src/add-ons/accelerants/skeleton/engine/info.c

1849

if (((uint32 *)si->framebuffer)[(data >> 2)] == 0x4e564441) stat = B_OK;

src/add-ons/accelerants/skeleton/engine/info.c

187

si->ps.min_system_vco = fvco_min / 1000;

src/add-ons/accelerants/skeleton/engine/info.c

188

si->ps.max_system_vco = fvco_max / 1000;

src/add-ons/accelerants/skeleton/engine/info.c

1882

((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441;

src/add-ons/accelerants/skeleton/engine/info.c

1884

((uint32 *)si->framebuffer)[0x00000000] = 0x00000000;

src/add-ons/accelerants/skeleton/engine/info.c

1886

dummy = ((uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/skeleton/engine/info.c

1888

dummy = ((uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/skeleton/engine/info.c

1890

dummy = ((uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/skeleton/engine/info.c

1892

dummy = ((uint32 *)si->framebuffer)[0x00000000];

src/add-ons/accelerants/skeleton/engine/info.c

1895

if (((uint32 *)si->framebuffer)[0x01fc0000] == 0x4e564441) stat = B_OK;

src/add-ons/accelerants/skeleton/engine/info.c

1988

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/info.c

2001

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/info.c

2022

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/info.c

2039

switch (si->ps.card_arch)

src/add-ons/accelerants/skeleton/engine/info.c

2050

if (si->settings.memory != 0)

src/add-ons/accelerants/skeleton/engine/info.c

2053

si->ps.memory_size = si->settings.memory * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2057

si->ps.tvout = false;

src/add-ons/accelerants/skeleton/engine/info.c

2058

si->ps.tvout_chip_type = NONE;

src/add-ons/accelerants/skeleton/engine/info.c

2077

if (si->ps.secondary_head && si->settings.switchhead)

src/add-ons/accelerants/skeleton/engine/info.c

2080

si->ps.crtc2_prim = !si->ps.crtc2_prim;

src/add-ons/accelerants/skeleton/engine/info.c

2130

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

2156

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2157

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2158

si->ps.panel1_aspect = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2159

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2160

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2161

si->ps.panel2_aspect = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2162

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2163

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2164

si->ps.master_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2165

si->ps.master_tmds2 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2166

si->ps.tmds1_active = false;

src/add-ons/accelerants/skeleton/engine/info.c

2167

si->ps.tmds2_active = false;

src/add-ons/accelerants/skeleton/engine/info.c

2199

si->ps.slaved_tmds1 = true;

src/add-ons/accelerants/skeleton/engine/info.c

2200

si->ps.tmds1_active = true;

src/add-ons/accelerants/skeleton/engine/info.c

2201

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/skeleton/engine/info.c

2202

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/skeleton/engine/info.c

2206

if (si->ps.secondary_head && slaved_for_dev2 && !tvout2)

src/add-ons/accelerants/skeleton/engine/info.c

2212

si->ps.slaved_tmds2 = true;

src/add-ons/accelerants/skeleton/engine/info.c

2213

si->ps.tmds2_active = true;

src/add-ons/accelerants/skeleton/engine/info.c

2214

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/skeleton/engine/info.c

2215

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/skeleton/engine/info.c

2219

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/skeleton/engine/info.c

2220

!si->ps.slaved_tmds1 && !tvout1)

src/add-ons/accelerants/skeleton/engine/info.c

2226

si->ps.master_tmds1 = true;

src/add-ons/accelerants/skeleton/engine/info.c

2227

si->ps.tmds1_active = true;

src/add-ons/accelerants/skeleton/engine/info.c

2228

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/skeleton/engine/info.c

2229

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/skeleton/engine/info.c

2233

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/skeleton/engine/info.c

2234

si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2)

src/add-ons/accelerants/skeleton/engine/info.c

2240

si->ps.master_tmds2 = true;

src/add-ons/accelerants/skeleton/engine/info.c

2241

si->ps.tmds2_active = true;

src/add-ons/accelerants/skeleton/engine/info.c

2242

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/skeleton/engine/info.c

2243

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/skeleton/engine/info.c

2250

if (si->ps.laptop && si->ps.tmds1_active && si->ps.tmds2_active &&

src/add-ons/accelerants/skeleton/engine/info.c

2252

(si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) &&

src/add-ons/accelerants/skeleton/engine/info.c

2253

(si->ps.p1_timing.v_display == si->ps.p2_timing.v_display))

src/add-ons/accelerants/skeleton/engine/info.c

2257

if (si->ps.card_type == NV11)

src/add-ons/accelerants/skeleton/engine/info.c

2260

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2261

si->ps.master_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2262

si->ps.tmds1_active = false;

src/add-ons/accelerants/skeleton/engine/info.c

2263

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2264

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2271

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2272

si->ps.master_tmds1 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2273

si->ps.tmds1_active = false;

src/add-ons/accelerants/skeleton/engine/info.c

2274

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2275

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2280

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2281

si->ps.master_tmds2 = false;

src/add-ons/accelerants/skeleton/engine/info.c

2282

si->ps.tmds2_active = false;

src/add-ons/accelerants/skeleton/engine/info.c

2283

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2284

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2290

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/info.c

2293

si->ps.panel1_aspect =

src/add-ons/accelerants/skeleton/engine/info.c

2294

(si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display));

src/add-ons/accelerants/skeleton/engine/info.c

2296

si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2297

si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2298

si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2300

si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2301

si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2302

si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2304

si->ps.p1_timing.flags = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2305

if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/skeleton/engine/info.c

2306

if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/skeleton/engine/info.c

2309

si->ps.p1_timing.pixel_clock =

src/add-ons/accelerants/skeleton/engine/info.c

2310

(si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000;

src/add-ons/accelerants/skeleton/engine/info.c

2312

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/info.c

2315

si->ps.panel2_aspect =

src/add-ons/accelerants/skeleton/engine/info.c

2316

(si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display));

src/add-ons/accelerants/skeleton/engine/info.c

2318

si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2319

si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2320

si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2322

si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2323

si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2324

si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/skeleton/engine/info.c

2326

si->ps.p2_timing.flags = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2327

if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/skeleton/engine/info.c

2328

if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/skeleton/engine/info.c

2331

si->ps.p2_timing.pixel_clock =

src/add-ons/accelerants/skeleton/engine/info.c

2332

(si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000;

src/add-ons/accelerants/skeleton/engine/info.c

2365

if(si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

2401

si->ps.monitors = 0x00;

src/add-ons/accelerants/skeleton/engine/info.c

2403

si->ps.crtc2_prim = false;

src/add-ons/accelerants/skeleton/engine/info.c

2406

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

2408

if (si->ps.card_type != NV11)

src/add-ons/accelerants/skeleton/engine/info.c

2415

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/skeleton/engine/info.c

2416

if (si->ps.tmds2_active) si->ps.monitors |= 0x10;

src/add-ons/accelerants/skeleton/engine/info.c

2419

if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;

src/add-ons/accelerants/skeleton/engine/info.c

2421

if (eng_dac2_crt_connected()) si->ps.monitors |= 0x20;

src/add-ons/accelerants/skeleton/engine/info.c

2425

switch (si->ps.monitors)

src/add-ons/accelerants/skeleton/engine/info.c

2456

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2462

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2473

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2484

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2497

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/skeleton/engine/info.c

2508

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/skeleton/engine/info.c

2509

if (si->ps.tmds2_active) si->ps.monitors |= 0x10;

src/add-ons/accelerants/skeleton/engine/info.c

2512

if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;

src/add-ons/accelerants/skeleton/engine/info.c

2517

switch (si->ps.monitors)

src/add-ons/accelerants/skeleton/engine/info.c

2544

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2555

si->ps.crtc2_prim = true;

src/add-ons/accelerants/skeleton/engine/info.c

2558

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/skeleton/engine/info.c

256

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

2567

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/skeleton/engine/info.c

2570

if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;

src/add-ons/accelerants/skeleton/engine/info.c

2578

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/info.c

2581

p1->timing = si->ps.p1_timing;

src/add-ons/accelerants/skeleton/engine/info.c

2594

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/info.c

2597

p2->timing = si->ps.p2_timing;

src/add-ons/accelerants/skeleton/engine/info.c

2614

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2616

si->ps.max_system_vco = 256;

src/add-ons/accelerants/skeleton/engine/info.c

2617

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2618

si->ps.max_pixel_vco = 256;

src/add-ons/accelerants/skeleton/engine/info.c

2619

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2620

si->ps.max_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2621

si->ps.min_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2622

si->ps.max_dac1_clock = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2623

si->ps.max_dac1_clock_8 = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2624

si->ps.max_dac1_clock_16 = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2626

si->ps.max_dac1_clock_24 = 220;

src/add-ons/accelerants/skeleton/engine/info.c

2627

si->ps.max_dac1_clock_32 = 180;

src/add-ons/accelerants/skeleton/engine/info.c

2628

si->ps.max_dac1_clock_32dh = 180;

src/add-ons/accelerants/skeleton/engine/info.c

2630

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2631

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2632

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2633

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2634

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2636

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2638

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2639

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2641

si->ps.std_engine_clock = 90;

src/add-ons/accelerants/skeleton/engine/info.c

2642

si->ps.std_memory_clock = 110;

src/add-ons/accelerants/skeleton/engine/info.c

2648

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2650

si->ps.max_system_vco = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2651

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2652

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2653

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2654

si->ps.max_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2655

si->ps.min_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2656

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2657

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2658

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2660

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/skeleton/engine/info.c

2661

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/skeleton/engine/info.c

2662

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/skeleton/engine/info.c

2664

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2665

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2666

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2667

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2668

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2670

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2672

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2673

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2675

si->ps.std_engine_clock = 125;

src/add-ons/accelerants/skeleton/engine/info.c

2676

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/skeleton/engine/info.c

268

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

2682

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2684

si->ps.max_system_vco = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2685

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2686

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2687

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2688

si->ps.max_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2689

si->ps.min_video_vco = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2690

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2691

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2692

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/skeleton/engine/info.c

2694

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/skeleton/engine/info.c

2695

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/skeleton/engine/info.c

2696

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/skeleton/engine/info.c

2698

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2699

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2700

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2701

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2702

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2704

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/skeleton/engine/info.c

2706

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2707

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2709

si->ps.std_engine_clock = 100;

src/add-ons/accelerants/skeleton/engine/info.c

2710

si->ps.std_memory_clock = 125;

src/add-ons/accelerants/skeleton/engine/info.c

2716

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2718

si->ps.max_system_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2719

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2720

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2721

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2722

si->ps.max_video_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2723

si->ps.min_video_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2724

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2725

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2726

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2728

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2729

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2730

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2732

if (si->ps.card_type < NV17)

src/add-ons/accelerants/skeleton/engine/info.c

2737

si->ps.max_dac2_clock = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2738

si->ps.max_dac2_clock_8 = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2739

si->ps.max_dac2_clock_16 = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2740

si->ps.max_dac2_clock_24 = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2741

si->ps.max_dac2_clock_32 = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2743

si->ps.max_dac2_clock_32dh = 180;

src/add-ons/accelerants/skeleton/engine/info.c

2749

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2750

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2751

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2753

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2754

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2755

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2758

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2759

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2761

si->ps.std_engine_clock = 120;

src/add-ons/accelerants/skeleton/engine/info.c

2762

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/skeleton/engine/info.c

2768

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2770

si->ps.max_system_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2771

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2772

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2773

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2774

si->ps.max_video_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2775

si->ps.min_video_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2776

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2777

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2778

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2780

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2781

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2782

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2786

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2787

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2788

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2790

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2791

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2792

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2794

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2795

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2797

si->ps.std_engine_clock = 175;

src/add-ons/accelerants/skeleton/engine/info.c

2798

si->ps.std_memory_clock = 200;

src/add-ons/accelerants/skeleton/engine/info.c

2806

switch (si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/info.c

2812

si->ps.ext_pll = true;

src/add-ons/accelerants/skeleton/engine/info.c

2816

si->ps.ext_pll = false;

src/add-ons/accelerants/skeleton/engine/info.c

2820

si->ps.max_system_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2821

si->ps.min_system_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2822

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2823

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2824

si->ps.max_video_vco = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2825

si->ps.min_video_vco = 128;

src/add-ons/accelerants/skeleton/engine/info.c

2826

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2827

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2828

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2830

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2831

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2832

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2836

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2837

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2838

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/skeleton/engine/info.c

2840

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/skeleton/engine/info.c

2841

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/skeleton/engine/info.c

2842

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/skeleton/engine/info.c

2844

si->ps.primary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2845

si->ps.secondary_dvi = false;

src/add-ons/accelerants/skeleton/engine/info.c

2847

si->ps.std_engine_clock = 190;

src/add-ons/accelerants/skeleton/engine/info.c

2848

si->ps.std_memory_clock = 190;

src/add-ons/accelerants/skeleton/engine/info.c

2858

si->ps.memory_size = 1024 * 1024 *

src/add-ons/accelerants/skeleton/engine/info.c

2869

si->ps.memory_size = 32 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2872

si->ps.memory_size = 4 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2875

si->ps.memory_size = 8 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2878

si->ps.memory_size = 16 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2890

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/skeleton/engine/info.c

2892

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/skeleton/engine/info.c

2895

si->ps.secondary_head = false;

src/add-ons/accelerants/skeleton/engine/info.c

2917

si->ps.memory_size = 2 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2920

si->ps.memory_size = 4 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2923

si->ps.memory_size = 8 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2926

si->ps.memory_size = 16 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2929

si->ps.memory_size = 32 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2932

si->ps.memory_size = 64 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2935

si->ps.memory_size = 128 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2938

si->ps.memory_size = 256 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2941

si->ps.memory_size = 16 * 1024 * 1024;

src/add-ons/accelerants/skeleton/engine/info.c

2957

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/skeleton/engine/info.c

2959

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/skeleton/engine/info.c

2980

if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000;

src/add-ons/accelerants/skeleton/engine/info.c

3007

si->ps.secondary_head = true;

src/add-ons/accelerants/skeleton/engine/info.c

3010

si->ps.secondary_head = false;

src/add-ons/accelerants/skeleton/engine/info.c

3021

if (si->ps.ext_pll) LOG(2,("extended\n")); else LOG(2,("standard\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3022

LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));

src/add-ons/accelerants/skeleton/engine/info.c

3023

LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3024

LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3025

LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3026

LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3027

LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3028

LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco));

src/add-ons/accelerants/skeleton/engine/info.c

3029

LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));

src/add-ons/accelerants/skeleton/engine/info.c

3030

LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock));

src/add-ons/accelerants/skeleton/engine/info.c

3031

LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));

src/add-ons/accelerants/skeleton/engine/info.c

3032

LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));

src/add-ons/accelerants/skeleton/engine/info.c

3033

LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));

src/add-ons/accelerants/skeleton/engine/info.c

3034

LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));

src/add-ons/accelerants/skeleton/engine/info.c

3035

LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));

src/add-ons/accelerants/skeleton/engine/info.c

3036

LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh));

src/add-ons/accelerants/skeleton/engine/info.c

3037

LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock));

src/add-ons/accelerants/skeleton/engine/info.c

3038

LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8));

src/add-ons/accelerants/skeleton/engine/info.c

3039

LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16));

src/add-ons/accelerants/skeleton/engine/info.c

3040

LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24));

src/add-ons/accelerants/skeleton/engine/info.c

3041

LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32));

src/add-ons/accelerants/skeleton/engine/info.c

3042

LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh));

src/add-ons/accelerants/skeleton/engine/info.c

3044

if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3046

if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3048

switch (si->ps.tvout_chip_type)

src/add-ons/accelerants/skeleton/engine/info.c

3107

LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/skeleton/engine/info.c

3109

if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3110

if (si->ps.tmds1_active)

src/add-ons/accelerants/skeleton/engine/info.c

3113

if (si->ps.slaved_tmds1) LOG(2,("slaved\n")); else LOG(2,("master\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3115

si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.panel1_aspect));

src/add-ons/accelerants/skeleton/engine/info.c

3117

if (si->ps.tmds2_active)

src/add-ons/accelerants/skeleton/engine/info.c

312

if (si->ps.card_type == NV28)

src/add-ons/accelerants/skeleton/engine/info.c

3120

if (si->ps.slaved_tmds2) LOG(2,("slaved\n")); else LOG(2,("master\n"));

src/add-ons/accelerants/skeleton/engine/info.c

3122

si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.panel2_aspect));

src/add-ons/accelerants/skeleton/engine/info.c

3124

LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors));

src/add-ons/accelerants/skeleton/engine/info.c

334

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

346

if (si->ps.secondary_head)

src/add-ons/accelerants/skeleton/engine/info.c

376

if (si->ps.card_type == NV28)

src/add-ons/accelerants/skeleton/engine/info.c

379

ACCW(PT_NUMERATOR, (si->ps.std_engine_clock * 20));

src/add-ons/accelerants/skeleton/engine/info.c

59

si->ps.pins_status = B_ERROR;

src/add-ons/accelerants/skeleton/engine/info.c

63

rom = (uint8 *) si->rom_mirror;

src/add-ons/accelerants/skeleton/engine/info.c

786

if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))

src/add-ons/accelerants/skeleton/engine/info.c

793

si->ps.std_memory_clock = freq;

src/add-ons/accelerants/skeleton/engine/info.c

798

si->ps.std_engine_clock = freq;

src/add-ons/accelerants/skeleton/engine/info.c

893

((uint32 *)si->framebuffer)[cnt] = data;

src/add-ons/accelerants/skeleton/engine/info.c

896

if (((uint32 *)si->framebuffer)[3] != data)

src/add-ons/accelerants/skeleton/engine/proto.h

19

uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \

src/add-ons/accelerants/skeleton/engine/proto.h

20

uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \

src/add-ons/accelerants/skeleton/engine/tvout.c

111

if (req_pclks_field < (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0))

src/add-ons/accelerants/skeleton/engine/tvout.c

113

req_pclks_field = (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0);

src/add-ons/accelerants/skeleton/engine/tvout.c

130

if ((vco_clks_field >= ((si->ps.min_video_vco * 1000000) / fields_sec)) &&

src/add-ons/accelerants/skeleton/engine/tvout.c

131

(vco_clks_field <= ((si->ps.max_video_vco * 1000000) / fields_sec)))

src/add-ons/accelerants/skeleton/engine/tvout.c

137

n = (int)(((vco_clks_field * m) / ((si->ps.f_ref * 1000000) / fields_sec)) + 0.5);

src/add-ons/accelerants/skeleton/engine/tvout.c

144

(((uint32)((si->ps.f_ref * 1000000) / fields_sec)) * n) / ((float)(m * p));

src/add-ons/accelerants/skeleton/engine/tvout.c

171

f_vco = (si->ps.f_ref / m) * n;

src/add-ons/accelerants/skeleton/engine/tvout.c

204

if (si->ps.f_ref == 27.000)

src/add-ons/accelerants/skeleton/engine/tvout.c

223

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/skeleton/engine/tvout.c

226

switch(si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/tvout.c

57

switch(si->ps.card_type)

src/add-ons/accelerants/skeleton/engine/tvout.c

83

max_pclks_field = (si->ps.max_dac2_clock_16 * 1000000) / fields_sec;

src/add-ons/accelerants/skeleton/engine/tvout.c

86

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/skeleton/engine/tvout.c

90

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/skeleton/engine/tvout.c

95

max_pclks_field = (si->ps.max_dac2_clock_32dh * 1000000) / fields_sec;

src/add-ons/accelerants/via/Cursor.c

101

hds = ((x - (si->dm.timing.h_display * 2)) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/via/Cursor.c

103

if ((hds + (si->dm.timing.h_display * 2)) > si->dm.virtual_width)

src/add-ons/accelerants/via/Cursor.c

110

if (x >= (si->dm.timing.h_display + hds))

src/add-ons/accelerants/via/Cursor.c

112

hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) & ~h_adjust;

src/add-ons/accelerants/via/Cursor.c

114

if ((hds + si->dm.timing.h_display) > si->dm.virtual_width)

src/add-ons/accelerants/via/Cursor.c

122

if (y >= (si->dm.timing.v_display + vds))

src/add-ons/accelerants/via/Cursor.c

123

vds = y - si->dm.timing.v_display + 1;

src/add-ons/accelerants/via/Cursor.c

128

if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))

src/add-ons/accelerants/via/Cursor.c

135

if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x);

src/add-ons/accelerants/via/Cursor.c

137

if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y);

src/add-ons/accelerants/via/Cursor.c

141

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/Cursor.c

149

if (x < si->dm.timing.h_display)

src/add-ons/accelerants/via/Cursor.c

151

if (si->cursor.dh_right)

src/add-ons/accelerants/via/Cursor.c

156

si->cursor.dh_right = false;

src/add-ons/accelerants/via/Cursor.c

162

if (!si->cursor.dh_right)

src/add-ons/accelerants/via/Cursor.c

167

si->cursor.dh_right = true;

src/add-ons/accelerants/via/Cursor.c

169

head2_cursor_position((x - si->dm.timing.h_display), y);

src/add-ons/accelerants/via/Cursor.c

181

si->cursor.is_visible = is_visible;

src/add-ons/accelerants/via/Cursor.c

183

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/Cursor.c

201

if (!si->cursor.dh_right)

src/add-ons/accelerants/via/Cursor.c

30

if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)

src/add-ons/accelerants/via/Cursor.c

34

si->cursor.width = width;

src/add-ons/accelerants/via/Cursor.c

35

si->cursor.height = height;

src/add-ons/accelerants/via/Cursor.c

36

si->cursor.hot_x = hot_x;

src/add-ons/accelerants/via/Cursor.c

37

si->cursor.hot_y = hot_y;

src/add-ons/accelerants/via/Cursor.c

46

uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */

src/add-ons/accelerants/via/Cursor.c

47

uint16 vds = si->dm.v_display_start; /* the current vertical starting line */

src/add-ons/accelerants/via/Cursor.c

51

if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1;

src/add-ons/accelerants/via/Cursor.c

52

if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1;

src/add-ons/accelerants/via/Cursor.c

55

si->cursor.x = x;

src/add-ons/accelerants/via/Cursor.c

56

si->cursor.y = y;

src/add-ons/accelerants/via/Cursor.c

59

if (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/Cursor.c

62

switch(si->dm.space)

src/add-ons/accelerants/via/Cursor.c

77

switch(si->dm.space)

src/add-ons/accelerants/via/Cursor.c

95

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/Cursor.c

99

if (x >= ((si->dm.timing.h_display * 2) + hds))

src/add-ons/accelerants/via/EngineManagement.c

26

AQUIRE_BEN(si->engine.lock)

src/add-ons/accelerants/via/EngineManagement.c

41

RELEASE_BEN(si->engine.lock)

src/add-ons/accelerants/via/EngineManagement.c

55

st->counter = si->engine.count;

src/add-ons/accelerants/via/GetAccelerantHook.c

215

if (si->acc_mode)

src/add-ons/accelerants/via/GetAccelerantHook.c

33

#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed

src/add-ons/accelerants/via/GetDeviceInfo.c

19

switch (si->ps.card_type)

src/add-ons/accelerants/via/GetDeviceInfo.c

41

adi->memory = si->ps.memory_size;

src/add-ons/accelerants/via/GetDeviceInfo.c

42

adi->dac_speed = si->ps.max_dac1_clock;

src/add-ons/accelerants/via/GetModeInfo.c

102

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/via/GetModeInfo.c

106

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/via/GetModeInfo.c

109

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/via/GetModeInfo.c

112

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/GetModeInfo.c

116

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/GetModeInfo.c

125

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/via/GetModeInfo.c

129

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/via/GetModeInfo.c

132

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/via/GetModeInfo.c

135

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/via/GetModeInfo.c

139

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/via/GetModeInfo.c

23

*current_mode = si->dm;

src/add-ons/accelerants/via/GetModeInfo.c

33

*afb = si->fbc;

src/add-ons/accelerants/via/GetModeInfo.c

54

switch (si->ps.card_type)

src/add-ons/accelerants/via/GetModeInfo.c

57

*low = ((si->ps.min_video_vco * 1000) / 16);

src/add-ons/accelerants/via/GetModeInfo.c

65

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/via/GetModeInfo.c

69

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/via/GetModeInfo.c

72

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/via/GetModeInfo.c

76

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/via/GetModeInfo.c

80

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/via/GetModeInfo.c

90

switch (si->ps.card_type)

src/add-ons/accelerants/via/GetModeInfo.c

93

*low = ((si->ps.min_pixel_vco * 1000) / 16);

src/add-ons/accelerants/via/GetModeInfo.c

97

if (!si->ps.crtc2_prim)

src/add-ons/accelerants/via/InitAccelerant.c

143

si->cursor.width = 16;

src/add-ons/accelerants/via/InitAccelerant.c

144

si->cursor.height = 16;

src/add-ons/accelerants/via/InitAccelerant.c

145

si->cursor.hot_x = 0;

src/add-ons/accelerants/via/InitAccelerant.c

146

si->cursor.hot_y = 0;

src/add-ons/accelerants/via/InitAccelerant.c

147

si->cursor.x = 0;

src/add-ons/accelerants/via/InitAccelerant.c

148

si->cursor.y = 0;

src/add-ons/accelerants/via/InitAccelerant.c

149

si->cursor.dh_right = false;

src/add-ons/accelerants/via/InitAccelerant.c

158

if (si->settings.hardcursor) pointer_reservation = 4096;

src/add-ons/accelerants/via/InitAccelerant.c

160

si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);

src/add-ons/accelerants/via/InitAccelerant.c

161

si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);

src/add-ons/accelerants/via/InitAccelerant.c

164

si->engine.last_idle = si->engine.count = 0;

src/add-ons/accelerants/via/InitAccelerant.c

165

INIT_BEN(si->engine.lock);

src/add-ons/accelerants/via/InitAccelerant.c

167

INIT_BEN(si->overlay.lock);

src/add-ons/accelerants/via/InitAccelerant.c

171

si->overlay.myBuffer[cnt].buffer = NULL;

src/add-ons/accelerants/via/InitAccelerant.c

172

si->overlay.myBuffer[cnt].buffer_dma = NULL;

src/add-ons/accelerants/via/InitAccelerant.c

175

si->overlay.myToken = NULL;

src/add-ons/accelerants/via/InitAccelerant.c

178

si->overlay.active = false;

src/add-ons/accelerants/via/InitAccelerant.c

182

if (si->ps.secondary_head) head2_cursor_init();

src/add-ons/accelerants/via/InitAccelerant.c

186

if (si->ps.secondary_head) head2_cursor_hide();

src/add-ons/accelerants/via/InitAccelerant.c

268

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/via/InitAccelerant.c

279

si->mode_area

src/add-ons/accelerants/via/InitAccelerant.c

310

DELETE_BEN(si->engine.lock);

src/add-ons/accelerants/via/InitAccelerant.c

311

DELETE_BEN(si->overlay.lock);

src/add-ons/accelerants/via/InitAccelerant.c

35

shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS,

src/add-ons/accelerants/via/InitAccelerant.c

43

si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead, si->settings.force_pci));

src/add-ons/accelerants/via/InitAccelerant.c

45

si->settings.dumprom, si->settings.unhide_fw, si->settings.pgm_panel));

src/add-ons/accelerants/via/InitAccelerant.c

49

if (si->use_clone_bugfix)

src/add-ons/accelerants/via/InitAccelerant.c

53

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/via/InitAccelerant.c

59

B_READ_AREA | B_WRITE_AREA, si->regs_area);

src/add-ons/accelerants/via/InitAccelerant.c

88

si = 0;

src/add-ons/accelerants/via/Overlay.c

100

si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;

src/add-ons/accelerants/via/Overlay.c

104

if (si->overlay.myBuffer[offset].width > 4088)

src/add-ons/accelerants/via/Overlay.c

109

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

119

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

126

if (si->overlay.myBuffer[offset].width > 1024)

src/add-ons/accelerants/via/Overlay.c

131

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

141

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

147

si->overlay.myBufInfo[offset].slopspace = si->overlay.myBuffer[offset].width - width;

src/add-ons/accelerants/via/Overlay.c

149

si->overlay.myBuffer[offset].space = cs;

src/add-ons/accelerants/via/Overlay.c

150

si->overlay.myBuffer[offset].height = height;

src/add-ons/accelerants/via/Overlay.c

176

adress2 = (((uintptr_t)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */

src/add-ons/accelerants/via/Overlay.c

177

(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */

src/add-ons/accelerants/via/Overlay.c

181

oldsize = si->overlay.myBufInfo[offset].size;

src/add-ons/accelerants/via/Overlay.c

182

si->overlay.myBufInfo[offset].size =

src/add-ons/accelerants/via/Overlay.c

183

si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;

src/add-ons/accelerants/via/Overlay.c

196

adress = (((uintptr_t)((uint8*)si->framebuffer)) + si->ps.memory_size);

src/add-ons/accelerants/via/Overlay.c

199

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/via/Overlay.c

207

temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));

src/add-ons/accelerants/via/Overlay.c

212

si->overlay.myBufInfo[offset].size += (temp32 - (temp32 & 0xfffffff0));

src/add-ons/accelerants/via/Overlay.c

233

if (si->overlay.myBuffer[cnt].buffer != NULL)

src/add-ons/accelerants/via/Overlay.c

236

if (si->overlay.myBufInfo[offset].size <= oldsize)

src/add-ons/accelerants/via/Overlay.c

240

adress -= (oldsize - si->overlay.myBufInfo[offset].size);

src/add-ons/accelerants/via/Overlay.c

241

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/via/Overlay.c

254

si->overlay.myBufInfo[offset].size = oldsize;

src/add-ons/accelerants/via/Overlay.c

257

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

272

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

277

si->overlay.myBuffer[offset].buffer = (void *) adress;

src/add-ons/accelerants/via/Overlay.c

280

adress = (((uintptr_t)((uint8*)si->framebuffer_pci)) + si->ps.memory_size);

src/add-ons/accelerants/via/Overlay.c

283

adress -= si->overlay.myBufInfo[cnt].size;

src/add-ons/accelerants/via/Overlay.c

286

si->overlay.myBuffer[offset].buffer_dma = (void *) adress;

src/add-ons/accelerants/via/Overlay.c

289

(uint8*)si->overlay.myBuffer[offset].buffer,

src/add-ons/accelerants/via/Overlay.c

290

(uint8*)si->overlay.myBuffer[offset].buffer_dma, cs));

src/add-ons/accelerants/via/Overlay.c

291

LOG(4,("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));

src/add-ons/accelerants/via/Overlay.c

294

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

296

return &si->overlay.myBuffer[offset];

src/add-ons/accelerants/via/Overlay.c

304

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

320

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/via/Overlay.c

326

si->overlay.myBuffer[offset].buffer = NULL;

src/add-ons/accelerants/via/Overlay.c

327

si->overlay.myBuffer[offset].buffer_dma = NULL;

src/add-ons/accelerants/via/Overlay.c

367

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/via/Overlay.c

451

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

454

if (si->overlay.myToken == NULL)

src/add-ons/accelerants/via/Overlay.c

459

si->overlay.myToken = &tmpToken;

src/add-ons/accelerants/via/Overlay.c

462

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

464

return si->overlay.myToken;

src/add-ons/accelerants/via/Overlay.c

472

RELEASE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

483

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/via/Overlay.c

498

si->overlay.myToken = NULL;

src/add-ons/accelerants/via/Overlay.c

541

if ((ot == NULL) || (si->overlay.myToken == NULL) || (ot != si->overlay.myToken))

src/add-ons/accelerants/via/Overlay.c

554

if (si->overlay.myBuffer[offset].buffer == ob->buffer) break;

src/add-ons/accelerants/via/Overlay.c

78

AQUIRE_BEN(si->overlay.lock)

src/add-ons/accelerants/via/Overlay.c

80

LOG(4,("Overlay: cardRAM_start = $%p\n", (uint8*)si->framebuffer));

src/add-ons/accelerants/via/Overlay.c

81

LOG(4,("Overlay: cardRAM_start_DMA = $%p\n", (uint8*)si->framebuffer_pci));

src/add-ons/accelerants/via/Overlay.c

82

LOG(4,("Overlay: cardRAM_size = %3.3fMb\n",(si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/via/Overlay.c

87

if (si->overlay.myBuffer[offset].buffer == NULL) break;

src/add-ons/accelerants/via/Overlay.c

99

si->overlay.myBuffer[offset].width = ((width + 0x0007) & ~0x0007);

src/add-ons/accelerants/via/ProposeDisplayMode.c

206

switch (si->ps.monitors)

src/add-ons/accelerants/via/ProposeDisplayMode.c

209

if (si->ps.panel1_aspect < (target_aspect - 0.10))

src/add-ons/accelerants/via/ProposeDisplayMode.c

216

if (si->ps.panel2_aspect < (target_aspect - 0.10))

src/add-ons/accelerants/via/ProposeDisplayMode.c

223

if ((si->ps.panel1_aspect < (target_aspect - 0.10)) ||

src/add-ons/accelerants/via/ProposeDisplayMode.c

224

(si->ps.panel2_aspect < (target_aspect - 0.10)))

src/add-ons/accelerants/via/ProposeDisplayMode.c

245

if (si->ps.tmds1_active)

src/add-ons/accelerants/via/ProposeDisplayMode.c

247

if ((target->timing.h_display == si->ps.p1_timing.h_display) &&

src/add-ons/accelerants/via/ProposeDisplayMode.c

248

(target->timing.v_display == si->ps.p1_timing.v_display))

src/add-ons/accelerants/via/ProposeDisplayMode.c

253

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/ProposeDisplayMode.c

255

if ((target->timing.h_display == si->ps.p2_timing.h_display) &&

src/add-ons/accelerants/via/ProposeDisplayMode.c

256

(target->timing.v_display == si->ps.p2_timing.v_display))

src/add-ons/accelerants/via/ProposeDisplayMode.c

269

if (si->ps.tmds1_active)

src/add-ons/accelerants/via/ProposeDisplayMode.c

271

if ((target->timing.h_display > si->ps.p1_timing.h_display) ||

src/add-ons/accelerants/via/ProposeDisplayMode.c

272

(target->timing.v_display > si->ps.p1_timing.v_display))

src/add-ons/accelerants/via/ProposeDisplayMode.c

278

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/ProposeDisplayMode.c

280

if ((target->timing.h_display > si->ps.p2_timing.h_display) ||

src/add-ons/accelerants/via/ProposeDisplayMode.c

281

(target->timing.v_display > si->ps.p2_timing.v_display))

src/add-ons/accelerants/via/ProposeDisplayMode.c

376

if (si->settings.hardcursor) pointer_reservation = 2048;

src/add-ons/accelerants/via/ProposeDisplayMode.c

379

(si->ps.memory_size - pointer_reservation))

src/add-ons/accelerants/via/ProposeDisplayMode.c

382

(si->ps.memory_size - pointer_reservation) / row_bytes;

src/add-ons/accelerants/via/ProposeDisplayMode.c

418

max_vclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/via/ProposeDisplayMode.c

423

max_vclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/via/ProposeDisplayMode.c

427

max_vclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/via/ProposeDisplayMode.c

431

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/via/ProposeDisplayMode.c

436

max_vclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/via/ProposeDisplayMode.c

443

if (si->ps.secondary_head && (target->timing.pixel_clock <= (max_vclk * 1000)))

src/add-ons/accelerants/via/ProposeDisplayMode.c

449

if (((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/via/ProposeDisplayMode.c

457

if ((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/via/ProposeDisplayMode.c

464

if ((si->ps.memory_size - pointer_reservation) >=

src/add-ons/accelerants/via/ProposeDisplayMode.c

477

if (si->ps.tvout &&

src/add-ons/accelerants/via/ProposeDisplayMode.c

486

if (si->settings.hardcursor)

src/add-ons/accelerants/via/ProposeDisplayMode.c

509

LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count));

src/add-ons/accelerants/via/ProposeDisplayMode.c

511

return si->mode_count;

src/add-ons/accelerants/via/ProposeDisplayMode.c

519

memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode));

src/add-ons/accelerants/via/ProposeDisplayMode.c

542

si->mode_area = my_mode_list_area =

src/add-ons/accelerants/via/ProposeDisplayMode.c

550

si->mode_count = 0;

src/add-ons/accelerants/via/ProposeDisplayMode.c

580

si->mode_count++;

src/add-ons/accelerants/via/SetDisplayMode.c

202

si->interlaced_tv_mode = false;

src/add-ons/accelerants/via/SetDisplayMode.c

243

if (si->ps.secondary_head)

src/add-ons/accelerants/via/SetDisplayMode.c

305

si->dm = target;

src/add-ons/accelerants/via/SetDisplayMode.c

347

if (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/SetDisplayMode.c

350

switch(si->dm.space)

src/add-ons/accelerants/via/SetDisplayMode.c

361

LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));

src/add-ons/accelerants/via/SetDisplayMode.c

367

switch(si->dm.space)

src/add-ons/accelerants/via/SetDisplayMode.c

387

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/SetDisplayMode.c

391

if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/via/SetDisplayMode.c

395

if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)

src/add-ons/accelerants/via/SetDisplayMode.c

399

if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)

src/add-ons/accelerants/via/SetDisplayMode.c

403

si->dm.h_display_start = h_display_start;

src/add-ons/accelerants/via/SetDisplayMode.c

404

si->dm.v_display_start = v_display_start;

src/add-ons/accelerants/via/SetDisplayMode.c

408

startadd = v_display_start * si->fbc.bytes_per_row;

src/add-ons/accelerants/via/SetDisplayMode.c

410

startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/via/SetDisplayMode.c

411

startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);

src/add-ons/accelerants/via/SetDisplayMode.c

415

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/SetDisplayMode.c

441

if (si->dm.space != B_CMAP8) return;

src/add-ons/accelerants/via/SetDisplayMode.c

443

r=si->color_data;

src/add-ons/accelerants/via/SetDisplayMode.c

466

if (si->dm.flags & DUALHEAD_BITS) /*dualhead*/

src/add-ons/accelerants/via/SetDisplayMode.c

472

if (si->ps.secondary_head) head2_dpms(true, true, true);

src/add-ons/accelerants/via/SetDisplayMode.c

476

if (si->ps.secondary_head) head2_dpms(false, false, true);

src/add-ons/accelerants/via/SetDisplayMode.c

480

if (si->ps.secondary_head) head2_dpms(false, true, false);

src/add-ons/accelerants/via/SetDisplayMode.c

484

if (si->ps.secondary_head) head2_dpms(false, false, false);

src/add-ons/accelerants/via/SetDisplayMode.c

89

startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;

src/add-ons/accelerants/via/SetDisplayMode.c

92

eng_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);

src/add-ons/accelerants/via/engine/acc.c

37

switch(si->dm.space)

src/add-ons/accelerants/via/engine/acc.c

53

switch (si->ps.card_arch)

src/add-ons/accelerants/via/engine/agp.c

51

if (nai.agpi.device_id == si->device_id

src/add-ons/accelerants/via/engine/agp.c

52

&& nai.agpi.vendor_id == si->vendor_id

src/add-ons/accelerants/via/engine/agp.c

53

&& nai.agpi.bus == si->bus

src/add-ons/accelerants/via/engine/agp.c

54

&& nai.agpi.device == si->device

src/add-ons/accelerants/via/engine/agp.c

55

&& nai.agpi.function == si->function) {

src/add-ons/accelerants/via/engine/agp.c

79

if (si->settings.force_pci) {

src/add-ons/accelerants/via/engine/bes.c

1043

if (si->ps.card_arch < K8M800)

src/add-ons/accelerants/via/engine/bes.c

106

if (!si->overlay.active) return;

src/add-ons/accelerants/via/engine/bes.c

1075

si->overlay.active = true;

src/add-ons/accelerants/via/engine/bes.c

1082

if (si->ps.card_arch < K8M800)

src/add-ons/accelerants/via/engine/bes.c

1102

si->overlay.active = false;

src/add-ons/accelerants/via/engine/bes.c

120

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/bes.c

122

switch (si->dm.flags & DUALHEAD_BITS)

src/add-ons/accelerants/via/engine/bes.c

126

if ((si->overlay.ow.h_start + (si->overlay.ow.width / 2)) <

src/add-ons/accelerants/via/engine/bes.c

127

(si->dm.h_display_start + si->dm.timing.h_display))

src/add-ons/accelerants/via/engine/bes.c

128

eng_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/via/engine/bes.c

130

eng_bes_to_crtc(!si->crtc_switch_mode);

src/add-ons/accelerants/via/engine/bes.c

133

eng_bes_to_crtc(si->crtc_switch_mode);

src/add-ons/accelerants/via/engine/bes.c

140

crtc_hstart = si->dm.h_display_start;

src/add-ons/accelerants/via/engine/bes.c

142

if (si->overlay.crtc)

src/add-ons/accelerants/via/engine/bes.c

144

crtc_hstart += si->dm.timing.h_display;

src/add-ons/accelerants/via/engine/bes.c

148

crtc_hend = crtc_hstart + si->dm.timing.h_display;

src/add-ons/accelerants/via/engine/bes.c

149

crtc_vstart = si->dm.v_display_start;

src/add-ons/accelerants/via/engine/bes.c

151

crtc_vend = crtc_vstart + si->dm.timing.v_display;

src/add-ons/accelerants/via/engine/bes.c

162

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/via/engine/bes.c

169

if (si->overlay.ow.h_start >= (crtc_hend - 1))

src/add-ons/accelerants/via/engine/bes.c

177

temp1 = (si->overlay.ow.h_start - crtc_hstart) & 0x7ff;

src/add-ons/accelerants/via/engine/bes.c

183

if (si->overlay.ow.width < 2)

src/add-ons/accelerants/via/engine/bes.c

190

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/via/engine/bes.c

197

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/via/engine/bes.c

205

temp2 = ((uint16)(si->overlay.ow.h_start + si->overlay.ow.width - crtc_hstart - 1)) & 0x7ff;

src/add-ons/accelerants/via/engine/bes.c

216

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/via/engine/bes.c

223

if (si->overlay.ow.v_start >= (crtc_vend - 1))

src/add-ons/accelerants/via/engine/bes.c

231

temp1 = (si->overlay.ow.v_start - crtc_vstart) & 0x7ff;

src/add-ons/accelerants/via/engine/bes.c

237

if (si->overlay.ow.height < 2)

src/add-ons/accelerants/via/engine/bes.c

244

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) > (crtc_vend - 1))

src/add-ons/accelerants/via/engine/bes.c

251

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/via/engine/bes.c

259

temp2 = ((uint16)(si->overlay.ow.v_start + si->overlay.ow.height - crtc_vstart - 1)) & 0x7ff;

src/add-ons/accelerants/via/engine/bes.c

281

if (si->overlay.ow.h_start < crtc_hstart)

src/add-ons/accelerants/via/engine/bes.c

285

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) < (crtc_hstart + 1))

src/add-ons/accelerants/via/engine/bes.c

288

moi->hsrcstv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/via/engine/bes.c

293

moi->hsrcstv += (crtc_hstart - si->overlay.ow.h_start);

src/add-ons/accelerants/via/engine/bes.c

299

moi->hsrcstv *= si->overlay.h_ifactor;

src/add-ons/accelerants/via/engine/bes.c

30

switch(si->dm.space)

src/add-ons/accelerants/via/engine/bes.c

302

moi->hsrcstv += ((uint32)si->overlay.my_ov.h_start) << 16;

src/add-ons/accelerants/via/engine/bes.c

317

if ((si->overlay.ow.h_start + si->overlay.ow.width - 1) > (crtc_hend - 1))

src/add-ons/accelerants/via/engine/bes.c

321

if (si->overlay.ow.h_start > (crtc_hend - 2))

src/add-ons/accelerants/via/engine/bes.c

324

moi->hsrcendv += (si->overlay.ow.width - 2);

src/add-ons/accelerants/via/engine/bes.c

329

moi->hsrcendv += ((si->overlay.ow.h_start + si->overlay.ow.width - 1) - (crtc_hend - 1));

src/add-ons/accelerants/via/engine/bes.c

335

moi->hsrcendv *= si->overlay.h_ifactor;

src/add-ons/accelerants/via/engine/bes.c

337

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16) - moi->hsrcendv;

src/add-ons/accelerants/via/engine/bes.c

342

moi->hsrcendv = (((uint32)((si->overlay.my_ov.h_start + si->overlay.my_ov.width) - 1)) << 16);

src/add-ons/accelerants/via/engine/bes.c

354

moi->a1orgv = (uintptr_t)((vuint32 *)si->overlay.ob.buffer);

src/add-ons/accelerants/via/engine/bes.c

355

moi->a1orgv -= (uintptr_t)((vuint32 *)si->framebuffer);

src/add-ons/accelerants/via/engine/bes.c

368

if (si->overlay.ow.v_start < crtc_vstart)

src/add-ons/accelerants/via/engine/bes.c

37

LOG(8,("Overlay: Invalid colour depth 0x%08x\n", si->dm.space));

src/add-ons/accelerants/via/engine/bes.c

372

if ((si->overlay.ow.v_start + si->overlay.ow.height - 1) < (crtc_vstart + 1))

src/add-ons/accelerants/via/engine/bes.c

376

moi->v1srcstv = (si->overlay.ow.height - 2) * si->overlay.v_ifactor;

src/add-ons/accelerants/via/engine/bes.c

379

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/via/engine/bes.c

385

moi->v1srcstv = (crtc_vstart - si->overlay.ow.v_start) * si->overlay.v_ifactor;

src/add-ons/accelerants/via/engine/bes.c

388

moi->a1orgv += ((moi->v1srcstv >> 16) * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/via/engine/bes.c

393

moi->v1srcstv += (((uint32)si->overlay.my_ov.v_start) << 16);

src/add-ons/accelerants/via/engine/bes.c

394

moi->a1orgv += (si->overlay.my_ov.v_start * si->overlay.ob.bytes_per_row);

src/add-ons/accelerants/via/engine/bes.c

417

if (si->ps.card_arch < K8M800)

src/add-ons/accelerants/via/engine/bes.c

42

(si->dm.timing.pixel_clock * 1000) /

src/add-ons/accelerants/via/engine/bes.c

43

(si->dm.timing.h_total * si->dm.timing.v_total);

src/add-ons/accelerants/via/engine/bes.c

45

si->dm.timing.h_display * si->dm.timing.v_display * refresh * depth;

src/add-ons/accelerants/via/engine/bes.c

477

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/bes.c

485

si->overlay.crtc = !si->crtc_switch_mode;

src/add-ons/accelerants/via/engine/bes.c

493

si->overlay.crtc = si->crtc_switch_mode;

src/add-ons/accelerants/via/engine/bes.c

505

if (si->ps.card_arch < K8M800)

src/add-ons/accelerants/via/engine/bes.c

507

if (si->ps.chip_rev < 0x10)

src/add-ons/accelerants/via/engine/bes.c

580

if (my_ov.h_start > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/via/engine/bes.c

581

my_ov.h_start = ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1);

src/add-ons/accelerants/via/engine/bes.c

582

if (((my_ov.h_start + my_ov.width) - 1) > ((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1))

src/add-ons/accelerants/via/engine/bes.c

583

my_ov.width = ((((ob->width - si->overlay.myBufInfo[offset].slopspace) - 1) - my_ov.h_start) + 1);

src/add-ons/accelerants/via/engine/bes.c

593

si->overlay.ow = *ow;

src/add-ons/accelerants/via/engine/bes.c

594

si->overlay.ob = *ob;

src/add-ons/accelerants/via/engine/bes.c

595

si->overlay.my_ov = my_ov;

src/add-ons/accelerants/via/engine/bes.c

602

(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));

src/add-ons/accelerants/via/engine/bes.c

644

si->overlay.h_ifactor = ifactor;

src/add-ons/accelerants/via/engine/bes.c

69

if (si->dm.timing.h_display > 800)

src/add-ons/accelerants/via/engine/bes.c

72

if (si->dm.timing.v_display > 768) return false;

src/add-ons/accelerants/via/engine/bes.c

750

si->overlay.v_ifactor = ifactor;

src/add-ons/accelerants/via/engine/bes.c

847

if (si->ps.card_arch < K8M800)

src/add-ons/accelerants/via/engine/bes.c

902

if (si->ps.chip_rev < 0x10)

src/add-ons/accelerants/via/engine/bes.c

984

switch(si->dm.space)

src/add-ons/accelerants/via/engine/bes.c

995

r = si->color_data;

src/add-ons/accelerants/via/engine/crtc.c

118

((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc.c

122

((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc.c

126

(((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc.c

131

if (target.timing.h_display == si->ps.p1_timing.h_display)

src/add-ons/accelerants/via/engine/crtc.c

134

if (si->ps.card_type == NV11)

src/add-ons/accelerants/via/engine/crtc.c

148

((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc.c

152

((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc.c

156

((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc.c

312

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display);

src/add-ons/accelerants/via/engine/crtc.c

313

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display);

src/add-ons/accelerants/via/engine/crtc.c

323

DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1));

src/add-ons/accelerants/via/engine/crtc.c

326

DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1));

src/add-ons/accelerants/via/engine/crtc.c

379

if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/via/engine/crtc.c

390

diff = ((si->ps.p1_timing.h_display -

src/add-ons/accelerants/via/engine/crtc.c

394

DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1));

src/add-ons/accelerants/via/engine/crtc.c

399

if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/via/engine/crtc.c

580

offset = si->fbc.bytes_per_row >> 3;

src/add-ons/accelerants/via/engine/crtc.c

596

LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/via/engine/crtc.c

597

LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/via/engine/crtc.c

628

fb = (uint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/via/engine/crtc.c

666

cursor = (uint8*) si->framebuffer;

src/add-ons/accelerants/via/engine/crtc2.c

108

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/crtc2.c

114

((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

118

((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

122

(((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

127

if (target.timing.h_display == si->ps.p2_timing.h_display)

src/add-ons/accelerants/via/engine/crtc2.c

130

if (si->ps.card_type == NV11)

src/add-ons/accelerants/via/engine/crtc2.c

144

((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

148

((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

152

((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *

src/add-ons/accelerants/via/engine/crtc2.c

298

if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));

src/add-ons/accelerants/via/engine/crtc2.c

301

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/crtc2.c

306

iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);

src/add-ons/accelerants/via/engine/crtc2.c

307

iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);

src/add-ons/accelerants/via/engine/crtc2.c

317

DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));

src/add-ons/accelerants/via/engine/crtc2.c

320

DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));

src/add-ons/accelerants/via/engine/crtc2.c

373

if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10)))

src/add-ons/accelerants/via/engine/crtc2.c

384

diff = ((si->ps.p2_timing.h_display -

src/add-ons/accelerants/via/engine/crtc2.c

388

DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));

src/add-ons/accelerants/via/engine/crtc2.c

393

if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10)))

src/add-ons/accelerants/via/engine/crtc2.c

569

offset = si->fbc.bytes_per_row / 8;

src/add-ons/accelerants/via/engine/crtc2.c

590

LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer));

src/add-ons/accelerants/via/engine/crtc2.c

591

LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer));

src/add-ons/accelerants/via/engine/crtc2.c

595

while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&

src/add-ons/accelerants/via/engine/crtc2.c

631

if (si->ps.laptop)

src/add-ons/accelerants/via/engine/crtc2.c

657

fb = (uint32 *) si->framebuffer + curadd;

src/add-ons/accelerants/via/engine/crtc2.c

707

cursor = (uint16*) si->framebuffer;

src/add-ons/accelerants/via/engine/crtc2.c

768

if (yhigh < (si->dm.timing.v_display - 16))

src/add-ons/accelerants/via/engine/crtc2.c

780

while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)

src/add-ons/accelerants/via/engine/dac.c

172

target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;

src/add-ons/accelerants/via/engine/dac.c

191

if (si->ps.card_arch != K8M800)

src/add-ons/accelerants/via/engine/dac.c

242

switch (si->ps.card_arch) {

src/add-ons/accelerants/via/engine/dac.c

285

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/via/engine/dac.c

289

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/via/engine/dac.c

292

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/via/engine/dac.c

295

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/engine/dac.c

299

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/engine/dac.c

304

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/via/engine/dac.c

308

if (req_pclk < (si->ps.min_pixel_vco / 8.0))

src/add-ons/accelerants/via/engine/dac.c

311

req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));

src/add-ons/accelerants/via/engine/dac.c

312

req_pclk = (si->ps.min_pixel_vco / 8.0);

src/add-ons/accelerants/via/engine/dac.c

329

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/via/engine/dac.c

336

if (((si->ps.f_ref / m) < 2.0) || ((si->ps.f_ref / m) > 3.6)) continue;

src/add-ons/accelerants/via/engine/dac.c

339

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/via/engine/dac.c

346

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac.c

366

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/via/engine/dac.c

432

max_pclk = si->ps.max_dac1_clock_8;

src/add-ons/accelerants/via/engine/dac.c

436

max_pclk = si->ps.max_dac1_clock_16;

src/add-ons/accelerants/via/engine/dac.c

439

max_pclk = si->ps.max_dac1_clock_24;

src/add-ons/accelerants/via/engine/dac.c

442

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/engine/dac.c

446

max_pclk = si->ps.max_dac1_clock_32;

src/add-ons/accelerants/via/engine/dac.c

451

max_pclk = si->ps.max_dac1_clock_32dh;

src/add-ons/accelerants/via/engine/dac.c

455

if (req_pclk < (si->ps.min_pixel_vco / 8.0))

src/add-ons/accelerants/via/engine/dac.c

458

req_pclk, (float)(si->ps.min_pixel_vco / 8.0)));

src/add-ons/accelerants/via/engine/dac.c

459

req_pclk = (si->ps.min_pixel_vco / 8.0);

src/add-ons/accelerants/via/engine/dac.c

476

if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))

src/add-ons/accelerants/via/engine/dac.c

485

if (((si->ps.f_ref / m) < 2.0) || ((si->ps.f_ref / m) > 3.6)) continue;

src/add-ons/accelerants/via/engine/dac.c

488

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/via/engine/dac.c

495

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac.c

515

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/via/engine/dac.c

558

switch (si->ps.card_arch)

src/add-ons/accelerants/via/engine/dac.c

571

switch (si->ps.card_type)

src/add-ons/accelerants/via/engine/dac.c

602

if (si->ps.card_type == NV36) discr_low = 3.2;

src/add-ons/accelerants/via/engine/dac.c

618

if (req_sclk < (si->ps.min_system_vco / ((float)p_max)))

src/add-ons/accelerants/via/engine/dac.c

621

req_sclk, (si->ps.min_system_vco / ((float)p_max))));

src/add-ons/accelerants/via/engine/dac.c

622

req_sclk = (si->ps.min_system_vco / ((float)p_max));

src/add-ons/accelerants/via/engine/dac.c

625

if (req_sclk > si->ps.max_system_vco)

src/add-ons/accelerants/via/engine/dac.c

628

req_sclk, (float)si->ps.max_system_vco));

src/add-ons/accelerants/via/engine/dac.c

629

req_sclk = si->ps.max_system_vco;

src/add-ons/accelerants/via/engine/dac.c

639

if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))

src/add-ons/accelerants/via/engine/dac.c

642

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/via/engine/dac.c

648

if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))

src/add-ons/accelerants/via/engine/dac.c

652

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/via/engine/dac.c

658

if (si->ps.ext_pll)

src/add-ons/accelerants/via/engine/dac.c

661

error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac.c

664

error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac.c

684

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/via/engine/dac.c

686

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/via/engine/dac.c

75

r = si->color_data;

src/add-ons/accelerants/via/engine/dac2.c

157

if (si->ps.tmds2_active && !si->settings.pgm_panel)

src/add-ons/accelerants/via/engine/dac2.c

166

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/dac2.c

171

target.timing.pixel_clock = si->ps.p2_timing.pixel_clock;

src/add-ons/accelerants/via/engine/dac2.c

192

if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401);

src/add-ons/accelerants/via/engine/dac2.c

221

switch (si->ps.card_type) {

src/add-ons/accelerants/via/engine/dac2.c

261

max_pclk = si->ps.max_dac2_clock_8;

src/add-ons/accelerants/via/engine/dac2.c

265

max_pclk = si->ps.max_dac2_clock_16;

src/add-ons/accelerants/via/engine/dac2.c

268

max_pclk = si->ps.max_dac2_clock_24;

src/add-ons/accelerants/via/engine/dac2.c

271

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/via/engine/dac2.c

275

max_pclk = si->ps.max_dac2_clock_32;

src/add-ons/accelerants/via/engine/dac2.c

280

max_pclk = si->ps.max_dac2_clock_32dh;

src/add-ons/accelerants/via/engine/dac2.c

284

if (req_pclk < (si->ps.min_video_vco / 16.0))

src/add-ons/accelerants/via/engine/dac2.c

287

req_pclk, (float)(si->ps.min_video_vco / 16.0)));

src/add-ons/accelerants/via/engine/dac2.c

288

req_pclk = (si->ps.min_video_vco / 16.0);

src/add-ons/accelerants/via/engine/dac2.c

305

if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco))

src/add-ons/accelerants/via/engine/dac2.c

308

if (si->ps.ext_pll) f_vco /= 4;

src/add-ons/accelerants/via/engine/dac2.c

315

if (si->ps.card_type == NV36)

src/add-ons/accelerants/via/engine/dac2.c

317

if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;

src/add-ons/accelerants/via/engine/dac2.c

321

if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;

src/add-ons/accelerants/via/engine/dac2.c

325

n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);

src/add-ons/accelerants/via/engine/dac2.c

330

if (si->ps.ext_pll)

src/add-ons/accelerants/via/engine/dac2.c

333

error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac2.c

336

error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));

src/add-ons/accelerants/via/engine/dac2.c

356

f_vco = ((si->ps.f_ref / m) * n);

src/add-ons/accelerants/via/engine/dac2.c

358

if (si->ps.ext_pll) f_vco *= 4;

src/add-ons/accelerants/via/engine/dac2.c

78

r = si->color_data;

src/add-ons/accelerants/via/engine/general.c

103

si->ps.card_type = VT3022;

src/add-ons/accelerants/via/engine/general.c

104

si->ps.card_arch = CLE266;

src/add-ons/accelerants/via/engine/general.c

109

si->ps.card_type = VT3108;

src/add-ons/accelerants/via/engine/general.c

110

si->ps.card_arch = K8M800;

src/add-ons/accelerants/via/engine/general.c

115

si->ps.card_type = VT3122;

src/add-ons/accelerants/via/engine/general.c

116

si->ps.card_arch = CLE266;

src/add-ons/accelerants/via/engine/general.c

121

si->ps.card_type = VT3205;

src/add-ons/accelerants/via/engine/general.c

122

si->ps.card_arch = KM400;

src/add-ons/accelerants/via/engine/general.c

127

si->ps.card_type = VT7205;

src/add-ons/accelerants/via/engine/general.c

128

si->ps.card_arch = KM400;

src/add-ons/accelerants/via/engine/general.c

146

if (si->fbc.frame_buffer == NULL)

src/add-ons/accelerants/via/engine/general.c

155

((uint32 *)si->fbc.frame_buffer)[offset] = value;

src/add-ons/accelerants/via/engine/general.c

163

if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;

src/add-ons/accelerants/via/engine/general.c

17

#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \

src/add-ons/accelerants/via/engine/general.c

187

if (si->ps.pins_status != B_OK)

src/add-ons/accelerants/via/engine/general.c

196

switch(si->ps.card_type)

src/add-ons/accelerants/via/engine/general.c

293

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/general.c

322

LOG(4,("POWERUP: Chip revision is $%02x\n", si->ps.chip_rev));

src/add-ons/accelerants/via/engine/general.c

335

if (!si->settings.usebios)

src/add-ons/accelerants/via/engine/general.c

355

if (si->settings.logmask & 0x80000000) eng_dump_configuration_space();

src/add-ons/accelerants/via/engine/general.c

358

setup_virtualized_heads(si->ps.crtc2_prim);

src/add-ons/accelerants/via/engine/general.c

371

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/general.c

374

if (si->ps.card_type != NV11)

src/add-ons/accelerants/via/engine/general.c

415

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/general.c

421

si->crtc_switch_mode = !si->ps.crtc2_prim;

src/add-ons/accelerants/via/engine/general.c

426

si->crtc_switch_mode = si->ps.crtc2_prim;

src/add-ons/accelerants/via/engine/general.c

429

setup_virtualized_heads(si->crtc_switch_mode);

src/add-ons/accelerants/via/engine/general.c

461

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/general.c

480

si->overlay.crtc = false;

src/add-ons/accelerants/via/engine/general.c

546

switch (si->ps.card_arch)

src/add-ons/accelerants/via/engine/general.c

569

switch (si->ps.card_type)

src/add-ons/accelerants/via/engine/general.c

588

switch (si->ps.card_arch)

src/add-ons/accelerants/via/engine/general.c

621

if (si->ps.card_type != NV31) break;

src/add-ons/accelerants/via/engine/general.c

641

switch (si->ps.card_type)

src/add-ons/accelerants/via/engine/general.c

96

si->ps.laptop = false;

src/add-ons/accelerants/via/engine/globals.c

13

shared_info *si;

src/add-ons/accelerants/via/engine/globals.h

2

extern shared_info *si;

src/add-ons/accelerants/via/engine/i2c.c

55

if (!si->ps.secondary_head) return result;

src/add-ons/accelerants/via/engine/info.c

1024

si->ps.secondary_head = true;

src/add-ons/accelerants/via/engine/info.c

1027

si->ps.secondary_head = false;

src/add-ons/accelerants/via/engine/info.c

1038

if (si->ps.ext_pll) LOG(2,("extended\n")); else LOG(2,("standard\n"));

src/add-ons/accelerants/via/engine/info.c

1039

LOG(2,("f_ref: %fMhz\n", si->ps.f_ref));

src/add-ons/accelerants/via/engine/info.c

1040

LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco));

src/add-ons/accelerants/via/engine/info.c

1041

LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));

src/add-ons/accelerants/via/engine/info.c

1042

LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco));

src/add-ons/accelerants/via/engine/info.c

1043

LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco));

src/add-ons/accelerants/via/engine/info.c

1044

LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco));

src/add-ons/accelerants/via/engine/info.c

1045

LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco));

src/add-ons/accelerants/via/engine/info.c

1046

LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock));

src/add-ons/accelerants/via/engine/info.c

1047

LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock));

src/add-ons/accelerants/via/engine/info.c

1048

LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock));

src/add-ons/accelerants/via/engine/info.c

1049

LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8));

src/add-ons/accelerants/via/engine/info.c

1050

LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16));

src/add-ons/accelerants/via/engine/info.c

1051

LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24));

src/add-ons/accelerants/via/engine/info.c

1052

LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32));

src/add-ons/accelerants/via/engine/info.c

1053

LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh));

src/add-ons/accelerants/via/engine/info.c

1054

LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock));

src/add-ons/accelerants/via/engine/info.c

1055

LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8));

src/add-ons/accelerants/via/engine/info.c

1056

LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16));

src/add-ons/accelerants/via/engine/info.c

1057

LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24));

src/add-ons/accelerants/via/engine/info.c

1058

LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32));

src/add-ons/accelerants/via/engine/info.c

1059

LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh));

src/add-ons/accelerants/via/engine/info.c

1061

if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/via/engine/info.c

1063

if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n"));

src/add-ons/accelerants/via/engine/info.c

1065

switch (si->ps.tvout_chip_type)

src/add-ons/accelerants/via/engine/info.c

112

if (si->settings.memory != 0)

src/add-ons/accelerants/via/engine/info.c

1124

LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0))));

src/add-ons/accelerants/via/engine/info.c

1126

if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n"));

src/add-ons/accelerants/via/engine/info.c

1127

if (si->ps.tmds1_active)

src/add-ons/accelerants/via/engine/info.c

1130

if (si->ps.slaved_tmds1) LOG(2,("slaved\n")); else LOG(2,("master\n"));

src/add-ons/accelerants/via/engine/info.c

1132

si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.panel1_aspect));

src/add-ons/accelerants/via/engine/info.c

1134

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/info.c

1137

if (si->ps.slaved_tmds2) LOG(2,("slaved\n")); else LOG(2,("master\n"));

src/add-ons/accelerants/via/engine/info.c

1139

si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.panel2_aspect));

src/add-ons/accelerants/via/engine/info.c

1141

LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors));

src/add-ons/accelerants/via/engine/info.c

115

si->ps.memory_size = si->settings.memory * 1024 * 1024;

src/add-ons/accelerants/via/engine/info.c

119

si->ps.tvout = false;

src/add-ons/accelerants/via/engine/info.c

120

si->ps.tvout_chip_type = NONE;

src/add-ons/accelerants/via/engine/info.c

139

if (si->ps.secondary_head && si->settings.switchhead)

src/add-ons/accelerants/via/engine/info.c

142

si->ps.crtc2_prim = !si->ps.crtc2_prim;

src/add-ons/accelerants/via/engine/info.c

192

if (si->ps.secondary_head)

src/add-ons/accelerants/via/engine/info.c

218

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/via/engine/info.c

219

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/via/engine/info.c

220

si->ps.panel1_aspect = 0;

src/add-ons/accelerants/via/engine/info.c

221

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/via/engine/info.c

222

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/via/engine/info.c

223

si->ps.panel2_aspect = 0;

src/add-ons/accelerants/via/engine/info.c

224

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

225

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/via/engine/info.c

226

si->ps.master_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

227

si->ps.master_tmds2 = false;

src/add-ons/accelerants/via/engine/info.c

228

si->ps.tmds1_active = false;

src/add-ons/accelerants/via/engine/info.c

229

si->ps.tmds2_active = false;

src/add-ons/accelerants/via/engine/info.c

261

si->ps.slaved_tmds1 = true;

src/add-ons/accelerants/via/engine/info.c

262

si->ps.tmds1_active = true;

src/add-ons/accelerants/via/engine/info.c

263

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/via/engine/info.c

264

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/via/engine/info.c

268

if (si->ps.secondary_head && slaved_for_dev2 && !tvout2)

src/add-ons/accelerants/via/engine/info.c

274

si->ps.slaved_tmds2 = true;

src/add-ons/accelerants/via/engine/info.c

275

si->ps.tmds2_active = true;

src/add-ons/accelerants/via/engine/info.c

276

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/via/engine/info.c

277

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/via/engine/info.c

281

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/via/engine/info.c

282

!si->ps.slaved_tmds1 && !tvout1)

src/add-ons/accelerants/via/engine/info.c

288

si->ps.master_tmds1 = true;

src/add-ons/accelerants/via/engine/info.c

289

si->ps.tmds1_active = true;

src/add-ons/accelerants/via/engine/info.c

290

si->ps.p1_timing.h_display = width;

src/add-ons/accelerants/via/engine/info.c

291

si->ps.p1_timing.v_display = height;

src/add-ons/accelerants/via/engine/info.c

295

if ((si->ps.card_type == NV11) &&

src/add-ons/accelerants/via/engine/info.c

296

si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2)

src/add-ons/accelerants/via/engine/info.c

302

si->ps.master_tmds2 = true;

src/add-ons/accelerants/via/engine/info.c

303

si->ps.tmds2_active = true;

src/add-ons/accelerants/via/engine/info.c

304

si->ps.p2_timing.h_display = width;

src/add-ons/accelerants/via/engine/info.c

305

si->ps.p2_timing.v_display = height;

src/add-ons/accelerants/via/engine/info.c

31

si->ps.pins_status = B_ERROR;

src/add-ons/accelerants/via/engine/info.c

312

if (si->ps.laptop && si->ps.tmds1_active && si->ps.tmds2_active &&

src/add-ons/accelerants/via/engine/info.c

314

(si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) &&

src/add-ons/accelerants/via/engine/info.c

315

(si->ps.p1_timing.v_display == si->ps.p2_timing.v_display))

src/add-ons/accelerants/via/engine/info.c

319

if (si->ps.card_type == NV11)

src/add-ons/accelerants/via/engine/info.c

322

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

323

si->ps.master_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

324

si->ps.tmds1_active = false;

src/add-ons/accelerants/via/engine/info.c

325

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/via/engine/info.c

326

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/via/engine/info.c

333

si->ps.slaved_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

334

si->ps.master_tmds1 = false;

src/add-ons/accelerants/via/engine/info.c

335

si->ps.tmds1_active = false;

src/add-ons/accelerants/via/engine/info.c

336

si->ps.p1_timing.h_display = 0;

src/add-ons/accelerants/via/engine/info.c

337

si->ps.p1_timing.v_display = 0;

src/add-ons/accelerants/via/engine/info.c

342

si->ps.slaved_tmds2 = false;

src/add-ons/accelerants/via/engine/info.c

343

si->ps.master_tmds2 = false;

src/add-ons/accelerants/via/engine/info.c

344

si->ps.tmds2_active = false;

src/add-ons/accelerants/via/engine/info.c

345

si->ps.p2_timing.h_display = 0;

src/add-ons/accelerants/via/engine/info.c

346

si->ps.p2_timing.v_display = 0;

src/add-ons/accelerants/via/engine/info.c

35

rom = (uint8 *) si->rom_mirror;

src/add-ons/accelerants/via/engine/info.c

352

if (si->ps.tmds1_active)

src/add-ons/accelerants/via/engine/info.c

355

si->ps.panel1_aspect =

src/add-ons/accelerants/via/engine/info.c

356

(si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display));

src/add-ons/accelerants/via/engine/info.c

358

si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

359

si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

360

si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

362

si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

363

si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

364

si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

366

si->ps.p1_timing.flags = 0;

src/add-ons/accelerants/via/engine/info.c

367

if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/via/engine/info.c

368

if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/via/engine/info.c

371

si->ps.p1_timing.pixel_clock =

src/add-ons/accelerants/via/engine/info.c

372

(si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000;

src/add-ons/accelerants/via/engine/info.c

374

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/info.c

377

si->ps.panel2_aspect =

src/add-ons/accelerants/via/engine/info.c

378

(si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display));

src/add-ons/accelerants/via/engine/info.c

380

si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

381

si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

382

si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

384

si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

385

si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

386

si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1;

src/add-ons/accelerants/via/engine/info.c

388

si->ps.p2_timing.flags = 0;

src/add-ons/accelerants/via/engine/info.c

389

if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC;

src/add-ons/accelerants/via/engine/info.c

390

if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC;

src/add-ons/accelerants/via/engine/info.c

393

si->ps.p2_timing.pixel_clock =

src/add-ons/accelerants/via/engine/info.c

394

(si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000;

src/add-ons/accelerants/via/engine/info.c

427

if(si->ps.secondary_head)

src/add-ons/accelerants/via/engine/info.c

463

si->ps.monitors = 0x00;

src/add-ons/accelerants/via/engine/info.c

465

si->ps.crtc2_prim = false;

src/add-ons/accelerants/via/engine/info.c

470

if (si->ps.card_type != NV11)

src/add-ons/accelerants/via/engine/info.c

477

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/via/engine/info.c

478

if (si->ps.tmds2_active) si->ps.monitors |= 0x10;

src/add-ons/accelerants/via/engine/info.c

481

if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;

src/add-ons/accelerants/via/engine/info.c

483

if (eng_dac2_crt_connected()) si->ps.monitors |= 0x20;

src/add-ons/accelerants/via/engine/info.c

487

switch (si->ps.monitors)

src/add-ons/accelerants/via/engine/info.c

518

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

524

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

535

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

54

si->ps.pins_status = B_OK;

src/add-ons/accelerants/via/engine/info.c

546

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

559

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/via/engine/info.c

570

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/via/engine/info.c

571

if (si->ps.tmds2_active) si->ps.monitors |= 0x10;

src/add-ons/accelerants/via/engine/info.c

574

if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;

src/add-ons/accelerants/via/engine/info.c

579

switch (si->ps.monitors)

src/add-ons/accelerants/via/engine/info.c

606

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

617

si->ps.crtc2_prim = true;

src/add-ons/accelerants/via/engine/info.c

620

LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors));

src/add-ons/accelerants/via/engine/info.c

629

si->ps.tmds1_active = false;

src/add-ons/accelerants/via/engine/info.c

630

si->ps.tmds2_active = false;

src/add-ons/accelerants/via/engine/info.c

634

if (si->ps.tmds1_active) si->ps.monitors |= 0x01;

src/add-ons/accelerants/via/engine/info.c

638

if (1/*eng_dac_crt_connected()*/) si->ps.monitors |= 0x02;

src/add-ons/accelerants/via/engine/info.c

646

if (si->ps.tmds1_active)

src/add-ons/accelerants/via/engine/info.c

649

p1->timing = si->ps.p1_timing;

src/add-ons/accelerants/via/engine/info.c

662

if (si->ps.tmds2_active)

src/add-ons/accelerants/via/engine/info.c

665

p2->timing = si->ps.p2_timing;

src/add-ons/accelerants/via/engine/info.c

681

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/via/engine/info.c

683

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

685

si->ps.max_system_vco = 230;

src/add-ons/accelerants/via/engine/info.c

686

si->ps.min_system_vco = 20;

src/add-ons/accelerants/via/engine/info.c

687

si->ps.max_pixel_vco = 400; /* VESA BIOS uses upto 433Mhz */

src/add-ons/accelerants/via/engine/info.c

688

si->ps.min_pixel_vco = 50; /* VESA BIOS uses downto 53.2Mhz */

src/add-ons/accelerants/via/engine/info.c

689

si->ps.max_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

690

si->ps.min_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

691

si->ps.max_dac1_clock = 230;

src/add-ons/accelerants/via/engine/info.c

692

si->ps.max_dac1_clock_8 = 230;

src/add-ons/accelerants/via/engine/info.c

693

si->ps.max_dac1_clock_16 = 230;

src/add-ons/accelerants/via/engine/info.c

695

si->ps.max_dac1_clock_24 = 200;

src/add-ons/accelerants/via/engine/info.c

696

si->ps.max_dac1_clock_32 = 180;

src/add-ons/accelerants/via/engine/info.c

697

si->ps.max_dac1_clock_32dh = 180;

src/add-ons/accelerants/via/engine/info.c

699

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/via/engine/info.c

700

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/via/engine/info.c

701

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/via/engine/info.c

702

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/via/engine/info.c

703

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/via/engine/info.c

705

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/via/engine/info.c

707

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

708

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

710

si->ps.std_engine_clock = 90;

src/add-ons/accelerants/via/engine/info.c

711

si->ps.std_memory_clock = 110;

src/add-ons/accelerants/via/engine/info.c

717

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

719

si->ps.max_system_vco = 300;

src/add-ons/accelerants/via/engine/info.c

720

si->ps.min_system_vco = 128;

src/add-ons/accelerants/via/engine/info.c

721

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/via/engine/info.c

722

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/via/engine/info.c

723

si->ps.max_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

724

si->ps.min_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

725

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/via/engine/info.c

726

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/via/engine/info.c

727

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/via/engine/info.c

729

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/via/engine/info.c

730

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/via/engine/info.c

731

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/via/engine/info.c

733

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/via/engine/info.c

734

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/via/engine/info.c

735

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/via/engine/info.c

736

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/via/engine/info.c

737

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/via/engine/info.c

739

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/via/engine/info.c

741

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

742

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

744

si->ps.std_engine_clock = 125;

src/add-ons/accelerants/via/engine/info.c

745

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/via/engine/info.c

751

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

753

si->ps.max_system_vco = 300;

src/add-ons/accelerants/via/engine/info.c

754

si->ps.min_system_vco = 128;

src/add-ons/accelerants/via/engine/info.c

755

si->ps.max_pixel_vco = 300;

src/add-ons/accelerants/via/engine/info.c

756

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/via/engine/info.c

757

si->ps.max_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

758

si->ps.min_video_vco = 0;

src/add-ons/accelerants/via/engine/info.c

759

si->ps.max_dac1_clock = 300;

src/add-ons/accelerants/via/engine/info.c

760

si->ps.max_dac1_clock_8 = 300;

src/add-ons/accelerants/via/engine/info.c

761

si->ps.max_dac1_clock_16 = 300;

src/add-ons/accelerants/via/engine/info.c

763

si->ps.max_dac1_clock_24 = 270;

src/add-ons/accelerants/via/engine/info.c

764

si->ps.max_dac1_clock_32 = 230;

src/add-ons/accelerants/via/engine/info.c

765

si->ps.max_dac1_clock_32dh = 230;

src/add-ons/accelerants/via/engine/info.c

767

si->ps.max_dac2_clock = 0;

src/add-ons/accelerants/via/engine/info.c

768

si->ps.max_dac2_clock_8 = 0;

src/add-ons/accelerants/via/engine/info.c

769

si->ps.max_dac2_clock_16 = 0;

src/add-ons/accelerants/via/engine/info.c

770

si->ps.max_dac2_clock_24 = 0;

src/add-ons/accelerants/via/engine/info.c

771

si->ps.max_dac2_clock_32 = 0;

src/add-ons/accelerants/via/engine/info.c

773

si->ps.max_dac2_clock_32dh = 0;

src/add-ons/accelerants/via/engine/info.c

775

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

776

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

778

si->ps.std_engine_clock = 100;

src/add-ons/accelerants/via/engine/info.c

779

si->ps.std_memory_clock = 125;

src/add-ons/accelerants/via/engine/info.c

785

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

787

si->ps.max_system_vco = 350;

src/add-ons/accelerants/via/engine/info.c

788

si->ps.min_system_vco = 128;

src/add-ons/accelerants/via/engine/info.c

789

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/via/engine/info.c

790

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/via/engine/info.c

791

si->ps.max_video_vco = 350;

src/add-ons/accelerants/via/engine/info.c

792

si->ps.min_video_vco = 128;

src/add-ons/accelerants/via/engine/info.c

793

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/via/engine/info.c

794

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

795

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

797

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

798

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

799

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

801

if (si->ps.card_type < NV17)

src/add-ons/accelerants/via/engine/info.c

806

si->ps.max_dac2_clock = 200;

src/add-ons/accelerants/via/engine/info.c

807

si->ps.max_dac2_clock_8 = 200;

src/add-ons/accelerants/via/engine/info.c

808

si->ps.max_dac2_clock_16 = 200;

src/add-ons/accelerants/via/engine/info.c

809

si->ps.max_dac2_clock_24 = 200;

src/add-ons/accelerants/via/engine/info.c

81

switch (si->ps.card_arch)

src/add-ons/accelerants/via/engine/info.c

810

si->ps.max_dac2_clock_32 = 200;

src/add-ons/accelerants/via/engine/info.c

812

si->ps.max_dac2_clock_32dh = 180;

src/add-ons/accelerants/via/engine/info.c

818

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/via/engine/info.c

819

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

820

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

822

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

823

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

824

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

827

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

828

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

830

si->ps.std_engine_clock = 120;

src/add-ons/accelerants/via/engine/info.c

831

si->ps.std_memory_clock = 150;

src/add-ons/accelerants/via/engine/info.c

837

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

839

si->ps.max_system_vco = 350;

src/add-ons/accelerants/via/engine/info.c

840

si->ps.min_system_vco = 128;

src/add-ons/accelerants/via/engine/info.c

841

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/via/engine/info.c

842

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/via/engine/info.c

843

si->ps.max_video_vco = 350;

src/add-ons/accelerants/via/engine/info.c

844

si->ps.min_video_vco = 128;

src/add-ons/accelerants/via/engine/info.c

845

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/via/engine/info.c

846

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

847

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

849

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

850

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

851

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

855

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/via/engine/info.c

856

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

857

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

859

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

860

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

861

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

863

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

864

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

866

si->ps.std_engine_clock = 175;

src/add-ons/accelerants/via/engine/info.c

867

si->ps.std_memory_clock = 200;

src/add-ons/accelerants/via/engine/info.c

875

switch (si->ps.card_type)

src/add-ons/accelerants/via/engine/info.c

881

si->ps.ext_pll = true;

src/add-ons/accelerants/via/engine/info.c

885

si->ps.ext_pll = false;

src/add-ons/accelerants/via/engine/info.c

889

si->ps.max_system_vco = 350;

src/add-ons/accelerants/via/engine/info.c

890

si->ps.min_system_vco = 128;

src/add-ons/accelerants/via/engine/info.c

891

si->ps.max_pixel_vco = 350;

src/add-ons/accelerants/via/engine/info.c

892

si->ps.min_pixel_vco = 128;

src/add-ons/accelerants/via/engine/info.c

893

si->ps.max_video_vco = 350;

src/add-ons/accelerants/via/engine/info.c

894

si->ps.min_video_vco = 128;

src/add-ons/accelerants/via/engine/info.c

895

si->ps.max_dac1_clock = 350;

src/add-ons/accelerants/via/engine/info.c

896

si->ps.max_dac1_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

897

si->ps.max_dac1_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

899

si->ps.max_dac1_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

900

si->ps.max_dac1_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

901

si->ps.max_dac1_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

905

si->ps.max_dac2_clock = 350;

src/add-ons/accelerants/via/engine/info.c

906

si->ps.max_dac2_clock_8 = 350;

src/add-ons/accelerants/via/engine/info.c

907

si->ps.max_dac2_clock_16 = 350;

src/add-ons/accelerants/via/engine/info.c

909

si->ps.max_dac2_clock_24 = 320;

src/add-ons/accelerants/via/engine/info.c

910

si->ps.max_dac2_clock_32 = 280;

src/add-ons/accelerants/via/engine/info.c

911

si->ps.max_dac2_clock_32dh = 250;

src/add-ons/accelerants/via/engine/info.c

913

si->ps.primary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

914

si->ps.secondary_dvi = false;

src/add-ons/accelerants/via/engine/info.c

916

si->ps.std_engine_clock = 190;

src/add-ons/accelerants/via/engine/info.c

917

si->ps.std_memory_clock = 190;

src/add-ons/accelerants/via/engine/info.c

924

if (si->ps.card_arch == CLE266)

src/add-ons/accelerants/via/engine/info.c

936

si->ps.memory_size = (ram_size + 1) * 512 * 1024;

src/add-ons/accelerants/via/engine/info.c

943

si->ps.memory_size = ram_size * 4 * 1024 * 1024;

src/add-ons/accelerants/via/engine/info.c

948

si->ps.memory_size = 16 * 1024 * 1024;

src/add-ons/accelerants/via/engine/info.c

959

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/via/engine/info.c

961

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/via/engine/info.c

964

si->ps.secondary_head = false;

src/add-ons/accelerants/via/engine/info.c

974

si->ps.f_ref = 14.31818;

src/add-ons/accelerants/via/engine/info.c

976

si->ps.f_ref = 13.50000;

src/add-ons/accelerants/via/engine/info.c

997

if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000;

src/add-ons/accelerants/via/engine/proto.h

19

uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \

src/add-ons/accelerants/via/engine/proto.h

20

uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \

src/add-ons/accelerants/via/engine/tvout.c

111

if (req_pclks_field < (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0))

src/add-ons/accelerants/via/engine/tvout.c

113

req_pclks_field = (((si->ps.min_video_vco * 1000000) / fields_sec) / 8.0);

src/add-ons/accelerants/via/engine/tvout.c

130

if ((vco_clks_field >= ((si->ps.min_video_vco * 1000000) / fields_sec)) &&

src/add-ons/accelerants/via/engine/tvout.c

131

(vco_clks_field <= ((si->ps.max_video_vco * 1000000) / fields_sec)))

src/add-ons/accelerants/via/engine/tvout.c

137

n = (int)(((vco_clks_field * m) / ((si->ps.f_ref * 1000000) / fields_sec)) + 0.5);

src/add-ons/accelerants/via/engine/tvout.c

144

(((uint32)((si->ps.f_ref * 1000000) / fields_sec)) * n) / ((float)(m * p));

src/add-ons/accelerants/via/engine/tvout.c

171

f_vco = (si->ps.f_ref / m) * n;

src/add-ons/accelerants/via/engine/tvout.c

204

if (si->ps.f_ref == 27.000)

src/add-ons/accelerants/via/engine/tvout.c

223

f_vco = (si->ps.f_ref / (m + 1)) * (n + 1);

src/add-ons/accelerants/via/engine/tvout.c

226

switch(si->ps.card_type)

src/add-ons/accelerants/via/engine/tvout.c

57

switch(si->ps.card_type)

src/add-ons/accelerants/via/engine/tvout.c

83

max_pclks_field = (si->ps.max_dac2_clock_16 * 1000000) / fields_sec;

src/add-ons/accelerants/via/engine/tvout.c

86

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/via/engine/tvout.c

90

max_pclks_field = (si->ps.max_dac2_clock_32 * 1000000) / fields_sec;

src/add-ons/accelerants/via/engine/tvout.c

95

max_pclks_field = (si->ps.max_dac2_clock_32dh * 1000000) / fields_sec;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

125

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

139

si.videoMemPCI = videoRamAddr;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

142

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

148

(void**)&si.videoMemAddr);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

151

si.videoMemArea, (uint32)(si.videoMemAddr), videoRamSize);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

153

if (si.videoMemArea < 0) {

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

155

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

161

(void**)&si.videoMemAddr);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

164

if (si.videoMemArea < 0)

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

165

return si.videoMemArea;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

172

si.regsArea = map_physical_memory("3DFX mmio registers",

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

180

if (si.regsArea < 0) {

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

181

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

182

si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

185

TRACE("leave MapDevice(); result: %" B_PRId32 "\n", si.regsArea);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

186

return si.regsArea;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

193

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

195

if (si.regsArea >= 0)

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

196

delete_area(si.regsArea);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

197

if (si.videoMemArea >= 0)

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

198

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

200

si.regsArea = si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

201

si.videoMemAddr = (addr_t)NULL;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

228

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

230

memset(&si, 0, sharedSize);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

234

si.vendorID = pciInfo.vendor_id;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

235

si.deviceID = pciInfo.device_id;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

236

si.revision = pciInfo.revision;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

237

si.chipType = di.pChipInfo->chipType;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

238

strcpy(si.chipName, di.pChipInfo->chipName);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

1108

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

1120

if (si.bInterruptAssigned) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

1127

if (si.vertBlankSem >= 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

1128

delete_sem(si.vertBlankSem);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

1129

si.vertBlankSem = -1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

409

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

410

M64_Params& params = si.m64Params;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

413

si.panelX = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

414

si.panelY = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

457

if (si.chipType == MACH64_MOBILITY) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

461

si.panelX = BIOS16(lcdPanelInfo + 25);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

462

si.panelY = BIOS16(lcdPanelInfo + 27);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

463

TRACE("Mobility LCD Panel size: %dx%d\n", si.panelX, si.panelY);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

488

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

489

R128_PLLParams& pll = si.r128PLLParams;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

496

si.panelX = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

497

si.panelY = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

498

si.panelPowerDelay = 1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

548

if (si.chipType == RAGE128_MOBILITY) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

570

si.panelX = BIOS16(fpStart + 25);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

571

si.panelY = BIOS16(fpStart + 27);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

572

si.panelPowerDelay = BIOS8(fpStart + 56);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

574

si.panelX, si.panelY, BIOS16(fpStart + 29),

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

575

si.panelPowerDelay);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

594

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

613

si.videoMemPCI = videoRamAddr;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

616

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

622

(void**)&(si.videoMemAddr));

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

624

if (si.videoMemArea < 0) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

626

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

632

(void**)&(si.videoMemAddr));

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

635

if (si.videoMemArea < 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

636

return si.videoMemArea;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

646

if (MACH64_FAMILY(si.chipType) && (regsBase == 0 || regAreaSize == 0)) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

648

addr_t regs = addr_t(si.videoMemAddr) + regsOffset;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

651

if (si.deviceID != (chipInfo & M64_CFG_CHIP_TYPE)) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

654

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

655

si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

668

si.regsArea = map_physical_memory("ATI mmio registers",

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

676

if (si.regsArea < 0) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

677

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

678

si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

681

return si.regsArea;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

688

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

690

if (si.regsArea >= 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

691

delete_area(si.regsArea);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

692

if (si.videoMemArea >= 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

693

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

695

si.regsArea = si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

696

si.videoMemAddr = (addr_t)NULL;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

738

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

741

si.bInterruptAssigned = false; // indicate interrupt not assigned yet

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

744

si.vertBlankSem = create_sem(0, di.name);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

745

if (si.vertBlankSem < 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

756

status = set_sem_owner(si.vertBlankSem, threadInfo.team);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

768

si.bInterruptAssigned = true; // we can use interrupt related functions

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

773

delete_sem(si.vertBlankSem);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

774

si.vertBlankSem = -1;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

807

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

809

memset(&si, 0, sharedSize);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

812

si.vesaModeTableOffset = sharedSize;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

813

si.vesaModeCount = vesaModeTableSize / sizeof(VesaMode);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

815

memcpy((uint8*)&si + si.vesaModeTableOffset, vesaModes,

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

821

si.vendorID = pciInfo.vendor_id;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

822

si.deviceID = pciInfo.device_id;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

823

si.revision = pciInfo.revision;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

824

si.chipType = di.pChipInfo->chipType;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

825

strcpy(si.chipName, di.pChipInfo->chipName);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

827

TRACE("Chip revision: 0x%x\n", si.revision);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

831

if (si.chipType == MACH64_264GT && si.revision & 0x7)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

832

si.chipType = MACH64_264GTB;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

836

if (si.chipType == MACH64_264VT && si.revision & 0x7)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

837

si.chipType = MACH64_264VTB;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

845

if (MACH64_FAMILY(si.chipType)) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

858

else if (RAGE128_FAMILY(si.chipType))

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

871

TRACE("Interrupt assigned: %s\n", si.bInterruptAssigned ? "yes" : "no");

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

197

di->si = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

279

ET6000SharedInfo *si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

280

int32 *flags = &(si->flags);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

294

switch (et6000aclInterruptCause(si->mmRegs)) {

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

299

et6000aclReadInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

303

et6000aclWriteInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

307

et6000aclReadInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

308

et6000aclWriteInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

369

ET6000SharedInfo *si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

384

si->pciConfigSpace = (uint16)di->pcii.u.h0.base_registers[1];

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

397

si->memoryArea = map_physical_memory(buffer,

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

402

&(si->memory));

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

404

si->framebuffer = si->memory;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

405

si->mmRegs = (void *)((uint32)si->memory + 0x003fff00);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

406

si->emRegs = (void *)((uint32)si->memory + 0x003fe000);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

409

si->physMemory = si->physFramebuffer =

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

412

si->memSize = et6000GetOnboardMemorySize(si->pciConfigSpace, si->memory);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

415

return si->memoryArea;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

419

ET6000SharedInfo *si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

422

ddprintf((" memoryArea: %ld\n", si->memoryArea));

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

424

if (si->memoryArea >= 0)

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

425

delete_area(si->memoryArea);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

426

si->memoryArea = -1;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

427

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

428

si->physFramebuffer = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

429

si->memory = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

430

si->physMemory = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

438

ET6000SharedInfo *si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

46

ET6000SharedInfo *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

468

di->sharedArea = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(ET6000SharedInfo) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

477

si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

480

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

481

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

482

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

484

si->pixelClockMax16 = 135000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

485

si->pixelClockMax24 = 135000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

486

if (si->vendor_id == 0x100C) { /* Tseng Labs, Inc. */

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

487

switch (si->device_id) {

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

489

if (si->revision < 0x70) { /* ET6000 */

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

490

si->pixelClockMax16 = 135000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

491

si->pixelClockMax24 = 135000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

494

si->pixelClockMax16 = 175000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

495

si->pixelClockMax24 = 175000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

499

si->pixelClockMax16 = 220000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

500

si->pixelClockMax24 = 220000;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

515

et6000aclReadInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

516

et6000aclWriteInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

517

et6000aclMasterInterruptDisable(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

542

di->si = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

588

ET6000SharedInfo *si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

599

et6000aclReadInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

600

et6000aclWriteInterruptClear(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

601

et6000aclMasterInterruptDisable(si->mmRegs);

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

612

di->si = NULL;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

703

ET6000SharedInfo *si = di->si;

src/add-ons/kernel/drivers/graphics/et6x00/driver.c

706

if (si) {

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

263

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

264

memset(&si, 0, sharedSize);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

265

si.regsArea = -1; // indicate area has not yet been created

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

266

si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

270

si.vendorID = pciInfo.vendor_id;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

271

si.deviceID = pciInfo.device_id;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

272

si.revision = pciInfo.revision;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

273

strcpy(si.chipName, di.pChipInfo->chipName);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

285

si.regsArea = map_physical_memory("i810 mmio registers",

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

292

if (si.regsArea < 0) {

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

293

TRACE("Unable to map MMIO, error: 0x%" B_PRIx32 "\n", si.regsArea);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

294

return si.regsArea;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

327

si.videoMemSize = 4 * 1024 * 1024;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

328

si.videoMemArea = create_area("video memory", (void**)&(si.videoMemAddr),

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

329

B_ANY_ADDRESS, si.videoMemSize, B_FULL_LOCK,

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

331

if (si.videoMemArea < B_OK) {

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

333

si.videoMemArea);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

340

for (uint32 offset = 0; offset < si.videoMemSize; offset += B_PAGE_SIZE) {

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

341

status = get_memory_map((void *)(si.videoMemAddr + offset),

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

350

si.videoMemPCI = entry.address;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

367

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

368

if (si.regsArea >= 0)

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

369

delete_area(si.regsArea);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

370

if (si.videoMemArea >= 0)

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

371

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

307

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

344

si->use_clone_bugfix = 1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

348

si->use_clone_bugfix = 0;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

357

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/matrox/driver.c

362

B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),

src/add-ons/kernel/drivers/graphics/matrox/driver.c

364

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

367

if (si->regs_area < 0) return si->regs_area;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

390

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

391

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

418

memcpy (si->rom_mirror, pd->di[index].rom_mirror, 32768);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

423

memcpy (si->rom_mirror, rom_temp, 32768);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

429

memcpy (si->rom_mirror, rom_temp, 32768);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

432

if (current_settings.dumprom) dumprom (si->rom_mirror, 32768, di->pcii);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

448

si->pseudo_dma_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/matrox/driver.c

454

&(si->pseudo_dma));

src/add-ons/kernel/drivers/graphics/matrox/driver.c

457

if (si->pseudo_dma_area < 0) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

458

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

459

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

460

return si->pseudo_dma_area;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

497

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/matrox/driver.c

503

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/matrox/driver.c

506

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

507

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/matrox/driver.c

513

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/matrox/driver.c

517

if (si->fb_area < 0)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

523

delete_area(si->dma_buffer_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

524

si->dma_buffer_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

525

delete_area(si->pseudo_dma_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

526

si->pseudo_dma_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

528

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

529

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

53

shared_info *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/matrox/driver.c

530

return si->fb_area;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

533

si->framebuffer_pci = (void *)(addr_t)di->pcii.u.h0.base_registers_pci[frame_buffer];

src/add-ons/kernel/drivers/graphics/matrox/driver.c

536

si->settings = current_settings;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

539

return si->fb_area;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

543

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

552

if (si->regs_area >= 0) delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

553

if (si->fb_area >= 0) delete_area(si->fb_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

554

si->regs_area = si->fb_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

560

delete_area(si->dma_buffer_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

561

si->dma_buffer_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

562

delete_area(si->pseudo_dma_area);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

563

si->pseudo_dma_area = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

566

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

668

di->si = NULL;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

697

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

700

if (si->vblank >= 0) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

702

if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

703

release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

715

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

716

int32 *flags = (int32*)&(si->flags);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

731

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

744

shared_info *si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

770

di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS,

src/add-ons/kernel/drivers/graphics/matrox/driver.c

780

si = di->si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

783

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

784

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

785

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

786

si->bus = di->pcii.bus;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

787

si->device = di->pcii.device;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

788

si->function = di->pcii.function;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

791

si->accelerant_in_use = false;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

804

si->ps.int_assigned = false;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

807

si->vblank = create_sem(0, di->name);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

808

if (si->vblank < 0) goto mark_as_open;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

814

set_sem_owner(si->vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

822

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

823

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

833

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

834

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

839

si->ps.int_assigned = true;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

857

di->si = NULL;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

904

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

917

if (si->ps.int_assigned)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

923

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

924

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

933

di->si = NULL;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

323

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

351

si->use_clone_bugfix = 1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

355

si->use_clone_bugfix = 0;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

366

si->regs_in_fb = true;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

370

si->regs_in_fb = false;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

377

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

382

B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

384

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

387

if (si->regs_area < 0) return si->regs_area;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

394

si->regs2_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

399

B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

401

si->clone_bugfix_regs2 = (uint32 *) di->regs2;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

404

if (si->regs2_area < 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

406

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

407

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

409

return si->regs2_area;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

462

if (si->regs_area >= 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

464

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

465

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

467

if (si->regs2_area >= 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

469

delete_area(si->regs2_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

470

si->regs2_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

479

memcpy (si->rom_mirror, rom_temp, 65536);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

493

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

499

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

502

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

503

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

509

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

513

if (si->fb_area < 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

515

if (si->regs_area >= 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

517

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

518

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

520

if (si->regs2_area >= 0)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

522

delete_area(si->regs2_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

523

si->regs2_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

525

return si->fb_area;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

533

di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x100000);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

534

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

539

di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x200000);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

540

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

545

si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer];

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

548

si->settings = current_settings;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

551

return si->fb_area;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

555

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

564

if (si->regs2_area >= 0) delete_area(si->regs2_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

565

if (si->regs_area >= 0) delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

566

if (si->fb_area >= 0) delete_area(si->fb_area);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

567

si->regs2_area = si->regs_area = si->fb_area = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

568

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

60

shared_info *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

601

di->si = NULL;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

625

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, vuint32 *regs2, shared_info *si) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

628

if (si->vblank >= 0) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

630

if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

631

release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

643

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

644

int32 *flags = (int32*)&(si->flags);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

660

handled = thread_interrupt_work(flags, regs, regs2, si);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

673

shared_info *si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

699

di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

708

si = di->si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

711

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

712

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

713

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

716

si->accelerant_in_use = false;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

729

si->ps.int_assigned = false;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

732

si->vblank = create_sem(0, di->name);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

733

if (si->vblank < 0) goto mark_as_open;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

739

set_sem_owner(si->vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

747

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

748

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

758

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

759

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

764

si->ps.int_assigned = true;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

782

di->si = NULL;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

829

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

843

if (si->ps.int_assigned)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

849

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

850

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

859

di->si = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1004

switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1011

if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1013

si->ps.memory_size -= (64 * 1024);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1020

if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1022

si->ps.memory_size -= (64 * 1024);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1036

si->ps.int_assigned = false;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1039

si->vblank = create_sem(0, di->name);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1040

if (si->vblank < 0) goto mark_as_open;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1046

set_sem_owner(si->vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1054

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1055

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1065

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1066

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1071

si->ps.int_assigned = true;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1088

delete_area(si->dma_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1089

si->dma_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1090

si->dma_buffer = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1094

delete_area(si->unaligned_dma_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1095

si->unaligned_dma_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1096

si->dma_buffer_pci = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1102

di->si = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1143

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1159

if (si->ps.int_assigned) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1165

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1166

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1173

delete_area(si->dma_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1174

si->dma_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1175

si->dma_buffer = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1178

delete_area(si->unaligned_dma_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1179

si->unaligned_dma_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1180

si->dma_buffer_pci = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1185

di->si = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

51

shared_info *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

527

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

556

si->use_clone_bugfix = 1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

560

si->use_clone_bugfix = 0;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

576

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

584

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

587

if (si->regs_area < 0) return si->regs_area;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

647

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

648

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

658

memcpy(si->rom_mirror, rom_temp, 65536);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

685

si->fb_area = map_physical_memory(buffer,

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

691

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

694

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

695

si->fb_area = map_physical_memory(buffer,

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

701

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

705

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

706

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

707

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

708

return si->fb_area;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

713

si->framebuffer_pci = (void*)(uintptr_t)physicalAddress;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

717

si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer];

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

720

si->settings = sSettings;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

722

if (si->fb_area >= 0) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

729

return si->fb_area;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

736

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

746

if (si->regs_area >= 0)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

747

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

748

if (si->fb_area >= 0)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

749

delete_area(si->fb_area);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

750

si->regs_area = si->fb_area = -1;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

751

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

796

di->si = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

822

thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

826

if (si->vblank >= 0) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

828

if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

829

release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

842

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

843

int32 *flags = (int32*)&(si->flags);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

854

if (si->ps.secondary_head) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

862

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

869

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

889

shared_info *si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

921

di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS,

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

931

si = di->si;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

938

si->unaligned_dma_area =

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

948

if (si->unaligned_dma_area < 0)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

951

result = si->unaligned_dma_area;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

958

si->dma_buffer_pci

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

962

si->dma_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

963

"NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size,

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

965

B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

967

if (si->dma_area < 0) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

968

si->dma_area = map_physical_memory("NV aligned DMA cmd buffer",

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

969

(addr_t)si->dma_buffer_pci, net_buf_size,

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

971

B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

974

if (si->dma_area < 0)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

977

result = si->dma_area;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

982

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

983

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

984

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

985

si->bus = di->pcii.bus;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

986

si->device = di->pcii.device;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

987

si->function = di->pcii.function;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

990

si->accelerant_in_use = false;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

993

si->ps.secondary_head = false;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

102

di->memmgr[ mem_type == mt_nonlocal ? di->si->nonlocal_type : mem_type], \

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

122

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

134

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

152

LOG( di->si->log, _Radeon_WaitForIdle );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

175

LOG( di->si->log, _Radeon_WaitForFifo );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

199

LOG( di->si->log, _Radeon_FlushPixelCache );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

209

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

270

if( si->cp.feedback.mem_handle != 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

271

*(uint32 *)MEM2CPU( si->cp.feedback.mem_type, si->cp.feedback.head_mem_offset) =

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

274

si->cp.ring.tail = cur_read_ptr;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

281

++si->engine.count;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

324

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

325

CP_info *cp = &si->cp;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

387

FREE_MEM( mt_nonlocal, di->si->cp.ring.mem_handle );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

392

CP_info *cp = &di->si->cp;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

439

FREE_MEM( mt_PCI, di->si->cp.feedback.mem_handle );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

444

CP_info *cp = &di->si->cp;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

484

FREE_MEM( mt_nonlocal, di->si->cp.buffers.mem_handle );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

498

memset( &di->si->cp, 0, sizeof( di->si->cp ));

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

500

if( (res = INIT_BEN( di->si->cp.lock, "Radeon CP" )) < 0 )

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

510

set_sem_owner( di->si->cp.lock.sem, thinfo.team );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

574

DELETE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

599

DELETE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

608

CP_info *cp = &di->si->cp;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

62

#define MEM2GC( mem ) ((mem).offset + si->memory[(mem).memory_type].virtual_addr_start)

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

83

mem_type = di->si->nonlocal_type; \

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

89

((uint8 *)(memory_type == mt_local ? di->si->local_mem : \

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

96

(di->si->memory[(memory_type)].virtual_addr_start + (offset))

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

170

OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

66

src += di->si->memory[mt_local].virtual_addr_start;

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

68

cur_desc = (DMA_descriptor *)(di->si->local_mem + di->dma_desc_offset);

src/add-ons/kernel/drivers/graphics/radeon/bios.c

1080

di->si = &dummy_si;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

1124

di->si = NULL;

src/add-ons/kernel/drivers/graphics/radeon/detect.c

684

di->si = NULL;

src/add-ons/kernel/drivers/graphics/radeon/driver.c

344

memory_type = am->memory_type == mt_nonlocal ? di->si->nonlocal_type : am->memory_type;

src/add-ons/kernel/drivers/graphics/radeon/driver.c

359

memory_type = fm->memory_type == mt_nonlocal ? di->si->nonlocal_type : fm->memory_type;

src/add-ons/kernel/drivers/graphics/radeon/driver.c

390

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/driver.c

392

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/driver.c

494

*(uint32 *)buf = log_getsize( di->si->log );

src/add-ons/kernel/drivers/graphics/radeon/driver.c

499

log_getcopy( di->si->log, buf, ((uint32 *)buf)[0] );

src/add-ons/kernel/drivers/graphics/radeon/init.c

101

if( si->ROM_area < 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/init.c

102

result = si->ROM_area;

src/add-ons/kernel/drivers/graphics/radeon/init.c

132

si->memory[mt_local].area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/radeon/init.c

138

(void **)&(si->local_mem));

src/add-ons/kernel/drivers/graphics/radeon/init.c

140

if( si->memory[mt_local].area < 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/init.c

142

si->memory[mt_local].area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/radeon/init.c

148

(void **)&(si->local_mem));

src/add-ons/kernel/drivers/graphics/radeon/init.c

151

SHOW_FLOW( 3, "mapped frame buffer @%p", si->local_mem );

src/add-ons/kernel/drivers/graphics/radeon/init.c

153

if( si->memory[mt_local].area < 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/init.c

154

result = si->memory[mt_local].area;

src/add-ons/kernel/drivers/graphics/radeon/init.c

160

si->framebuffer_pci = (phys_addr_t)di->pcii.u.h0.base_registers_pci[fb];

src/add-ons/kernel/drivers/graphics/radeon/init.c

165

delete_area( si->ROM_area );

src/add-ons/kernel/drivers/graphics/radeon/init.c

167

delete_area( si->regs_area );

src/add-ons/kernel/drivers/graphics/radeon/init.c

175

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/init.c

187

if( si->regs_area > 0 )

src/add-ons/kernel/drivers/graphics/radeon/init.c

188

delete_area( si->regs_area );

src/add-ons/kernel/drivers/graphics/radeon/init.c

190

if( si->ROM_area > 0 )

src/add-ons/kernel/drivers/graphics/radeon/init.c

191

delete_area( si->ROM_area );

src/add-ons/kernel/drivers/graphics/radeon/init.c

193

if( si->memory[mt_local].area > 0 )

src/add-ons/kernel/drivers/graphics/radeon/init.c

194

delete_area( si->memory[mt_local].area );

src/add-ons/kernel/drivers/graphics/radeon/init.c

196

si->regs_area = si->ROM_area = si->memory[mt_local].area = 0;

src/add-ons/kernel/drivers/graphics/radeon/init.c

205

shared_info *si;

src/add-ons/kernel/drivers/graphics/radeon/init.c

216

(void **)&(di->si),

src/add-ons/kernel/drivers/graphics/radeon/init.c

226

memset( di->si, 0, sizeof( *di->si ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

228

si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/init.c

230

si->settings = di->settings = current_settings;

src/add-ons/kernel/drivers/graphics/radeon/init.c

239

si->log = log_init( 1000000 );

src/add-ons/kernel/drivers/graphics/radeon/init.c

244

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/radeon/init.c

245

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/radeon/init.c

246

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/radeon/init.c

248

si->asic = di->asic;

src/add-ons/kernel/drivers/graphics/radeon/init.c

249

si->is_mobility = di->is_mobility;

src/add-ons/kernel/drivers/graphics/radeon/init.c

250

si->tv_chip = di->tv_chip;

src/add-ons/kernel/drivers/graphics/radeon/init.c

251

si->new_pll = di->new_pll;

src/add-ons/kernel/drivers/graphics/radeon/init.c

252

si->is_igp = di->is_igp;

src/add-ons/kernel/drivers/graphics/radeon/init.c

253

si->has_no_i2c = di->has_no_i2c;

src/add-ons/kernel/drivers/graphics/radeon/init.c

254

si->is_atombios = di->is_atombios;

src/add-ons/kernel/drivers/graphics/radeon/init.c

255

si->is_mobility = di->is_mobility;

src/add-ons/kernel/drivers/graphics/radeon/init.c

256

si->panel_pwr_delay = di->si->panel_pwr_delay;

src/add-ons/kernel/drivers/graphics/radeon/init.c

257

si->acc_dma = di->acc_dma;

src/add-ons/kernel/drivers/graphics/radeon/init.c

259

memcpy(&si->routing, &di->routing, sizeof(disp_entity));

src/add-ons/kernel/drivers/graphics/radeon/init.c

263

si->theatre_channel = -1;

src/add-ons/kernel/drivers/graphics/radeon/init.c

265

si->crtc[0].crtc_idx = 0;

src/add-ons/kernel/drivers/graphics/radeon/init.c

266

si->crtc[0].flatpanel_port = 0;

src/add-ons/kernel/drivers/graphics/radeon/init.c

267

si->crtc[1].crtc_idx = 1;

src/add-ons/kernel/drivers/graphics/radeon/init.c

268

si->crtc[1].flatpanel_port = 1;

src/add-ons/kernel/drivers/graphics/radeon/init.c

269

si->num_crtc = di->num_crtc;

src/add-ons/kernel/drivers/graphics/radeon/init.c

272

si->flatpanels[0] = di->fp_info;

src/add-ons/kernel/drivers/graphics/radeon/init.c

274

si->pll = di->pll;

src/add-ons/kernel/drivers/graphics/radeon/init.c

295

di->vc->assigned_crtc[1] = si->num_crtc > 1;

src/add-ons/kernel/drivers/graphics/radeon/init.c

315

memcpy(&si->tmds_pll, &di->tmds_pll, sizeof(di->tmds_pll));

src/add-ons/kernel/drivers/graphics/radeon/init.c

316

si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/init.c

317

si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/init.c

342

si->memory[mt_local].size = di->local_mem_size;

src/add-ons/kernel/drivers/graphics/radeon/init.c

344

si->memory[mt_PCI].area = di->pci_gart.buffer.area;

src/add-ons/kernel/drivers/graphics/radeon/init.c

345

si->memory[mt_PCI].size = di->pci_gart.buffer.size;

src/add-ons/kernel/drivers/graphics/radeon/init.c

348

si->nonlocal_type = mt_PCI;

src/add-ons/kernel/drivers/graphics/radeon/init.c

43

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/init.c

460

log_exit( di->si->log );

src/add-ons/kernel/drivers/graphics/radeon/init.c

51

si->ROM_area = si->regs_area = si->memory[mt_local].area = 0;

src/add-ons/kernel/drivers/graphics/radeon/init.c

72

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/radeon/init.c

81

if( si->regs_area < 0 )

src/add-ons/kernel/drivers/graphics/radeon/init.c

82

return si->regs_area;

src/add-ons/kernel/drivers/graphics/radeon/init.c

94

si->ROM_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/radeon/irq.c

153

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

161

bigtime_t when = si->refresh_period;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

165

if (si->enable_virtual_irq) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

168

when -= si->blank_period - 4;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

204

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

212

si->crtc[0].vblank = create_sem(0, buffer);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

213

if (si->crtc[0].vblank < 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

214

result = si->crtc[0].vblank;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

218

si->crtc[1].vblank = 0;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

224

si->crtc[1].vblank = create_sem(0, buffer);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

225

if (si->crtc[1].vblank < 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

226

result = si->crtc[1].vblank;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

255

set_sem_owner(si->crtc[0].vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

257

set_sem_owner(si->crtc[1].vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

268

si->refresh_period = 16666; /* fake 60Hz to start */

src/add-ons/kernel/drivers/graphics/radeon/irq.c

269

si->blank_period = si->refresh_period / 20;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

277

si->refresh_period, B_ONE_SHOT_RELATIVE_TIMER);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

298

delete_sem(si->crtc[1].vblank);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

300

delete_sem(si->crtc[0].vblank);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

311

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

32

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

328

delete_sem(si->crtc[0].vblank);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

331

delete_sem(si->crtc[1].vblank);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

336

di->cap_sem = si->crtc[1].vblank = si->crtc[0].vblank = 0;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

36

&& si->crtc[0].vblank >= 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

41

if (get_sem_count(si->crtc[0].vblank, &blocked ) == B_OK && blocked < 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

42

release_sem_etc(si->crtc[0].vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

48

&& si->crtc[1].vblank >= 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

53

if (get_sem_count(si->crtc[1].vblank, &blocked) == B_OK && blocked < 0) {

src/add-ons/kernel/drivers/graphics/radeon/irq.c

54

release_sem_etc(si->crtc[1].vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

104

si->memory[mt_local].virtual_addr_start = 0;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

105

si->memory[mt_local].virtual_size =

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

106

si->memory[mt_AGP].virtual_addr_start -

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

107

si->memory[mt_local].virtual_addr_start;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

114

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

120

si->memory[mt_local].virtual_addr_start = (tom & 0xffff) << 16;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

121

si->memory[mt_local].virtual_size =

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

123

si->memory[mt_local].virtual_addr_start;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

127

si->memory[mt_PCI].virtual_addr_start = ((((tom >> 16) + 1) << 16) + 4095) & ~4095;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

128

si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

131

si->memory[mt_AGP].virtual_addr_start =

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

132

(si->memory[mt_PCI].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

133

si->memory[mt_PCI].virtual_size + 0x3fffff) & ~0x3fffff;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

134

si->memory[mt_AGP].virtual_size = 0x400000;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

141

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

150

si->memory[mt_local].virtual_size, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

152

si->memory[mt_PCI].virtual_size, si->memory[mt_PCI].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

154

si->memory[mt_AGP].virtual_size, si->memory[mt_AGP].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

167

OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

168

OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

169

si->memory[mt_PCI].virtual_size/*di->pci_gart.buffer.size*/ - 1 );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

183

((si->memory[mt_local].virtual_addr_start + si->memory[mt_local].virtual_size - 1) & 0xffff0000) |

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

184

(si->memory[mt_local].virtual_addr_start >> 16) );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

188

OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

189

OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

190

OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

41

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

51

si->memory[mt_local].virtual_addr_start = aper0;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

52

si->memory[mt_local].virtual_size = di->local_mem_size;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

59

si->memory[mt_PCI].virtual_addr_start = (getTopOfRam() + 4095) & ~4095;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

60

si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

67

si->memory[mt_AGP].virtual_addr_start =

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

68

(si->memory[mt_PCI].virtual_addr_start + si->memory[mt_PCI].virtual_size

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

70

si->memory[mt_AGP].virtual_size = 0x400000;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

79

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

88

si->memory[mt_PCI].virtual_size = ATI_MAX_PCIGART_PAGES * ATI_PCIGART_PAGE_SIZE;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

89

si->memory[mt_PCI].virtual_addr_start = 0 - si->memory[mt_PCI].virtual_size;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

96

si->memory[mt_AGP].virtual_size = 0x400000;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

97

si->memory[mt_AGP].virtual_addr_start =

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

98

si->memory[mt_PCI].virtual_addr_start -

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

99

si->memory[mt_AGP].virtual_size;

src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h

99

shared_info *si;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

177

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

182

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

217

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

222

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

281

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

287

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

300

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

340

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

422

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

439

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

444

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

85

ACQUIRE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

90

RELEASE_BEN( di->si->cp.lock );

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

183

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

218

si.videoMemPCI = (void *)(pciInfo.u.h0.base_registers_pci[0]);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

227

si.videoMemPCI = (void *)(pciInfo.u.h0.base_registers_pci[1]);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

237

si.videoMemPCI = (void *)(pciInfo.u.h0.base_registers_pci[0]);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

246

si.regsArea = map_physical_memory(areaName, regsBase, regAreaSize,

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

251

if (si.regsArea < 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

252

return si.regsArea; // return error code

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

260

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

266

&(si.videoMemAddr));

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

268

if (si.videoMemArea < 0) {

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

270

si.videoMemArea = map_physical_memory(

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

276

&(si.videoMemAddr));

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

279

TRACE("Video memory, area: %" B_PRId32 ", addr: 0x%" B_PRIXADDR "\n", si.videoMemArea,

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

280

(addr_t)(si.videoMemAddr));

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

283

if (si.videoMemArea < 0) {

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

284

delete_area(si.regsArea);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

285

si.regsArea = -1;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

288

TRACE("leave MapDevice(); result: %" B_PRId32 "\n", si.videoMemArea);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

289

return si.videoMemArea;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

296

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

300

if (si.regsArea >= 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

301

delete_area(si.regsArea);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

302

if (si.videoMemArea >= 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

303

delete_area(si.videoMemArea);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

305

si.regsArea = si.videoMemArea = -1;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

306

si.videoMemAddr = NULL;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

350

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

355

si.bInterruptAssigned = false; // indicate interrupt not assigned yet

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

358

si.vertBlankSem = create_sem(0, di.name);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

359

if (si.vertBlankSem < 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

370

status = set_sem_owner(si.vertBlankSem, threadInfo.team);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

382

si.bInterruptAssigned = true; // we can use interrupt related functions

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

387

delete_sem(si.vertBlankSem);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

388

si.vertBlankSem = -1;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

419

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

421

si.vendorID = pciInfo.vendor_id;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

422

si.deviceID = pciInfo.device_id;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

423

si.revision = pciInfo.revision;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

424

si.chipType = di.pChipInfo->chipType;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

425

strcpy(si.chipName, di.pChipInfo->chipName);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

431

if (si.chipType == S3_TRIO64 && si.revision & 0x40) {

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

432

si.chipType = S3_TRIO64_VP;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

433

strcpy(si.chipName, "Trio64 V+");

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

446

TRACE("Interrupt assigned: %s\n", si.bInterruptAssigned ? "yes" : "no");

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

774

SharedInfo& si = *(di.sharedInfo);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

786

if (si.bInterruptAssigned) {

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

791

if (si.vertBlankSem >= 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

792

delete_sem(si.vertBlankSem);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

793

si.vertBlankSem = -1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

331

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

363

si->use_clone_bugfix = 1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

367

si->use_clone_bugfix = 0;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

376

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

382

B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

384

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

387

if (si->regs_area < 0) return si->regs_area;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

445

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

446

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

454

memcpy (si->rom_mirror, rom_temp, 65536);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

468

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

475

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

478

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

479

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

486

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

490

if (si->fb_area < 0)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

492

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

493

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

494

return si->fb_area;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

498

si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer];

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

501

si->settings = current_settings;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

504

return si->fb_area;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

508

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

517

if (si->regs_area >= 0) delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

518

if (si->fb_area >= 0) delete_area(si->fb_area);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

519

si->regs_area = si->fb_area = -1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

520

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

553

di->si = NULL;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

57

shared_info *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

577

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

580

if (si->vblank >= 0) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

582

if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

583

release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

595

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

596

int32 *flags = &(si->flags);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

611

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

624

shared_info *si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

651

di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

660

si = di->si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

663

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

664

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

665

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

666

si->bus = di->pcii.bus;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

667

si->device = di->pcii.device;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

668

si->function = di->pcii.function;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

672

switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

676

si->ps.memory_size = 1024 * 1024 *

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

679

si->ps.memory_size -= (64 * 1024);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

683

si->ps.memory_size = 1024 * 1024 *

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

686

si->ps.memory_size -= (64 * 1024);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

700

si->vblank = create_sem(0, di->name);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

701

if (si->vblank < 0) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

702

result = si->vblank;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

710

set_sem_owner(si->vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

748

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

757

di->si = NULL;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

803

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

820

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

821

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

829

di->si = NULL;

src/add-ons/kernel/drivers/graphics/via/driver.c

340

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/via/driver.c

372

si->use_clone_bugfix = 1;

src/add-ons/kernel/drivers/graphics/via/driver.c

376

si->use_clone_bugfix = 0;

src/add-ons/kernel/drivers/graphics/via/driver.c

385

si->regs_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/via/driver.c

391

B_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),

src/add-ons/kernel/drivers/graphics/via/driver.c

393

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

396

if (si->regs_area < 0) return si->regs_area;

src/add-ons/kernel/drivers/graphics/via/driver.c

454

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/via/driver.c

455

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/via/driver.c

463

memcpy (si->rom_mirror, rom_temp, 65536);

src/add-ons/kernel/drivers/graphics/via/driver.c

477

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/via/driver.c

484

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/via/driver.c

487

if (si->fb_area < 0) {

src/add-ons/kernel/drivers/graphics/via/driver.c

488

si->fb_area = map_physical_memory(

src/add-ons/kernel/drivers/graphics/via/driver.c

495

&(si->framebuffer));

src/add-ons/kernel/drivers/graphics/via/driver.c

499

if (si->fb_area < 0)

src/add-ons/kernel/drivers/graphics/via/driver.c

501

delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/via/driver.c

502

si->regs_area = -1;

src/add-ons/kernel/drivers/graphics/via/driver.c

503

return si->fb_area;

src/add-ons/kernel/drivers/graphics/via/driver.c

507

si->framebuffer_pci = (void *)(addr_t) di->pcii.u.h0.base_registers_pci[frame_buffer];

src/add-ons/kernel/drivers/graphics/via/driver.c

510

si->settings = current_settings;

src/add-ons/kernel/drivers/graphics/via/driver.c

513

return si->fb_area;

src/add-ons/kernel/drivers/graphics/via/driver.c

517

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/via/driver.c

526

if (si->regs_area >= 0) delete_area(si->regs_area);

src/add-ons/kernel/drivers/graphics/via/driver.c

527

if (si->fb_area >= 0) delete_area(si->fb_area);

src/add-ons/kernel/drivers/graphics/via/driver.c

528

si->regs_area = si->fb_area = -1;

src/add-ons/kernel/drivers/graphics/via/driver.c

529

si->framebuffer = NULL;

src/add-ons/kernel/drivers/graphics/via/driver.c

562

di->si = NULL;

src/add-ons/kernel/drivers/graphics/via/driver.c

57

shared_info *si; /* a pointer to the shared area, for convenience */

src/add-ons/kernel/drivers/graphics/via/driver.c

586

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/via/driver.c

589

if (si->vblank >= 0) {

src/add-ons/kernel/drivers/graphics/via/driver.c

591

if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {

src/add-ons/kernel/drivers/graphics/via/driver.c

592

release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);

src/add-ons/kernel/drivers/graphics/via/driver.c

604

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/via/driver.c

605

int32 *flags = (int32*)&(si->flags);

src/add-ons/kernel/drivers/graphics/via/driver.c

620

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/via/driver.c

633

shared_info *si;

src/add-ons/kernel/drivers/graphics/via/driver.c

660

di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,

src/add-ons/kernel/drivers/graphics/via/driver.c

669

si = di->si;

src/add-ons/kernel/drivers/graphics/via/driver.c

672

si->vendor_id = di->pcii.vendor_id;

src/add-ons/kernel/drivers/graphics/via/driver.c

673

si->device_id = di->pcii.device_id;

src/add-ons/kernel/drivers/graphics/via/driver.c

674

si->revision = di->pcii.revision;

src/add-ons/kernel/drivers/graphics/via/driver.c

675

si->bus = di->pcii.bus;

src/add-ons/kernel/drivers/graphics/via/driver.c

676

si->device = di->pcii.device;

src/add-ons/kernel/drivers/graphics/via/driver.c

677

si->function = di->pcii.function;

src/add-ons/kernel/drivers/graphics/via/driver.c

680

si->ps.chip_rev = ((*pci_bus->read_pci_config)(0, 0, 0, 0xf6, 1));

src/add-ons/kernel/drivers/graphics/via/driver.c

688

si->vblank = create_sem(0, di->name);

src/add-ons/kernel/drivers/graphics/via/driver.c

689

if (si->vblank < 0) {

src/add-ons/kernel/drivers/graphics/via/driver.c

690

result = si->vblank;

src/add-ons/kernel/drivers/graphics/via/driver.c

698

set_sem_owner(si->vblank, thinfo.team);

src/add-ons/kernel/drivers/graphics/via/driver.c

736

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/via/driver.c

745

di->si = NULL;

src/add-ons/kernel/drivers/graphics/via/driver.c

791

shared_info *si = di->si;

src/add-ons/kernel/drivers/graphics/via/driver.c

808

delete_sem(si->vblank);

src/add-ons/kernel/drivers/graphics/via/driver.c

809

si->vblank = -1;

src/add-ons/kernel/drivers/graphics/via/driver.c

817

di->si = NULL;

src/add-ons/kernel/drivers/network/ether/atheros81xx/dev/ale/if_ale.c

1604

int error, i, nsegs, prod, si;

src/add-ons/kernel/drivers/network/ether/atheros81xx/dev/ale/if_ale.c

1724

si = prod = sc->ale_cdata.ale_tx_prod;

src/add-ons/kernel/drivers/network/ether/atheros81xx/dev/ale/if_ale.c

1844

desc = &sc->ale_cdata.ale_tx_ring[si];

src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/if_age.c

1495

int error, i, nsegs, prod, si;

src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/if_age.c

1590

si = prod = sc->age_cdata.age_tx_prod;

src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/if_age.c

1700

desc = &sc->age_rdata.age_tx_ring[si];

src/add-ons/kernel/drivers/network/ether/broadcom440x/dev/bfe/if_bfe.c

1511

uint32_t cur, si;

src/add-ons/kernel/drivers/network/ether/broadcom440x/dev/bfe/if_bfe.c

1518

si = cur = sc->bfe_tx_prod;

src/add-ons/kernel/drivers/network/ether/broadcom440x/dev/bfe/if_bfe.c

1575

d = &sc->bfe_tx_list[si];

src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/if_msk.c

2626

uint32_t control, csum, prod, si;

src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/if_msk.c

2836

si = prod;

src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/if_msk.c

2879

tx_le = &sc_if->msk_rdata.msk_tx_ring[si];

src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/if_nfe.c

2378

int error, i, nsegs, prod, si;

src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/if_nfe.c

2383

prod = si = sc->txq.cur;

src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/if_nfe.c

2467

desc64 = &sc->txq.desc64[si];

src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/if_nfe.c

2490

desc32 = &sc->txq.desc32[si];

src/add-ons/kernel/drivers/network/ether/nforce/dev/nfe/if_nfe.c

2509

sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map;

src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/if_re.c

2744

int i, error, ei, si;

src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/if_re.c

2887

si = prod;

src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/if_re.c

2909

desc = &sc->rl_ldata.rl_tx_list[si];

src/add-ons/kernel/drivers/network/ether/sis19x/dev/sge/if_sge.c

1401

int error, i, nsegs, prod, si;

src/add-ons/kernel/drivers/network/ether/sis19x/dev/sge/if_sge.c

1405

si = prod = sc->sge_cdata.sge_tx_prod;

src/add-ons/kernel/drivers/network/ether/sis19x/dev/sge/if_sge.c

1532

desc = &sc->sge_ldata.sge_tx_ring[si];

src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/if_sk.c

2326

u_int32_t cflags, frag, si, sk_ctl;

src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/if_sk.c

2368

si = frag = sc_if->sk_cdata.sk_tx_prod;

src/add-ons/kernel/drivers/network/ether/syskonnect/dev/sk/if_sk.c

2392

f = &sc_if->sk_rdata.sk_tx_ring[si];

src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/if_vr.c

1798

int error, i, nsegs, prod, si;

src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/if_vr.c

1913

si = prod;

src/add-ons/kernel/drivers/network/ether/via_rhine/dev/vr/if_vr.c

1942

desc = &sc->vr_rdata.vr_tx_ring[si];

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1480

STANDARD_INFORMATION *si = NULL;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1509

si = ntfs_calloc(si_len);

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1510

if (!si) {

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1514

si->creation_time = ni->creation_time;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1515

si->last_data_change_time = ni->last_data_change_time;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1516

si->last_mft_change_time = ni->last_mft_change_time;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1517

si->last_access_time = ni->last_access_time;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1520

ni->owner_id = si->owner_id = const_cpu_to_le32(0);

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1521

ni->security_id = si->security_id = securid;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1522

ni->quota_charged = si->quota_charged = const_cpu_to_le64(0);

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1523

ni->usn = si->usn = const_cpu_to_le64(0);

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1530

si->file_attributes

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1536

si->file_attributes = FILE_ATTR_SYSTEM;

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1560

(u8*)si, si_len)) {

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1772

free(si);

src/add-ons/kernel/file_systems/ntfs/libntfs/dir.c

1801

free(si);

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

509

int di, si; /* Current index into @[ds]rl. */

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

548

si = di = 0;

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

551

while (srl[si].length && srl[si].lcn < (LCN)LCN_HOLE)

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

552

si++;

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

555

if (!srl[si].length) {

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

562

sstart = si;

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

576

if ((drl[di].vcn == srl[si].vcn) && (drl[di].lcn >= 0) &&

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

577

(srl[si].lcn >= 0)) {

src/add-ons/kernel/file_systems/ntfs/libntfs/runlist.c

584

for (send = si; srl[send].length; send++)

src/add-ons/kernel/file_systems/ntfs/libntfs/volume.c

226

STANDARD_INFORMATION *si;

src/add-ons/kernel/file_systems/ntfs/libntfs/volume.c

230

si = (STANDARD_INFORMATION*)ntfs_attr_readall(ni,

src/add-ons/kernel/file_systems/ntfs/libntfs/volume.c

232

if (si) {

src/add-ons/kernel/file_systems/ntfs/libntfs/volume.c

234

ni->flags = si->file_attributes;

src/add-ons/kernel/file_systems/ntfs/libntfs/volume.c

235

free(si);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1619

STANDARD_INFORMATION si;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1624

si.creation_time = mkntfs_time();

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1625

si.last_data_change_time = si.creation_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1626

si.last_mft_change_time = si.creation_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1627

si.last_access_time = si.creation_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1628

si.file_attributes = flags; /* already LE */

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1629

si.maximum_versions = cpu_to_le32(0);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1630

si.version_number = cpu_to_le32(0);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1631

si.class_id = cpu_to_le32(0);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1632

si.security_id = security_id;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1633

if (si.security_id != const_cpu_to_le32(0))

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1636

si.owner_id = cpu_to_le32(0);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1637

si.quota_charged = cpu_to_le64(0ULL);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1639

si.usn = cpu_to_le64(0ULL);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1643

0, (u8*)&si, sd_size);

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1680

STANDARD_INFORMATION *si;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1688

si = (STANDARD_INFORMATION*)((char*)ctx->attr +

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1690

info_time = si->creation_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1712

STANDARD_INFORMATION *si;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1731

si = (STANDARD_INFORMATION*)((char*)ctx->attr +

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1742

fn->creation_time = si->creation_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1743

fn->last_data_change_time = si->last_data_change_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1744

fn->last_mft_change_time = si->last_mft_change_time;

src/add-ons/kernel/file_systems/ntfs/utils/mkntfs.c

1745

fn->last_access_time = si->last_access_time;

src/add-ons/media/media-add-ons/esound_sink/ESDEndpoint.cpp

367

} si;

src/add-ons/media/media-add-ons/esound_sink/ESDEndpoint.cpp

369

err = SendCommand(ESD_PROTO_SERVER_INFO, (const uint8 *)&si, 0, (uint8 *)&si, sizeof(si));

src/add-ons/media/media-add-ons/esound_sink/ESDEndpoint.cpp

372

PRINT(("err 0x%08lx, version: %lu, rate: %lu, fmt: %lu\n", err, si.ver, si.rate, si.fmt));

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

162

if (si->asic >= rt_r200) {

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

200

if (si->asic >= rt_r200) {

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

29

si = fRadeon.GetSharedInfo();

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

31

if ( si->asic == rt_rv200 ) {

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

78

if ( si == NULL )

src/add-ons/media/media-add-ons/radeon/I2CPort.cpp

81

if ( si->has_no_i2c ) {

src/add-ons/media/media-add-ons/radeon/I2CPort.h

60

shared_info* si;

src/add-ons/screen_savers/flurry/Smoke.cpp

253

int si = 0;

src/add-ons/screen_savers/flurry/Smoke.cpp

341

si++;

src/add-ons/screen_savers/flurry/Smoke.cpp

393

glDrawArrays(GL_QUADS, 0, si * 4);

src/bin/setmime.cpp

1125

for (int32 si = 0; si < superCount; si++) {

src/bin/setmime.cpp

1127

if (superTypes.FindString("super_types", si, &superName) != B_OK)

src/bin/setmime.cpp

1128

throw Error("name for supertype #%d not found", si);

src/libs/compat/freebsd_iflib/iflib.c

1384

int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);

src/libs/compat/freebsd_iflib/iflib.c

1386

NMB(na, slot + si));

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

351

struct ieee80211req_sta_info *si;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

381

struct ieee80211req_sta_info *si;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

393

si = req->si;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

394

si->isi_len = len;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

395

si->isi_ie_off = sizeof(struct ieee80211req_sta_info);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

396

si->isi_ie_len = ielen;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

397

si->isi_freq = ni->ni_chan->ic_freq;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

398

si->isi_flags = ni->ni_chan->ic_flags;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

399

si->isi_state = ni->ni_flags;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

400

si->isi_authmode = ni->ni_authmode;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

401

vap->iv_ic->ic_node_getsignal(ni, &si->isi_rssi, &si->isi_noise);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

402

vap->iv_ic->ic_node_getmimoinfo(ni, &si->isi_mimo);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

403

si->isi_capinfo = ni->ni_capinfo;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

404

si->isi_erp = ni->ni_erp;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

405

IEEE80211_ADDR_COPY(si->isi_macaddr, ni->ni_macaddr);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

406

si->isi_nrates = ni->ni_rates.rs_nrates;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

407

if (si->isi_nrates > 15)

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

408

si->isi_nrates = 15;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

409

memcpy(si->isi_rates, ni->ni_rates.rs_rates, si->isi_nrates);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

419

si->isi_txrate = ieee80211_node_get_txrate_dot11rate(ni);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

421

si->isi_txmbps = ieee80211_node_get_txrate_kbit(ni) / 500;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

422

si->isi_associd = ni->ni_associd;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

423

si->isi_txpower = ni->ni_txpower;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

424

si->isi_vlan = ni->ni_vlan;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

426

memcpy(si->isi_txseqs, ni->ni_txseqs, sizeof(ni->ni_txseqs));

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

427

memcpy(si->isi_rxseqs, ni->ni_rxseqs, sizeof(ni->ni_rxseqs));

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

429

si->isi_txseqs[0] = ni->ni_txseqs[IEEE80211_NONQOS_TID];

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

430

si->isi_rxseqs[0] = ni->ni_rxseqs[IEEE80211_NONQOS_TID];

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

434

si->isi_inact = vap->iv_inact_run;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

438

si->isi_inact = vap->iv_inact_auth;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

440

si->isi_inact = vap->iv_inact_init;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

441

si->isi_inact = (si->isi_inact - ni->ni_inact) * IEEE80211_INACT_WAIT;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

442

si->isi_localid = ni->ni_mllid;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

443

si->isi_peerid = ni->ni_mlpid;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

444

si->isi_peerstate = ni->ni_mlstate;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

447

cp = ((uint8_t *)si) + si->isi_ie_off;

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

451

req->si = (struct ieee80211req_sta_info *)(((uint8_t *)si) + len);

src/libs/compat/freebsd_wlan/net80211/ieee80211_ioctl.c

483

req.si = p;

src/libs/libsolv/solv/bitmap.c

66

unsigned char *ti, *si, *end;

src/libs/libsolv/solv/bitmap.c

68

si = s->map;

src/libs/libsolv/solv/bitmap.c

71

*ti++ &= *si++;

src/libs/libsolv/solv/bitmap.c

78

unsigned char *ti, *si, *end;

src/libs/libsolv/solv/bitmap.c

82

si = s->map;

src/libs/libsolv/solv/bitmap.c

85

*ti++ |= *si++;

src/libs/libsolv/solv/bitmap.c

92

unsigned char *ti, *si, *end;

src/libs/libsolv/solv/bitmap.c

94

si = s->map;

src/libs/libsolv/solv/bitmap.c

97

*ti++ &= ~*si++;

src/libs/libsolv/solv/solvable.c

630

Solvable *si;

src/libs/libsolv/solv/solvable.c

633

si = pool->solvables + p;

src/libs/libsolv/solv/solvable.c

634

if (!pool_match_nevr(pool, si, con))

src/libs/libsolv/solv/solvable.c

647

if (si->vendor == s2->vendor)

src/libs/libsolv/solv/solvable.c

649

if (!pool_illegal_vendorchange(pool, si, s2))

src/libs/libsolv/solv/solver.c

2749

Solvable *si = pool->solvables + pi;

src/libs/libsolv/solv/solver.c

2750

if (si->repo != installed || si->name != s->name)

src/libs/libsolv/solv/solver.c

2762

if (s->evr == si->evr && solvable_identical(s, si))

src/libs/libsolv/solv/solver.c

2772

Solvable *si = pool->solvables + pi;

src/libs/libsolv/solv/solver.c

2773

if (si->repo != installed)

src/libs/libsolv/solv/solver.c

2775

if (si->name == s->name)

src/libs/libsolv/solv/solver.c

2777

if (!pool->obsoleteusesprovides && !pool_match_nevr(pool, si, obs))

src/libs/libsolv/solv/solver.c

2779

if (pool->obsoleteusescolors && !pool_colormatch(pool, s, si))

src/libs/libsolv/solv/solver.c

4208

Solvable *si = pool->solvables + pi;

src/libs/libsolv/solv/solver.c

4209

if (si->repo != pool->installed || si->name != s->name)

src/libs/libsolv/solv/solver.c

4220

Solvable *si = pool->solvables + pi;

src/libs/libsolv/solv/solver.c

4221

if (si->repo != pool->installed)

src/libs/libsolv/solv/solver.c

4223

if (!pool->obsoleteusesprovides && !pool_match_nevr(pool, si, obs))

src/libs/libsolv/solv/solver.c

4225

if (pool->obsoleteusescolors && !pool_colormatch(pool, s, si))

src/system/kernel/arch/x86/32/descriptors.cpp

173

frame->si = tss->esi;

src/system/kernel/arch/x86/32/thread.cpp

318

signalFrameData->context.uc_mcontext.esi = frame->si;

src/system/kernel/arch/x86/32/thread.cpp

398

frame->si = signalFrameData->context.uc_mcontext.esi;

src/system/kernel/arch/x86/64/thread.cpp

302

frame.si = (uint64)args2;

src/system/kernel/arch/x86/64/thread.cpp

359

signalFrameData->context.uc_mcontext.rsi = frame->si;

src/system/kernel/arch/x86/64/thread.cpp

439

frame->si = signalFrameData->context.uc_mcontext.rsi;

src/system/kernel/arch/x86/arch_debug.cpp

1300

{ B_UINT64_TYPE, frame->si }, { B_UINT64_TYPE, frame->di },

src/system/kernel/arch/x86/arch_debug.cpp

1326

{ B_UINT32_TYPE, frame->si }, { B_UINT32_TYPE, frame->di },

src/system/kernel/arch/x86/arch_debug.cpp

432

frame->si, frame->di);

src/system/kernel/arch/x86/arch_debug.cpp

448

frame->si, frame->di, frame->bp, frame->sp);

src/system/kernel/arch/x86/arch_debug.cpp

619

CHECK_DEBUG_VARIABLE("rsi", frame->si, true);

src/system/kernel/arch/x86/arch_debug.cpp

635

CHECK_DEBUG_VARIABLE("esi", frame->si, true);

src/system/kernel/arch/x86/arch_user_debugger.cpp

131

frame->si = cpuState->rsi;

src/system/kernel/arch/x86/arch_user_debugger.cpp

155

cpuState->esi = frame->si;

src/system/kernel/arch/x86/arch_user_debugger.cpp

180

frame->si = cpuState->esi;

src/system/kernel/arch/x86/arch_user_debugger.cpp

91

cpuState->rsi = frame->si;

src/system/kernel/arch/x86/asm_offsets.cpp

66

DEFINE_OFFSET_MACRO(IFRAME, iframe, si);

src/system/kernel/lib/strtod.c

1665

ULong si, zs;

src/system/kernel/lib/strtod.c

1689

si = *sx++;

src/system/kernel/lib/strtod.c

1690

ys = (si & 0xffff) * q + carry;

src/system/kernel/lib/strtod.c

1691

zs = (si >> 16) * q + (ys >> 16);

src/system/kernel/lib/strtod.c

1724

si = *sx++;

src/system/kernel/lib/strtod.c

1725

ys = (si & 0xffff) + carry;

src/system/kernel/lib/strtod.c

1726

zs = (si >> 16) + (ys >> 16);

src/system/libroot/posix/stdlib/radixsort.c

122

#define pop(a, n, i) a = (--sp)->sa, n = sp->sn, i = sp->si

src/system/libroot/posix/stdlib/radixsort.c

123

#define push(a, n, i) sp->sa = a, sp->sn = n, (sp++)->si = i

src/system/libroot/posix/stdlib/radixsort.c

59

int sn, si;