headers/os/drivers/bios.h

60

status_t (*interrupt)(bios_state* state, uint8 vector, bios_regs* regs);

headers/os/drivers/bus/FDT.h

26

bool (*get_reg)(struct fdt_device* dev, uint32 ord, uint64* regs, uint64* len);

headers/os/kernel/OS.h

594

} regs;

headers/posix/setjmp.h

17

__jmp_buf regs; /* saved registers, stack & program pointer */

headers/private/graphics/matrox/mga_macros.h

308

#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)]

headers/private/graphics/matrox/mga_macros.h

309

#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]

headers/private/graphics/neomagic/nm_macros.h

302

#define NM_REG8(r_) ((vuint8 *)regs)[(r_)]

headers/private/graphics/neomagic/nm_macros.h

303

#define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]

headers/private/graphics/neomagic/nm_macros.h

304

#define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]

headers/private/graphics/nvidia/nv_macros.h

888

#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]

headers/private/graphics/nvidia/nv_macros.h

889

#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]

headers/private/graphics/nvidia/nv_macros.h

890

#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]

headers/private/graphics/radeon/mmio.h

14

#define INREG8( regs, addr ) (*(regs + (addr)))

headers/private/graphics/radeon/mmio.h

16

#define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 )

headers/private/graphics/radeon/mmio.h

18

#define INREG( regs, addr ) (*((vuint32 *)(regs + (addr))))

headers/private/graphics/radeon/mmio.h

20

#define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 )

headers/private/graphics/radeon/mmio.h

22

#define OUTREGP( regs, addr, val, mask ) \

headers/private/graphics/radeon/mmio.h

24

uint32 tmp = INREG( (regs), (addr) ); \

headers/private/graphics/radeon/mmio.h

27

OUTREG( (regs), (addr), tmp ); \

headers/private/graphics/radeon/pll_access.h

19

void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic );

headers/private/graphics/radeon/pll_access.h

24

void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic );

headers/private/graphics/radeon/pll_access.h

36

uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );

headers/private/graphics/radeon/pll_access.h

39

void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val );

headers/private/graphics/radeon/pll_access.h

42

void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );

headers/private/graphics/skeleton/macros.h

741

#define ENG_REG8(r_) ((vuint8 *)regs)[(r_)]

headers/private/graphics/skeleton/macros.h

742

#define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]

headers/private/graphics/skeleton/macros.h

743

#define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2]

headers/private/graphics/via/macros.h

804

#define ENG_REG8(r_) ((vuint8 *)regs)[(r_)]

headers/private/graphics/via/macros.h

805

#define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]

headers/private/graphics/via/macros.h

806

#define ENG_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]

headers/private/kernel/arch/arm64/arch_thread_types.h

17

uint64 regs[32 * 2];

headers/private/kernel/arch/arm64/arch_thread_types.h

50

uint64 regs[14]; // x19-x30, sp, tpidr_el0

headers/private/kernel/arch/x86/arch_hpet.h

22

#define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)

headers/private/kernel/arch/x86/arch_hpet.h

23

#define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)

headers/private/kernel/arch/x86/arch_hpet.h

24

#define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)

headers/private/kernel/arch/x86/arch_hpet.h

25

#define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)

headers/private/kernel/arch/x86/arch_hpet.h

26

#define HPET_GET_VENDOR_ID(regs) (((regs)->capabilities & HPET_CAP_MASK_VENDOR_ID) >> 16)

headers/private/kernel/arch/x86/arch_hpet.h

27

#define HPET_GET_PERIOD(regs) (((regs)->capabilities & HPET_CAP_MASK_PERIOD) >> 32)

headers/private/kernel/arch/x86/arch_hpet.h

34

#define HPET_IS_ENABLED(regs) ((regs)->config & HPET_CONF_MASK_ENABLED)

headers/private/kernel/arch/x86/arch_hpet.h

35

#define HPET_IS_LEGACY(regs) (((regs)->config & HPET_CONF_MASK_LEGACY) >> 1)

headers/private/kernel/boot/timer.h

20

addr_range regs;

headers/private/kernel/boot/uart.h

15

addr_range regs;

headers/private/shared/cpu_type.h

240

memcpy(name, &nameInfo.regs.eax, 4);

headers/private/shared/cpu_type.h

241

memcpy(name + 4, &nameInfo.regs.ebx, 4);

headers/private/shared/cpu_type.h

242

memcpy(name + 8, &nameInfo.regs.ecx, 4);

headers/private/shared/cpu_type.h

243

memcpy(name + 12, &nameInfo.regs.edx, 4);

headers/private/shared/cpu_type.h

256

return info.regs.ebx & 0xff;

src/add-ons/accelerants/3dfx/accelerant.cpp

43

gInfo.regsArea = clone_area("3DFX regs area", (void**)&(gInfo.regs),

src/add-ons/accelerants/3dfx/accelerant.cpp

60

gInfo.regs = 0;

src/add-ons/accelerants/3dfx/accelerant.h

177

#define INREG8(addr) *((vuint8*)(gInfo.regs + addr))

src/add-ons/accelerants/3dfx/accelerant.h

178

#define INREG16(addr) *((vuint16*)(gInfo.regs + addr))

src/add-ons/accelerants/3dfx/accelerant.h

179

#define INREG32(addr) *((vuint32*)(gInfo.regs + addr))

src/add-ons/accelerants/3dfx/accelerant.h

181

#define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/3dfx/accelerant.h

182

#define OUTREG16(addr, val) *((vuint16*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/3dfx/accelerant.h

183

#define OUTREG32(addr, val) *((vuint32*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/3dfx/accelerant.h

38

uint8* regs; // base address of MMIO register area

src/add-ons/accelerants/ati/accelerant.cpp

41

gInfo.regsArea = clone_area("ATI regs area", (void**)&(gInfo.regs),

src/add-ons/accelerants/ati/accelerant.cpp

67

gInfo.regs = 0;

src/add-ons/accelerants/ati/accelerant.h

236

#define INREG8(addr) *((vuint8*)(gInfo.regs + addr))

src/add-ons/accelerants/ati/accelerant.h

237

#define INREG16(addr) *((vuint16*)(gInfo.regs + addr))

src/add-ons/accelerants/ati/accelerant.h

238

#define INREG(addr) *((vuint32*)(gInfo.regs + addr))

src/add-ons/accelerants/ati/accelerant.h

240

#define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/ati/accelerant.h

241

#define OUTREG16(addr, val) *((vuint16*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/ati/accelerant.h

242

#define OUTREG(addr, val) *((vuint32*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/ati/accelerant.h

34

uint8* regs; // base address of MMIO register area

src/add-ons/accelerants/intel_810/accelerant.cpp

78

gInfo.regsArea = clone_area("i810 regs area", (void**)&(gInfo.regs),

src/add-ons/accelerants/intel_810/accelerant.cpp

95

gInfo.regs = 0;

src/add-ons/accelerants/intel_810/accelerant.h

33

uint8* regs; // base address of MMIO register area

src/add-ons/accelerants/intel_810/i810_regs.h

111

#define INREG8(addr) (*((vuint8*)(gInfo.regs + (addr))))

src/add-ons/accelerants/intel_810/i810_regs.h

112

#define INREG16(addr) (*((vuint16*)(gInfo.regs + (addr))))

src/add-ons/accelerants/intel_810/i810_regs.h

113

#define INREG32(addr) (*((vuint32*)(gInfo.regs + (addr))))

src/add-ons/accelerants/intel_810/i810_regs.h

115

#define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val))

src/add-ons/accelerants/intel_810/i810_regs.h

116

#define OUTREG16(addr, val) (*((vuint16*)(gInfo.regs + (addr))) = (val))

src/add-ons/accelerants/intel_810/i810_regs.h

117

#define OUTREG32(addr, val) (*((vuint32*)(gInfo.regs + (addr))) = (val))

src/add-ons/accelerants/matrox/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/matrox/InitAccelerant.c

57

regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,

src/add-ons/accelerants/matrox/InitAccelerant.c

83

regs = 0;

src/add-ons/accelerants/matrox/engine/mga_globals.c

14

vuint32 *regs;

src/add-ons/accelerants/matrox/engine/mga_globals.h

5

extern vuint32 *regs;

src/add-ons/accelerants/matrox/global.h

5

extern vuint32 *regs;

src/add-ons/accelerants/neomagic/InitAccelerant.c

113

regs = 0;

src/add-ons/accelerants/neomagic/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/neomagic/InitAccelerant.c

63

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/neomagic/InitAccelerant.c

69

regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,

src/add-ons/accelerants/neomagic/engine/nm_globals.c

15

vuint32 *regs, *regs2;

src/add-ons/accelerants/neomagic/engine/nm_globals.h

5

extern vuint32 *regs, *regs2;

src/add-ons/accelerants/nvidia/InitAccelerant.c

55

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/nvidia/InitAccelerant.c

60

regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,

src/add-ons/accelerants/nvidia/InitAccelerant.c

83

regs = 0;

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1358

&(regs[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1361

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1364

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1367

&(regs[(si->engine.fifo.ch_ptr[NV_IMAGE_BLIT]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_acc.c

1370

&(regs[(si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT]) >> 2]);

src/add-ons/accelerants/nvidia/engine/nv_globals.c

16

vuint32 *regs;

src/add-ons/accelerants/nvidia/engine/nv_globals.h

6

extern vuint32 *regs;

src/add-ons/accelerants/radeon/Acceleration.c

100

OUTREG( ai->regs, RADEON_DST_HEIGHT_WIDTH, ((list->height + 1) << 16 ) | (list->width + 1));

src/add-ons/accelerants/radeon/Acceleration.c

166

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)

src/add-ons/accelerants/radeon/Acceleration.c

171

OUTREG(ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);

src/add-ons/accelerants/radeon/Acceleration.c

172

OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));

src/add-ons/accelerants/radeon/Acceleration.c

178

OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);

src/add-ons/accelerants/radeon/Acceleration.c

179

OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom - list->top + 1));

src/add-ons/accelerants/radeon/Acceleration.c

249

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, ((vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT)

src/add-ons/accelerants/radeon/Acceleration.c

255

OUTREG(ai->regs, RADEON_DP_CNTL, (RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM));

src/add-ons/accelerants/radeon/Acceleration.c

261

OUTREG(ai->regs, RADEON_DST_Y_X, (list->top << 16) | list->left);

src/add-ons/accelerants/radeon/Acceleration.c

262

OUTREG(ai->regs, RADEON_DST_WIDTH_HEIGHT, ((list->right - list->left + 1) << 16) | (list->bottom - list->top + 1));

src/add-ons/accelerants/radeon/Acceleration.c

330

OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL, 0

src/add-ons/accelerants/radeon/Acceleration.c

338

OUTREG( ai->regs, RADEON_DST_LINE_PATCOUNT, 0x55 << RADEON_BRES_CNTL_SHIFT);

src/add-ons/accelerants/radeon/Acceleration.c

342

OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR, colorIndex);

src/add-ons/accelerants/radeon/Acceleration.c

352

OUTREG( ai->regs, RADEON_DST_LINE_START, (y << 16) | x);

src/add-ons/accelerants/radeon/Acceleration.c

353

OUTREG( ai->regs, RADEON_DST_LINE_END, ((y) << 16) | (x + width));

src/add-ons/accelerants/radeon/Acceleration.c

408

OUTREG( ai->regs, RADEON_RB3D_CNTL, 0 );

src/add-ons/accelerants/radeon/Acceleration.c

463

OUTREG( ai->regs, RADEON_DEFAULT_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

464

OUTREG( ai->regs, RADEON_DST_PITCH_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

465

OUTREG( ai->regs, RADEON_SRC_PITCH_OFFSET, pitch_offset );

src/add-ons/accelerants/radeon/Acceleration.c

467

OUTREG( ai->regs, RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX

src/add-ons/accelerants/radeon/Acceleration.c

470

OUTREG( ai->regs, RADEON_DP_GUI_MASTER_CNTL,

src/add-ons/accelerants/radeon/Acceleration.c

483

OUTREG( ai->regs, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

484

OUTREG( ai->regs, RADEON_DP_BRUSH_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/radeon/Acceleration.c

485

OUTREG( ai->regs, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

486

OUTREG( ai->regs, RADEON_DP_SRC_BKGD_CLR, 0x00000000);

src/add-ons/accelerants/radeon/Acceleration.c

487

OUTREG( ai->regs, RADEON_DP_WRITE_MASK, 0xffffffff);

src/add-ons/accelerants/radeon/Acceleration.c

73

OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT

src/add-ons/accelerants/radeon/Acceleration.c

92

OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0)

src/add-ons/accelerants/radeon/Acceleration.c

96

OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left);

src/add-ons/accelerants/radeon/Acceleration.c

97

OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left);

src/add-ons/accelerants/radeon/CP.c

339

INREG( ai->regs, RADEON_CP_RB_RPTR );

src/add-ons/accelerants/radeon/CP.c

347

OUTREG( ai->regs, RADEON_CP_RB_WPTR, cp->ring.tail );

src/add-ons/accelerants/radeon/Cursor.c

197

OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_OFF, RADEON_CUR_LOCK

src/add-ons/accelerants/radeon/Cursor.c

200

OUTREG( ai->regs, RADEON_CUR_HORZ_VERT_POSN, RADEON_CUR_LOCK

src/add-ons/accelerants/radeon/Cursor.c

203

OUTREG( ai->regs, RADEON_CUR_OFFSET,

src/add-ons/accelerants/radeon/Cursor.c

206

OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_OFF, RADEON_CUR2_LOCK

src/add-ons/accelerants/radeon/Cursor.c

209

OUTREG( ai->regs, RADEON_CUR2_HORZ_VERT_POSN, RADEON_CUR2_LOCK

src/add-ons/accelerants/radeon/Cursor.c

212

OUTREG( ai->regs, RADEON_CUR2_OFFSET,

src/add-ons/accelerants/radeon/Cursor.c

227

tmp = INREG( ai->regs, RADEON_CRTC_GEN_CNTL );

src/add-ons/accelerants/radeon/Cursor.c

235

OUTREG( ai->regs, RADEON_CRTC_GEN_CNTL, tmp );

src/add-ons/accelerants/radeon/Cursor.c

238

tmp = INREG( ai->regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/Cursor.c

245

OUTREG( ai->regs, RADEON_CRTC2_GEN_CNTL, tmp );

src/add-ons/accelerants/radeon/Cursor.c

25

OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff );

src/add-ons/accelerants/radeon/Cursor.c

26

OUTREG( ai->regs, RADEON_CUR_CLR1, 0 );

src/add-ons/accelerants/radeon/Cursor.c

28

OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff );

src/add-ons/accelerants/radeon/Cursor.c

29

OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 );

src/add-ons/accelerants/radeon/EngineManagment.c

86

OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);

src/add-ons/accelerants/radeon/EngineManagment.c

87

OUTREG( ai->regs, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |

src/add-ons/accelerants/radeon/InitAccelerant.c

132

ai->regs = 0;

src/add-ons/accelerants/radeon/InitAccelerant.c

63

ai->regs_area = clone_area( "Radeon regs area", (void **)&ai->regs, B_ANY_ADDRESS,

src/add-ons/accelerants/radeon/SetDisplayMode.c

100

OUTREG( regs, RADEON_CRTC_MORE_CNTL, 0 );

src/add-ons/accelerants/radeon/SetDisplayMode.c

111

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/SetDisplayMode.c

263

OUTREG( regs, RADEON_SURFACE_CNTL, surface_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

283

SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

284

SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

285

SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

286

SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

287

SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

288

SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

289

SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

290

SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

291

SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

292

SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( regs, RADEON_FP_GEN_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

293

SHOW_FLOW( 0, "RADEON_FP2_GEN_CNTL %08X ", INREG( regs, RADEON_FP2_GEN_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

294

SHOW_FLOW( 0, "RADEON_LVDS_GEN_CNTL %08X ", INREG( regs, RADEON_LVDS_GEN_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

295

SHOW_FLOW( 0, "RADEON_TMDS_PLL_CNTL %08X ", INREG( regs, RADEON_TMDS_PLL_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

296

SHOW_FLOW( 0, "RADEON_TMDS_TRANSMITTER_CNTL %08X ", INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

297

SHOW_FLOW( 0, "RADEON_FP_H_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H_SYNC_STRT_WID ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

298

SHOW_FLOW( 0, "RADEON_FP_V_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V_SYNC_STRT_WID ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

299

SHOW_FLOW( 0, "RADEON_FP_H2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

300

SHOW_FLOW( 0, "RADEON_FP_V2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ));

src/add-ons/accelerants/radeon/SetDisplayMode.c

324

int_cntl = INREG( ai->regs, RADEON_GEN_INT_CNTL );

src/add-ons/accelerants/radeon/SetDisplayMode.c

334

OUTREG( ai->regs, RADEON_GEN_INT_CNTL, int_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

339

OUTREG( ai->regs, RADEON_GEN_INT_STATUS, int_cntl );

src/add-ons/accelerants/radeon/SetDisplayMode.c

523

OUTREGP( ai->regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );

src/add-ons/accelerants/radeon/SetDisplayMode.c

529

si->dac_cntl2 = INREG( ai->regs, RADEON_DAC_CNTL2 );

src/add-ons/accelerants/radeon/SetDisplayMode.c

86

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/SetDisplayMode.c

90

OUTREG( regs, common_regs[i].reg, common_regs[i].val );

src/add-ons/accelerants/radeon/SetDisplayMode.c

93

OUTREGP( regs, RADEON_CRTC_GEN_CNTL,

src/add-ons/accelerants/radeon/crtc.c

143

OUTREG( ai->regs, crtc->crtc_idx == 0 ? RADEON_CRTC_OFFSET : RADEON_CRTC2_OFFSET, offset );

src/add-ons/accelerants/radeon/crtc.c

22

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/crtc.c

27

OUTREGP( regs, RADEON_CRTC_GEN_CNTL, values->crtc_gen_cntl,

src/add-ons/accelerants/radeon/crtc.c

30

OUTREG( regs, RADEON_CRTC_H_TOTAL_DISP, values->crtc_h_total_disp );

src/add-ons/accelerants/radeon/crtc.c

31

OUTREG( regs, RADEON_CRTC_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

32

OUTREG( regs, RADEON_CRTC_V_TOTAL_DISP, values->crtc_v_total_disp );

src/add-ons/accelerants/radeon/crtc.c

33

OUTREG( regs, RADEON_CRTC_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

34

OUTREG( regs, RADEON_CRTC_OFFSET_CNTL, values->crtc_offset_cntl );

src/add-ons/accelerants/radeon/crtc.c

35

OUTREG( regs, RADEON_CRTC_PITCH, values->crtc_pitch );

src/add-ons/accelerants/radeon/crtc.c

38

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc_gen_cntl,

src/add-ons/accelerants/radeon/crtc.c

44

OUTREG( regs, RADEON_CRTC2_H_TOTAL_DISP, values->crtc_h_total_disp );

src/add-ons/accelerants/radeon/crtc.c

45

OUTREG( regs, RADEON_CRTC2_H_SYNC_STRT_WID, values->crtc_h_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

46

OUTREG( regs, RADEON_CRTC2_V_TOTAL_DISP, values->crtc_v_total_disp );

src/add-ons/accelerants/radeon/crtc.c

47

OUTREG( regs, RADEON_CRTC2_V_SYNC_STRT_WID, values->crtc_v_sync_strt_wid );

src/add-ons/accelerants/radeon/crtc.c

48

OUTREG( regs, RADEON_CRTC2_OFFSET_CNTL, values->crtc_offset_cntl );

src/add-ons/accelerants/radeon/crtc.c

49

OUTREG( regs, RADEON_CRTC2_PITCH, values->crtc_pitch );

src/add-ons/accelerants/radeon/dpms.c

104

OUTREGP( regs, RADEON_FP_GEN_CNTL, RADEON_FP_FPON | RADEON_FP_TMDS_EN,

src/add-ons/accelerants/radeon/dpms.c

110

OUTREGP( regs, RADEON_FP_GEN_CNTL, 0, ~RADEON_FP_FPON | RADEON_FP_TMDS_EN );

src/add-ons/accelerants/radeon/dpms.c

119

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

126

OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);

src/add-ons/accelerants/radeon/dpms.c

127

OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_FPON, ~RADEON_FP2_FPON);

src/add-ons/accelerants/radeon/dpms.c

129

OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN);

src/add-ons/accelerants/radeon/dpms.c

135

OUTREGP( regs, RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN );

src/add-ons/accelerants/radeon/dpms.c

136

OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_FPON);

src/add-ons/accelerants/radeon/dpms.c

138

OUTREGP( regs, RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN);

src/add-ons/accelerants/radeon/dpms.c

150

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

154

OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, ~RADEON_CRTC_DISPLAY_DIS );

src/add-ons/accelerants/radeon/dpms.c

160

OUTREGP( regs, RADEON_CRTC_EXT_CNTL,

src/add-ons/accelerants/radeon/dpms.c

172

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

176

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0,

src/add-ons/accelerants/radeon/dpms.c

180

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

184

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

188

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

198

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

204

OUTREGP( regs, RADEON_CRTC_EXT_CNTL, 0, mask );

src/add-ons/accelerants/radeon/dpms.c

207

OUTREGP( regs, RADEON_CRTC_EXT_CNTL,

src/add-ons/accelerants/radeon/dpms.c

211

OUTREGP( regs, RADEON_CRTC_EXT_CNTL,

src/add-ons/accelerants/radeon/dpms.c

215

OUTREGP( regs, RADEON_CRTC_EXT_CNTL,

src/add-ons/accelerants/radeon/dpms.c

224

OUTREGP( regs, RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B );

src/add-ons/accelerants/radeon/dpms.c

230

OUTREGP( regs, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B,

src/add-ons/accelerants/radeon/dpms.c

240

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

246

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, mask );

src/add-ons/accelerants/radeon/dpms.c

249

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), mask );

src/add-ons/accelerants/radeon/dpms.c

252

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), mask);

src/add-ons/accelerants/radeon/dpms.c

255

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL,

src/add-ons/accelerants/radeon/dpms.c

263

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_DISP_REQ_EN_B );

src/add-ons/accelerants/radeon/dpms.c

269

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_REQ_EN_B,

src/add-ons/accelerants/radeon/dpms.c

281

OUTREG( ai->regs, RADEON_TV_LINEAR_GAIN_SETTINGS,

src/add-ons/accelerants/radeon/dpms.c

345

tmp = INREG( di->regs, RADEON_CRTC_EXT_CNTL );

src/add-ons/accelerants/radeon/dpms.c

365

tmp = INREG( di->regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/dpms.c

59

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/dpms.c

68

OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON );

src/add-ons/accelerants/radeon/dpms.c

70

OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON );

src/add-ons/accelerants/radeon/dpms.c

78

old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);

src/add-ons/accelerants/radeon/dpms.c

82

Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );

src/add-ons/accelerants/radeon/dpms.c

84

OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) );

src/add-ons/accelerants/radeon/dpms.c

87

Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );

src/add-ons/accelerants/radeon/dpms.c

97

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/driver_wrapper.c

34

int slots = INREG( ai->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;

src/add-ons/accelerants/radeon/flat_panel.c

110

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/flat_panel.c

112

OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch );

src/add-ons/accelerants/radeon/flat_panel.c

113

OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch );

src/add-ons/accelerants/radeon/flat_panel.c

120

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/flat_panel.c

122

values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );

src/add-ons/accelerants/radeon/flat_panel.c

123

values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );

src/add-ons/accelerants/radeon/flat_panel.c

124

values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );

src/add-ons/accelerants/radeon/flat_panel.c

125

values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );

src/add-ons/accelerants/radeon/flat_panel.c

126

values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );

src/add-ons/accelerants/radeon/flat_panel.c

127

values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );

src/add-ons/accelerants/radeon/flat_panel.c

128

values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );

src/add-ons/accelerants/radeon/flat_panel.c

129

values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID );

src/add-ons/accelerants/radeon/flat_panel.c

130

values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID );

src/add-ons/accelerants/radeon/flat_panel.c

131

values->bios_4_scratch = INREG( regs, RADEON_BIOS_4_SCRATCH );

src/add-ons/accelerants/radeon/flat_panel.c

132

values->bios_5_scratch = INREG( regs, RADEON_BIOS_5_SCRATCH );

src/add-ons/accelerants/radeon/flat_panel.c

133

values->bios_6_scratch = INREG( regs, RADEON_BIOS_6_SCRATCH );

src/add-ons/accelerants/radeon/flat_panel.c

23

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/flat_panel.c

25

values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );

src/add-ons/accelerants/radeon/flat_panel.c

254

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/flat_panel.c

258

OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 );

src/add-ons/accelerants/radeon/flat_panel.c

26

values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );

src/add-ons/accelerants/radeon/flat_panel.c

262

OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,

src/add-ons/accelerants/radeon/flat_panel.c

264

OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,

src/add-ons/accelerants/radeon/flat_panel.c

266

OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

267

OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

270

OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

271

OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid );

src/add-ons/accelerants/radeon/flat_panel.c

277

OUTREG( regs, RADEON_GRPH_BUFFER_CNTL,

src/add-ons/accelerants/radeon/flat_panel.c

278

INREG( regs, RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);

src/add-ons/accelerants/radeon/flat_panel.c

282

OUTREG( regs, RADEON_BIOS_4_SCRATCH, values->bios_4_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

283

OUTREG( regs, RADEON_BIOS_5_SCRATCH, values->bios_5_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

284

OUTREG( regs, RADEON_BIOS_6_SCRATCH, values->bios_6_scratch);

src/add-ons/accelerants/radeon/flat_panel.c

295

old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);

src/add-ons/accelerants/radeon/flat_panel.c

301

Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );

src/add-ons/accelerants/radeon/flat_panel.c

306

tmp = INREG( regs, RADEON_LVDS_GEN_CNTL);

src/add-ons/accelerants/radeon/flat_panel.c

311

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

315

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

319

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl | RADEON_LVDS_BLON );

src/add-ons/accelerants/radeon/flat_panel.c

321

OUTREG( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl );

src/add-ons/accelerants/radeon/flat_panel.c

327

Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );

src/add-ons/accelerants/radeon/internal_tv_out.c

114

Radeon_OUTPLL( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/internal_tv_out.c

129

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/internal_tv_out.c

135

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_RD);

src/add-ons/accelerants/radeon/internal_tv_out.c

142

status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );

src/add-ons/accelerants/radeon/internal_tv_out.c

148

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0);

src/add-ons/accelerants/radeon/internal_tv_out.c

149

res = INREG( regs, RADEON_TV_HOST_READ_DATA );

src/add-ons/accelerants/radeon/internal_tv_out.c

161

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/internal_tv_out.c

168

OUTREG( regs, RADEON_TV_HOST_WRITE_DATA, value );

src/add-ons/accelerants/radeon/internal_tv_out.c

169

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_TV_HOST_RD_WT_CNTL_WT );

src/add-ons/accelerants/radeon/internal_tv_out.c

176

status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );

src/add-ons/accelerants/radeon/internal_tv_out.c

182

OUTREG( regs, RADEON_TV_HOST_RD_WT_CNTL, 0 );

src/add-ons/accelerants/radeon/internal_tv_out.c

210

OUTREG( ai->regs, RADEON_TV_MASTER_CNTL,

src/add-ons/accelerants/radeon/internal_tv_out.c

233

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/internal_tv_out.c

237

INREG( regs, mapping->address );

src/add-ons/accelerants/radeon/internal_tv_out.c

253

Radeon_INPLL( ai->regs, ai->si->asic, mapping->address );

src/add-ons/accelerants/radeon/internal_tv_out.c

93

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/internal_tv_out.c

99

OUTREG( regs, mapping->address, *(uint32 *)((char *)(values) + mapping->offset) );

src/add-ons/accelerants/radeon/monitor_detection.c

1017

if (INREG(ai->regs, RADEON_FP_GEN_CNTL) & (1 << 7) || (!si->is_mobility)) {

src/add-ons/accelerants/radeon/monitor_detection.c

104

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

1053

if (si->is_mobility && (INREG(ai->regs, RADEON_BIOS_4_SCRATCH) & 4)) {

src/add-ons/accelerants/radeon/monitor_detection.c

1061

if (si->is_mobility && (INREG(ai->regs, RADEON_FP2_GEN_CNTL) & RADEON_FP2_FPON)) {

src/add-ons/accelerants/radeon/monitor_detection.c

109

old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

112

OUTREG(regs, RADEON_CRTC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

116

old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

121

OUTREG(regs, RADEON_DAC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

124

old_dac_cntl = INREG(regs, RADEON_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

128

OUTREG(regs, RADEON_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

137

found = (INREG(regs, RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) != 0;

src/add-ons/accelerants/radeon/monitor_detection.c

143

OUTREG(regs, RADEON_DAC_CNTL, old_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

144

OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

145

OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

159

old_vclk_ecp_cntl = Radeon_INPLL(ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_detection.c

164

Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

169

Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

180

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

185

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

189

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

192

old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

196

OUTREG(regs, RADEON_TV_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

202

OUTREG(regs, RADEON_DAC_EXT_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

204

old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);

src/add-ons/accelerants/radeon/monitor_detection.c

209

OUTREG(regs, RADEON_DAC_CNTL2, value);

src/add-ons/accelerants/radeon/monitor_detection.c

214

found = (INREG(regs, RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) != 0;

src/add-ons/accelerants/radeon/monitor_detection.c

218

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

219

OUTREG(regs, RADEON_DAC_EXT_CNTL, 0);

src/add-ons/accelerants/radeon/monitor_detection.c

220

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

221

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

231

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

236

old_radeon_gpiopad_a = INREG(regs, RADEON_GPIOPAD_A);

src/add-ons/accelerants/radeon/monitor_detection.c

239

OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

240

OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

241

OUTREGP(regs, RADEON_GPIOPAD_A, 1, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

243

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

252

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

254

old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

257

OUTREG(regs, RADEON_TV_DAC_CNTL, RADEON_TV_DAC_CNTL_NBLANK

src/add-ons/accelerants/radeon/monitor_detection.c

262

OUTREG(regs, RADEON_DAC_EXT_CNTL, RADEON_DAC2_FORCE_BLANK_OFF_EN

src/add-ons/accelerants/radeon/monitor_detection.c

266

old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);

src/add-ons/accelerants/radeon/monitor_detection.c

269

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2 | RADEON_DAC2_CLK_SEL_CRT

src/add-ons/accelerants/radeon/monitor_detection.c

275

found = (INREG(regs, RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) != 0;

src/add-ons/accelerants/radeon/monitor_detection.c

278

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

279

OUTREG(regs, RADEON_DAC_EXT_CNTL, 0);

src/add-ons/accelerants/radeon/monitor_detection.c

280

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

281

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

283

OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

334

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

345

old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);

src/add-ons/accelerants/radeon/monitor_detection.c

347

OUTREG(regs, RADEON_DAC_CNTL2, value);

src/add-ons/accelerants/radeon/monitor_detection.c

349

old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

350

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

351

old_tv_master_cntl = INREG(regs, RADEON_TV_MASTER_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

364

OUTREG(regs, RADEON_TV_MASTER_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

366

old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

368

config_cntl = INREG(regs, RADEON_CONFIG_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

376

OUTREG(regs, RADEON_TV_DAC_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

378

old_pre_dac_mux_cntl = INREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

387

OUTREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

393

value = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

40

vuint8 *regs = info->ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

404

OUTREG(regs, RADEON_TV_PRE_DAC_MUX_CNTL, old_pre_dac_mux_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

405

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

406

OUTREG(regs, RADEON_TV_MASTER_CNTL, old_tv_master_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

407

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

408

OUTREG(regs, RADEON_CRTC_EXT_CNTL, old_crtc_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

409

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

419

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

424

old_radeon_gpiopad_a = INREG(regs, RADEON_GPIOPAD_A);

src/add-ons/accelerants/radeon/monitor_detection.c

427

OUTREGP(regs, RADEON_GPIOPAD_EN, 1, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

428

OUTREGP(regs, RADEON_GPIOPAD_MASK, 1, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

429

OUTREGP(regs, RADEON_GPIOPAD_A, 0, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

43

value = INREG(regs, info->port);

src/add-ons/accelerants/radeon/monitor_detection.c

431

old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);

src/add-ons/accelerants/radeon/monitor_detection.c

434

OUTREG(regs, RADEON_DAC_CNTL2, RADEON_DAC2_CLK_SEL_CRT);

src/add-ons/accelerants/radeon/monitor_detection.c

436

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

441

OUTREG(regs, RADEON_CRTC2_GEN_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

444

old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

447

OUTREG(regs, RADEON_DAC_EXT_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

452

old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

455

OUTREG(regs, RADEON_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

460

(void)INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

464

OUTREG(regs, RADEON_TV_DAC_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

471

(void)INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

476

tmp = INREG(regs, RADEON_TV_DAC_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

488

OUTREG(regs, RADEON_TV_DAC_CNTL, old_tv_dac_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

489

OUTREG(regs, RADEON_DAC_EXT_CNTL, old_dac_ext_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

490

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

491

OUTREG(regs, RADEON_DAC_CNTL2, old_dac_cntl2);

src/add-ons/accelerants/radeon/monitor_detection.c

493

OUTREGP(regs, RADEON_GPIOPAD_A, old_radeon_gpiopad_a, ~1);

src/add-ons/accelerants/radeon/monitor_detection.c

56

vuint8 *regs = info->ai->regs;

src/add-ons/accelerants/radeon/monitor_detection.c

59

value = INREG(regs, info->port);

src/add-ons/accelerants/radeon/monitor_detection.c

65

OUTREG(regs, info->port, value);

src/add-ons/accelerants/radeon/monitor_routing.c

29

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_routing.c

31

values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

32

values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );

src/add-ons/accelerants/radeon/monitor_routing.c

33

values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

34

values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

35

values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

36

values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

37

values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

422

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/monitor_routing.c

424

OUTREG( regs, RADEON_DAC_CNTL, values->dac_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

425

OUTREG( regs, RADEON_DAC_CNTL2, values->dac_cntl2 );

src/add-ons/accelerants/radeon/monitor_routing.c

426

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

428

OUTREG( regs, RADEON_DISP_OUTPUT_CNTL, values->disp_output_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

438

OUTREG( regs, RADEON_DISP_HW_DEBUG, values->disp_hw_debug );

src/add-ons/accelerants/radeon/monitor_routing.c

442

OUTREG( regs, RADEON_DISP_TV_OUT_CNTL, values->disp_tv_out_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

450

OUTREGP( regs, RADEON_GPIOPAD_A, values->gpiopad_a, ~1 );

src/add-ons/accelerants/radeon/monitor_routing.c

462

OUTREG( regs, RADEON_TV_DAC_CNTL, values->tv_dac_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

466

OUTREG( regs, RADEON_TV_MASTER_CNTL, values->tv_master_cntl );

src/add-ons/accelerants/radeon/monitor_routing.c

468

OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, ~(

src/add-ons/accelerants/radeon/monitor_routing.c

47

values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG );

src/add-ons/accelerants/radeon/monitor_routing.c

481

OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

485

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

491

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

496

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/monitor_routing.c

504

crtc_gen_cntl = INREG( regs, RADEON_CRTC_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

51

values->disp_tv_out_cntl = INREG( regs, RADEON_DISP_TV_OUT_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

513

OUTREGP( regs, RADEON_CRTC_GEN_CNTL, crtc_gen_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

521

crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

530

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

535

OUTREGP( regs, RADEON_CRTC_EXT_CNTL, values->crtc_ext_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

59

values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A );

src/add-ons/accelerants/radeon/monitor_routing.c

68

values->tv_dac_cntl = INREG( regs, RADEON_TV_DAC_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

72

values->tv_master_cntl = INREG( regs, RADEON_TV_MASTER_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

74

values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

75

values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );

src/add-ons/accelerants/radeon/overlay.c

101

Radeon_OUTPLLP( regs, si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/overlay.c

1022

OUTREG( ai->regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset);

src/add-ons/accelerants/radeon/overlay.c

1025

OUTREG( ai->regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

108

Radeon_OUTPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL,

src/add-ons/accelerants/radeon/overlay.c

109

(Radeon_INPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL) | (1<<18)));

src/add-ons/accelerants/radeon/overlay.c

162

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/overlay.c

263

OUTREG( regs, RADEON_OV0_LIN_TRANS_A, dwOvRCb | dwOvRY );

src/add-ons/accelerants/radeon/overlay.c

264

OUTREG( regs, RADEON_OV0_LIN_TRANS_B, dwOvROff | dwOvRCr );

src/add-ons/accelerants/radeon/overlay.c

265

OUTREG( regs, RADEON_OV0_LIN_TRANS_C, dwOvGCb | dwOvGY );

src/add-ons/accelerants/radeon/overlay.c

266

OUTREG( regs, RADEON_OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr );

src/add-ons/accelerants/radeon/overlay.c

267

OUTREG( regs, RADEON_OV0_LIN_TRANS_E, dwOvBCb | dwOvBY );

src/add-ons/accelerants/radeon/overlay.c

268

OUTREG( regs, RADEON_OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr );

src/add-ons/accelerants/radeon/overlay.c

317

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/overlay.c

336

OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_LOW, min32 );

src/add-ons/accelerants/radeon/overlay.c

337

OUTREG( regs, RADEON_OV0_GRAPHICS_KEY_CLR_HIGH, max32 );

src/add-ons/accelerants/radeon/overlay.c

338

OUTREG( regs, RADEON_OV0_KEY_CNTL,

src/add-ons/accelerants/radeon/overlay.c

534

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/overlay.c

56

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/overlay.c

68

OUTREG( regs, RADEON_OV0_SCALE_CNTL, RADEON_SCALER_SOFT_RESET );

src/add-ons/accelerants/radeon/overlay.c

69

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/overlay.c

70

OUTREG( regs, RADEON_OV0_FILTER_CNTL, // use fixed filter coefficients

src/add-ons/accelerants/radeon/overlay.c

75

OUTREG( regs, RADEON_OV0_KEY_CNTL, RADEON_GRAPHIC_KEY_FN_EQ |

src/add-ons/accelerants/radeon/overlay.c

78

OUTREG( regs, RADEON_OV0_TEST, 0 );

src/add-ons/accelerants/radeon/overlay.c

81

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

83

OUTREG( regs, RADEON_OV0_DEINTERLACE_PATTERN,

src/add-ons/accelerants/radeon/overlay.c

849

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, RADEON_REG_LD_CTL_LOCK );

src/add-ons/accelerants/radeon/overlay.c

852

while( (INREG( regs, RADEON_OV0_REG_LOAD_CNTL)

src/add-ons/accelerants/radeon/overlay.c

856

OUTREG( regs, RADEON_OV0_VID_BUF0_BASE_ADRS, offset );

src/add-ons/accelerants/radeon/overlay.c

857

OUTREG( regs, RADEON_OV0_VID_BUF_PITCH0_VALUE, node->buffer.bytes_per_row );

src/add-ons/accelerants/radeon/overlay.c

858

OUTREG( regs, RADEON_OV0_H_INC, p1_h_inc | (p23_h_inc << 16) );

src/add-ons/accelerants/radeon/overlay.c

859

OUTREG( regs, RADEON_OV0_STEP_BY, factors->p1_step_by | (factors->p23_step_by << 8) );

src/add-ons/accelerants/radeon/overlay.c

860

OUTREG( regs, RADEON_OV0_V_INC, v_inc );

src/add-ons/accelerants/radeon/overlay.c

862

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

865

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

869

OUTREG( regs, RADEON_OV0_P1_BLANK_LINES_AT_TOP,

src/add-ons/accelerants/radeon/overlay.c

871

OUTREG( regs, RADEON_OV0_P1_X_START_END, p1_x_end | (p1_x_start << 16) );

src/add-ons/accelerants/radeon/overlay.c

872

OUTREG( regs, RADEON_OV0_P1_H_ACCUM_INIT, p1_h_accum_init );

src/add-ons/accelerants/radeon/overlay.c

873

OUTREG( regs, RADEON_OV0_P1_V_ACCUM_INIT, p1_v_accum_init );

src/add-ons/accelerants/radeon/overlay.c

875

OUTREG( regs, RADEON_OV0_P23_BLANK_LINES_AT_TOP,

src/add-ons/accelerants/radeon/overlay.c

877

OUTREG( regs, RADEON_OV0_P2_X_START_END,

src/add-ons/accelerants/radeon/overlay.c

879

OUTREG( regs, RADEON_OV0_P3_X_START_END,

src/add-ons/accelerants/radeon/overlay.c

881

OUTREG( regs, RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init );

src/add-ons/accelerants/radeon/overlay.c

882

OUTREG( regs, RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init );

src/add-ons/accelerants/radeon/overlay.c

884

OUTREG( regs, RADEON_OV0_TEST, node->test_reg );

src/add-ons/accelerants/radeon/overlay.c

89

OUTREG( regs, std_gamma[i].reg,

src/add-ons/accelerants/radeon/overlay.c

897

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |

src/add-ons/accelerants/radeon/overlay.c

902

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl);

src/add-ons/accelerants/radeon/overlay.c

906

OUTREG( regs, RADEON_OV0_SCALE_CNTL, scale_ctrl |

src/add-ons/accelerants/radeon/overlay.c

913

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL,

src/add-ons/accelerants/radeon/overlay.c

916

OUTREG( regs, RADEON_OV0_REG_LOAD_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

936

OUTREG( ai->regs, RADEON_OV0_SCALE_CNTL, 0 );

src/add-ons/accelerants/radeon/overlay.c

965

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/overlay.c

989

OUTREG( regs,

src/add-ons/accelerants/radeon/overlay.c

996

OUTREG( regs, RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );

src/add-ons/accelerants/radeon/palette.c

104

OUTREG( ai->regs, RADEON_DAC_CNTL2,

src/add-ons/accelerants/radeon/palette.c

108

OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );

src/add-ons/accelerants/radeon/palette.c

111

OUTREG( ai->regs, RADEON_PALETTE_DATA,

src/add-ons/accelerants/radeon/palette.c

41

OUTREG( ai->regs, RADEON_DAC_CNTL2,

src/add-ons/accelerants/radeon/palette.c

45

OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );

src/add-ons/accelerants/radeon/palette.c

48

OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );

src/add-ons/accelerants/radeon/pll.c

29

if( (Radeon_INPLL( ai->regs, ai->si->asic, crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV )

src/add-ons/accelerants/radeon/pll.c

40

Radeon_OUTPLLP( ai->regs, ai->si->asic,

src/add-ons/accelerants/radeon/pll.c

457

vuint8 *regs = ai->regs;

src/add-ons/accelerants/radeon/pll.c

464

Radeon_OUTPLLP( regs, asic, crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,

src/add-ons/accelerants/radeon/pll.c

467

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

477

OUTREGP( regs, RADEON_CLOCK_CNTL_INDEX,

src/add-ons/accelerants/radeon/pll.c

481

RADEONPllErrataAfterIndex(regs, asic);

src/add-ons/accelerants/radeon/pll.c

487

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

492

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

498

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

503

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

511

Radeon_OUTPLL( regs, asic,

src/add-ons/accelerants/radeon/pll.c

515

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/pll.c

526

Radeon_OUTPLLP( regs, asic,

src/add-ons/accelerants/radeon/radeon_accelerant.h

44

vuint8 *regs; // pointer to mapped registers

src/add-ons/accelerants/radeon_hd/accelerant.cpp

134

(void**)&gInfo->regs, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA,

src/add-ons/accelerants/radeon_hd/accelerant.cpp

183

free(gDisplay[id]->regs);

src/add-ons/accelerants/radeon_hd/accelerant.cpp

79

gDisplay[id]->regs = (register_info*)malloc(sizeof(register_info));

src/add-ons/accelerants/radeon_hd/accelerant.cpp

80

if (gDisplay[id]->regs == NULL)

src/add-ons/accelerants/radeon_hd/accelerant.cpp

82

memset(gDisplay[id]->regs, 0, sizeof(register_info));

src/add-ons/accelerants/radeon_hd/accelerant.h

192

register_info* regs;

src/add-ons/accelerants/radeon_hd/accelerant.h

224

return *(volatile uint32*)(gInfo->regs + offset);

src/add-ons/accelerants/radeon_hd/accelerant.h

231

*(volatile uint32 *)(gInfo->regs + offset) = value;

src/add-ons/accelerants/radeon_hd/accelerant.h

54

vuint8* regs;

src/add-ons/accelerants/radeon_hd/display.cpp

101

regs->grphSurfaceOffsetY

src/add-ons/accelerants/radeon_hd/display.cpp

103

regs->grphXStart = EVERGREEN_GRPH_X_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

104

regs->grphYStart = EVERGREEN_GRPH_Y_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

105

regs->grphXEnd = EVERGREEN_GRPH_X_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

106

regs->grphYEnd = EVERGREEN_GRPH_Y_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

107

regs->modeDesktopHeight = EVERGREEN_DESKTOP_HEIGHT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

108

regs->modeDataFormat = EVERGREEN_DATA_FORMAT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

109

regs->viewportStart = EVERGREEN_VIEWPORT_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

110

regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

119

regs->vgaControl = AVIVO_D1VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

120

regs->grphPrimarySurfaceAddrHigh

src/add-ons/accelerants/radeon_hd/display.cpp

125

regs->vgaControl = AVIVO_D2VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

126

regs->grphPrimarySurfaceAddrHigh

src/add-ons/accelerants/radeon_hd/display.cpp

135

regs->crtcOffset = offset;

src/add-ons/accelerants/radeon_hd/display.cpp

137

regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

138

regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

139

regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

141

regs->grphPrimarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

143

regs->grphSecondarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

146

regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

147

regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

148

regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

149

regs->grphXStart = AVIVO_D1GRPH_X_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

150

regs->grphYStart = AVIVO_D1GRPH_Y_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

151

regs->grphXEnd = AVIVO_D1GRPH_X_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

152

regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

154

regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

155

regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

156

regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

157

regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

166

regs->vgaControl = AVIVO_D1VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

170

regs->vgaControl = AVIVO_D2VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

178

regs->crtcOffset = offset;

src/add-ons/accelerants/radeon_hd/display.cpp

180

regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

181

regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

182

regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

184

regs->grphPrimarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

186

regs->grphSecondarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

190

regs->grphPrimarySurfaceAddrHigh = 0xDEAD;

src/add-ons/accelerants/radeon_hd/display.cpp

191

regs->grphSecondarySurfaceAddrHigh = 0xDEAD;

src/add-ons/accelerants/radeon_hd/display.cpp

193

regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

194

regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

195

regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

196

regs->grphXStart = AVIVO_D1GRPH_X_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

197

regs->grphYStart = AVIVO_D1GRPH_Y_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

198

regs->grphXEnd = AVIVO_D1GRPH_X_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

199

regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

201

regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

202

regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

203

regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

204

regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

370

init_registers(gDisplay[displayIndex]->regs, displayIndex);

src/add-ons/accelerants/radeon_hd/display.cpp

42

init_registers(register_info* regs, uint8 crtcID)

src/add-ons/accelerants/radeon_hd/display.cpp

44

memset(regs, 0, sizeof(register_info));

src/add-ons/accelerants/radeon_hd/display.cpp

55

regs->vgaControl = AVIVO_D1VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

59

regs->vgaControl = AVIVO_D2VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

597

register_info* regs = gDisplay[crtcID]->regs;

src/add-ons/accelerants/radeon_hd/display.cpp

606

Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

609

Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

611

Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

613

Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

618

Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

620

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

621

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

622

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

624

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

625

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

626

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

63

regs->vgaControl = EVERGREEN_D3VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

633

Write32(OUT, EVERGREEN_DC_LUT_30_COLOR + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

638

Write32(OUT, NI_DEGAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

643

Write32(OUT, NI_GAMUT_REMAP_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

646

Write32(OUT, NI_REGAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

649

Write32(OUT, NI_OUTPUT_CSC_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

653

Write32(OUT, 0x6940 + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

662

register_info* regs = gDisplay[crtcID]->regs;

src/add-ons/accelerants/radeon_hd/display.cpp

67

regs->vgaControl = EVERGREEN_D4VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

670

Write32(OUT, AVIVO_DC_LUTA_CONTROL + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

672

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

673

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

674

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_RED + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

676

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

677

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

678

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

690

Write32(OUT, AVIVO_D1GRPH_LUT_SEL + regs->crtcOffset, crtcID);

src/add-ons/accelerants/radeon_hd/display.cpp

698

register_info* regs = gDisplay[crtcID]->regs;

src/add-ons/accelerants/radeon_hd/display.cpp

71

regs->vgaControl = EVERGREEN_D5VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

75

regs->vgaControl = EVERGREEN_D6VGA_CONTROL;

src/add-ons/accelerants/radeon_hd/display.cpp

802

Write32(OUT, regs->vgaControl, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

812

Write32(OUT, regs->grphPrimarySurfaceAddrHigh,

src/add-ons/accelerants/radeon_hd/display.cpp

814

Write32(OUT, regs->grphSecondarySurfaceAddrHigh,

src/add-ons/accelerants/radeon_hd/display.cpp

821

Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));

src/add-ons/accelerants/radeon_hd/display.cpp

822

Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));

src/add-ons/accelerants/radeon_hd/display.cpp

825

Write32(CRT, regs->grphControl, fbFormat);

src/add-ons/accelerants/radeon_hd/display.cpp

826

Write32(CRT, regs->grphSwapControl, fbSwap);

src/add-ons/accelerants/radeon_hd/display.cpp

83

regs->crtcOffset = offset;

src/add-ons/accelerants/radeon_hd/display.cpp

85

regs->grphEnable = EVERGREEN_GRPH_ENABLE + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

855

Write32(CRT, regs->grphSurfaceOffsetX, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

856

Write32(CRT, regs->grphSurfaceOffsetY, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

857

Write32(CRT, regs->grphXStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

858

Write32(CRT, regs->grphYStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

859

Write32(CRT, regs->grphXEnd, mode->virtual_width);

src/add-ons/accelerants/radeon_hd/display.cpp

86

regs->grphControl = EVERGREEN_GRPH_CONTROL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

860

Write32(CRT, regs->grphYEnd, mode->virtual_height);

src/add-ons/accelerants/radeon_hd/display.cpp

861

Write32(CRT, regs->grphPitch, widthAligned);

src/add-ons/accelerants/radeon_hd/display.cpp

863

Write32(CRT, regs->grphEnable, 1);

src/add-ons/accelerants/radeon_hd/display.cpp

866

Write32(CRT, regs->modeDesktopHeight, mode->virtual_height);

src/add-ons/accelerants/radeon_hd/display.cpp

87

regs->grphSwapControl = EVERGREEN_GRPH_SWAP_CONTROL + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

871

Write32(CRT, regs->viewportStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

872

Write32(CRT, regs->viewportSize,

src/add-ons/accelerants/radeon_hd/display.cpp

878

= Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);

src/add-ons/accelerants/radeon_hd/display.cpp

880

Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);

src/add-ons/accelerants/radeon_hd/display.cpp

882

Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

886

uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);

src/add-ons/accelerants/radeon_hd/display.cpp

888

Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);

src/add-ons/accelerants/radeon_hd/display.cpp

89

regs->grphPrimarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

890

Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

91

regs->grphSecondarySurfaceAddr

src/add-ons/accelerants/radeon_hd/display.cpp

93

regs->grphPrimarySurfaceAddrHigh

src/add-ons/accelerants/radeon_hd/display.cpp

95

regs->grphSecondarySurfaceAddrHigh

src/add-ons/accelerants/radeon_hd/display.cpp

98

regs->grphPitch = EVERGREEN_GRPH_PITCH + offset;

src/add-ons/accelerants/radeon_hd/display.cpp

99

regs->grphSurfaceOffsetX

src/add-ons/accelerants/radeon_hd/encoder.cpp

373

register_info* regs = gDisplay[crtcID]->regs;

src/add-ons/accelerants/radeon_hd/encoder.cpp

382

Write32(OUT, regs->modeDataFormat, 0);

src/add-ons/accelerants/s3/accel.cpp

42

gInfo.regsArea = clone_area("S3 regs area", (void**)&(gInfo.regs),

src/add-ons/accelerants/s3/accel.cpp

70

gInfo.regs = 0;

src/add-ons/accelerants/s3/accel.h

35

uint8* regs; // base address of MMIO register area

src/add-ons/accelerants/s3/register_io.cpp

17

#define INREG8(addr) *((vuint8*)(gInfo.regs + addr))

src/add-ons/accelerants/s3/register_io.cpp

18

#define INREG16(addr) *((vuint16*)(gInfo.regs + addr))

src/add-ons/accelerants/s3/register_io.cpp

19

#define INREG32(addr) *((vuint32*)(gInfo.regs + addr))

src/add-ons/accelerants/s3/register_io.cpp

21

#define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/s3/register_io.cpp

22

#define OUTREG16(addr, val) *((vuint16*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/s3/register_io.cpp

23

#define OUTREG32(addr, val) *((vuint32*)(gInfo.regs + addr)) = val

src/add-ons/accelerants/s3/savage.h

78

#define BCI_GET_PTR vuint32* bci_ptr = ((uint32*)(gInfo.regs + BCI_BUFFER_OFFSET))

src/add-ons/accelerants/skeleton/InitAccelerant.c

52

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/skeleton/InitAccelerant.c

57

regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,

src/add-ons/accelerants/skeleton/InitAccelerant.c

83

regs = 0;

src/add-ons/accelerants/skeleton/engine/globals.c

15

vuint32 *regs;

src/add-ons/accelerants/skeleton/engine/globals.h

5

extern vuint32 *regs;

src/add-ons/accelerants/via/InitAccelerant.c

53

regs = si->clone_bugfix_regs;

src/add-ons/accelerants/via/InitAccelerant.c

58

regs_area = clone_area(DRIVER_PREFIX " regs", (void **)&regs, B_ANY_ADDRESS,

src/add-ons/accelerants/via/InitAccelerant.c

84

regs = 0;

src/add-ons/accelerants/via/engine/globals.c

15

vuint32 *regs;

src/add-ons/accelerants/via/engine/globals.h

5

extern vuint32 *regs;

src/add-ons/kernel/bus_managers/fdt/fdt_module.cpp

418

fdt_device_get_reg(fdt_device* dev, uint32 ord, uint64* regs, uint64* len)

src/add-ons/kernel/bus_managers/fdt/fdt_module.cpp

443

*regs = fdt32_to_cpu(*(const uint32*)addressPtr);

src/add-ons/kernel/bus_managers/fdt/fdt_module.cpp

446

*regs = fdt64_to_cpu(*(const uint64*)addressPtr);

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBusDevice_x86.cpp

29

return (cpuInfo.regs.eax & HV_CPUID_FEATURE_TIME_REF_COUNTER) != 0;

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

28

if (cpuInfo.regs.eax < IA32_CPUID_LEAF_HV_IMP_LIMITS) {

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

35

if (cpuInfo.regs.eax != HV_CPUID_INTERFACE_ID) {

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

44

cpuInfo.regs.eax, cpuInfo.regs.ebx, cpuInfo.regs.ecx, cpuInfo.regs.edx);

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

45

if ((cpuInfo.regs.eax & HV_CPUID_EAX_REQUIRED_FEATURES) == 0

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

46

|| (cpuInfo.regs.ebx & HV_CPUID_EBX_REQUIRED_FEATURES) == 0) {

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

53

TRACE("Hyper-V version: %d.%d.%d [SP%d]\n", cpuInfo.regs.ebx >> 16, cpuInfo.regs.ebx & 0xFFFF,

src/add-ons/kernel/bus_managers/hyperv/arch/x86/VMBus_x86.cpp

54

cpuInfo.regs.eax, cpuInfo.regs.ecx);

src/add-ons/kernel/busses/i2c/ocores/ocores_i2c.cpp

149

uint64 regs = 0;

src/add-ons/kernel/busses/i2c/ocores/ocores_i2c.cpp

151

if (!parentModule->get_reg(parentDev, 0, &regs, &regsLen))

src/add-ons/kernel/busses/i2c/ocores/ocores_i2c.cpp

154

fRegsArea.SetTo(map_physical_memory("Ocores i2c MMIO", regs, regsLen, B_ANY_KERNEL_ADDRESS,

src/add-ons/kernel/busses/pci/ecam/ECAMPCIControllerFDT.cpp

85

uint64 regs = 0;

src/add-ons/kernel/busses/pci/ecam/ECAMPCIControllerFDT.cpp

86

if (!fdtModule->get_reg(fdtDev, 0, &regs, &fRegsLen))

src/add-ons/kernel/busses/pci/ecam/ECAMPCIControllerFDT.cpp

89

fRegsArea.SetTo(map_physical_memory("PCI Config MMIO", regs, fRegsLen, B_ANY_KERNEL_ADDRESS,

src/add-ons/kernel/busses/virtio/virtio_mmio/VirtioDevice.cpp

296

VirtioDevice::Init(phys_addr_t regs, size_t regsLen, int32 irq, int32 queueCnt)

src/add-ons/kernel/busses/virtio/virtio_mmio/VirtioDevice.cpp

299

regs, regsLen, B_ANY_KERNEL_ADDRESS,

src/add-ons/kernel/busses/virtio/virtio_mmio/VirtioDevice.h

94

status_t Init(phys_addr_t regs, size_t regsLen, int32 irq, int32 queueCnt);

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

175

uint64 regs = 0;

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

188

if (!parentModule->get_reg(parentDev, 0, &regs, &regsLen)) {

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

207

regs = range.base;

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

212

AreaDeleter fRegsArea(map_physical_memory("Virtio MMIO", regs, regsLen,

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

261

uint64 regs = 0;

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

277

for (uint32 i = 0; parentModule->get_reg(parentDev, i, &regs, &regsLen);

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

280

i, regs, regsLen);

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

298

if (!parentModule->get_reg(parentDev, 0, &regs, &regsLen)) {

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

323

regs = range.base;

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

330

regs, regsLen);

src/add-ons/kernel/busses/virtio/virtio_mmio/virtio_mmio.cpp

339

status_t res = dev->Init(regs, regsLen, interrupt, 1);

src/add-ons/kernel/busses/virtio/virtio_pci/virtio_pci.cpp

88

} * v = (union regs*)buffer;

src/add-ons/kernel/cpu/x86/generic_x86.cpp

215

bits = cpuInfo.regs.eax & 0xff;

src/add-ons/kernel/drivers/audio/cmedia/cm.c

582

static uchar regs[] = {

src/add-ons/kernel/drivers/audio/cmedia/cm.c

590

uchar * ptr = regs;

src/add-ons/kernel/drivers/audio/cmedia/cm.c

600

while (ptr < regs + sizeof(regs)) {

src/add-ons/kernel/drivers/audio/cmedia/pcm.c

117

uint8 regs[0x2e];

src/add-ons/kernel/drivers/audio/cmedia/pcm.c

130

state->regs[ix] = get_indirect(port->card, ix+0x30);

src/add-ons/kernel/drivers/audio/cmedia/pcm.c

145

set_indirect(port->card, ix, state->regs[ix]+0x30, 0xff);

src/add-ons/kernel/drivers/audio/hda/driver.h

101

return *(vuint32*)(regs + reg);

src/add-ons/kernel/drivers/audio/hda/driver.h

106

*(regs + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

111

*(vuint16*)(regs + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

116

*(vuint32*)(regs + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

204

*(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

209

*(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

214

*(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;

src/add-ons/kernel/drivers/audio/hda/driver.h

62

vuint8* regs;

src/add-ons/kernel/drivers/audio/hda/driver.h

91

return *(regs + reg);

src/add-ons/kernel/drivers/audio/hda/driver.h

96

return *(vuint16*)(regs + reg);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1121

(void**)&controller->regs);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1351

controller->regs = NULL;

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1424

controller->regs = NULL;

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_ctrlr.c

808

ctrlr->regs = (volatile struct nvme_registers *)addr;

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_ctrlr.c

819

void *addr = (void *)ctrlr->regs;

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_internal.h

470

volatile struct nvme_registers *regs;

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_internal.h

736

nvme_mmio_read_4((__u32 *)&(sc)->regs->reg)

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_internal.h

739

nvme_mmio_read_8((__u64 *)&(sc)->regs->reg)

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_internal.h

742

nvme_mmio_write_4((__u32 *)&(sc)->regs->reg, val)

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_internal.h

745

nvme_mmio_write_8((__u64 *)&(sc)->regs->reg, val)

src/add-ons/kernel/drivers/disk/nvme/libnvme/nvme_qpair.c

917

doorbell_base = &ctrlr->regs->doorbell[0].sq_tdbl;

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.c

324

char *start = (char *)(device->regs) + SRAM_START_ADDRESS + SRAM_BASE_RISC_PROG;

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

36

void * regs;

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

55

#define reg_read8(offset) (*(volatile uint8 *) ((char *)(device->regs) + (offset)))

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

56

#define reg_read16(offset) (*(volatile uint16 *)((char *)(device->regs) + (offset)))

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

57

#define reg_read32(offset) (*(volatile uint32 *)((char *)(device->regs) + (offset)))

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

58

#define reg_write8(offset, value) (*(volatile uint8 *) ((char *)(device->regs) + (offset)) = value)

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

59

#define reg_write16(offset, value) (*(volatile uint16 *)((char *)(device->regs) + (offset)) = value)

src/add-ons/kernel/drivers/dvb/cx23882/cx23882.h

60

#define reg_write32(offset, value) (*(volatile uint32 *)((char *)(device->regs) + (offset)) = value)

src/add-ons/kernel/drivers/dvb/cx23882/dvb_interface.c

118

device->regs_area = map_mem(&device->regs, (addr_t)val,

src/add-ons/kernel/drivers/dvb/cx23882/dvb_interface.c

124

TRACE("mapped registers to %p\n", device->regs);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

177

(void**)&di.regs);

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

202

di.regs = NULL;

src/add-ons/kernel/drivers/graphics/3dfx/driver.cpp

67

vuint8* regs; // pointer to memory mapped registers

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

161

vuint8* regs; // pointer to memory mapped registers

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

269

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

270

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

271

regs.ebx = 0; // 0 = report DDC service

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

272

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

273

regs.es = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

274

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

276

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

280

if (regs.eax != 0x4f)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

284

if ((regs.ebx & 3) == 0)

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

296

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

297

regs.ebx = 1; // 1 = read EDID

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

298

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

299

regs.edx = 0;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

300

regs.es = ADDRESS_SEGMENT(edid);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

301

regs.edi = ADDRESS_OFFSET(edid);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

303

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

305

if (regs.eax != 0x4f) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

365

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

366

regs.eax = 0x4f02;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

367

regs.ebx = (mode & SET_MODE_MASK) | SET_MODE_LINEAR_BUFFER;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

369

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

374

if (status == B_OK && (regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

376

mode, regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

648

addr_t regs = addr_t(si.videoMemAddr) + regsOffset;

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

649

uint32 chipInfo = *((vuint32*)(regs + M64_CONFIG_CHIP_ID));

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

673

(void**)&di.regs);

src/add-ons/kernel/drivers/graphics/ati/driver.cpp

697

di.regs = NULL;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

120

#define INREG16(addr) (*((vuint16*)(di.regs + (addr))))

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

121

#define INREG32(addr) (*((vuint32*)(di.regs + (addr))))

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

123

#define OUTREG16(addr, val) (*((vuint16*)(di.regs + (addr))) = (val))

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

124

#define OUTREG32(addr, val) (*((vuint32*)(di.regs + (addr))) = (val))

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

168

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

169

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

170

regs.ebx = 0; // 0 = report DDC service

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

171

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

172

regs.es = 0;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

173

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

175

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

179

if (regs.eax != 0x4f)

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

183

if ((regs.ebx & 3) == 0)

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

195

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

196

regs.ebx = 1; // 1 = read EDID

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

197

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

198

regs.edx = 0;

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

199

regs.es = ADDRESS_SEGMENT(edid);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

200

regs.edi = ADDRESS_OFFSET(edid);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

202

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

204

if (regs.eax != 0x4f) {

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

290

(void**)&di.regs);

src/add-ons/kernel/drivers/graphics/intel_810/driver.cpp

64

vuint8* regs; // pointer to memory mapped registers

src/add-ons/kernel/drivers/graphics/matrox/driver.c

1007

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

1009

enable_vbi(regs);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

1011

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

151

static int caused_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

157

static void clear_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

162

static void enable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

167

static void disable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/matrox/driver.c

363

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/matrox/driver.c

364

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

54

vuint32 *regs; /* kernel's pointer to memory mapped registers */

src/add-ons/kernel/drivers/graphics/matrox/driver.c

567

di->regs = NULL;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

697

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

717

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

724

regs = di->regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

727

if (caused_vbi(regs)) {

src/add-ons/kernel/drivers/graphics/matrox/driver.c

729

clear_vbi(regs);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

731

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

801

disable_vbi(di->regs);

src/add-ons/kernel/drivers/graphics/matrox/driver.c

905

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/matrox/driver.c

915

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

154

static int caused_vbi(vuint32 * regs, vuint32 * regs2)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

161

static void clear_vbi(vuint32 * regs, vuint32 * regs2)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

166

static void enable_vbi(vuint32 * regs, vuint32 * regs2)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

171

static void disable_vbi(vuint32 * regs, vuint32 * regs2)

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

383

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

384

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

533

di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x100000);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

534

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

539

di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x200000);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

540

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

569

di->regs = NULL;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

61

vuint32 *regs, *regs2; /* kernel's pointer to memory mapped registers */

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

625

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, vuint32 *regs2, shared_info *si) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

645

vuint32 *regs, *regs2;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

652

regs = di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

656

if (caused_vbi(regs, regs2)) {

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

658

clear_vbi(regs, regs2);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

660

handled = thread_interrupt_work(flags, regs, regs2, si);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

726

disable_vbi(di->regs, di->regs2);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

830

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

841

disable_vbi(regs, regs2);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

920

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

923

enable_vbi(regs, regs2);

src/add-ons/kernel/drivers/graphics/neomagic/driver.c

925

disable_vbi(regs, regs2);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1033

disable_vbi_all(di->regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1144

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1157

disable_vbi_all(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1265

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1268

enable_vbi_crtc1(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1270

disable_vbi_crtc1(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1274

enable_vbi_crtc2(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

1276

disable_vbi_crtc2(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

425

caused_vbi_crtc1(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

433

clear_vbi_crtc1(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

440

enable_vbi_crtc1(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

452

disable_vbi_crtc1(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

463

caused_vbi_crtc2(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

471

clear_vbi_crtc2(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

478

enable_vbi_crtc2(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

490

disable_vbi_crtc2(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

506

disable_vbi_all(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

52

vuint32 *regs; /* kernel's pointer to memory mapped registers */

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

583

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

584

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

752

di->regs = NULL;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

822

thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si)

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

844

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

850

regs = di->regs;

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

857

if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

859

clear_vbi_crtc1(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

860

clear_vbi_crtc2(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

862

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

865

if (caused_vbi_crtc1(regs)) {

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

867

clear_vbi_crtc1(regs);

src/add-ons/kernel/drivers/graphics/nvidia/driver.c

869

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

130

if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

147

INREG( di->regs, RADEON_RBBM_STATUS ),

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

148

INREG( di->regs, RADEON_CP_STAT ),

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

149

INREG( di->regs, RADEON_AIC_TLB_ADDR ),

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

150

INREG( di->regs, RADEON_AIC_TLB_DATA ));

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

167

int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

186

OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL,

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

192

if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

208

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

217

clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

218

RADEONPllErrataAfterIndex( regs, di->asic ); // drm has no errata here!

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

219

mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

222

Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl |

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

231

host_path_cntl = INREG( regs, RADEON_HOST_PATH_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

232

rbbm_soft_reset = INREG( regs, RADEON_RBBM_SOFT_RESET );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

234

OUTREG( regs, RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

242

INREG( regs, RADEON_RBBM_SOFT_RESET);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

243

OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset &

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

251

INREG( regs, RADEON_RBBM_SOFT_RESET);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

253

OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

254

INREG( regs, RADEON_HOST_PATH_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

255

OUTREG( regs, RADEON_HOST_PATH_CNTL, host_path_cntl );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

257

Radeon_OUTPLL( regs, di->asic, RADEON_MCLK_CNTL, mclk_cntl );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

258

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

260

OUTREG( regs, RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

265

cur_read_ptr = INREG( regs, RADEON_CP_RB_RPTR );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

266

OUTREG( regs, RADEON_CP_RB_WPTR, cur_read_ptr );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

312

OUTREG( di->regs, RADEON_CP_ME_RAM_ADDR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

315

OUTREG( di->regs, RADEON_CP_ME_RAM_DATAH, microcode[i][1] );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

316

OUTREG( di->regs, RADEON_CP_ME_RAM_DATAL, microcode[i][0] );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

326

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

351

OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

356

OUTREG( regs, RADEON_CP_RB_CNTL, radeon_log2( cp->ring.size / 2 ));

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

362

OUTREG( regs, RADEON_CP_RB_WPTR_DELAY, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

367

OUTREG( regs, RADEON_CP_RB_RPTR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

368

OUTREG( regs, RADEON_CP_RB_WPTR, 0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

377

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

383

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

385

INREG( regs, RADEON_CP_CSQ_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

393

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

415

OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

422

OUTREG( regs, RADEON_SCRATCH_ADDR, cp->feedback.scratch_vm_start );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

423

OUTREG( regs, RADEON_SCRATCH_UMSK, 0x3f );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

434

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

437

OUTREG( regs, RADEON_SCRATCH_UMSK, 0x0 );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

521

OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

522

INREG( di->regs, RADEON_CP_CSQ_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

545

OUTREG( di->regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

548

OUTREGP( di->regs, RADEON_BUS_CNTL, 0, ~RADEON_BUS_MASTER_DIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

555

OUTREG( di->regs, RADEON_ISYNC_CNTL,

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

561

SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

582

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

588

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

590

INREG( regs, RADEON_CP_CSQ_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

642

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

649

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

657

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

660

tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

664

Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

666

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

675

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

677

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

679

Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

681

tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

687

Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

689

tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

693

Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

695

tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

710

Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

712

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

736

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

741

tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

745

Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

750

tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

753

Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

760

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

762

Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

766

tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

775

Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

778

tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

781

Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

787

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

788

if ((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > RADEON_CFG_ATI_REV_A13) {

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

796

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

801

tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

808

Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

810

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

820

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

822

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

825

Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

827

tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

830

Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

832

tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

846

Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

848

tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_MISC);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

851

Radeon_OUTPLL(regs, asic, RADEON_MCLK_MISC, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

853

tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

868

tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

870

if (INREG( regs, RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

880

Radeon_OUTPLL(regs, asic, RADEON_MCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

882

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

885

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

888

tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

892

Radeon_OUTPLL(regs, asic, R300_SCLK_CNTL2, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

895

tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

903

Radeon_OUTPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

906

tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PIN_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

908

Radeon_OUTPLL(regs, asic, RADEON_CLK_PIN_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

914

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

920

((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

923

((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

930

Radeon_OUTPLL(regs, asic, RADEON_SCLK_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

935

tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

941

((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

946

Radeon_OUTPLL(regs, asic, RADEON_SCLK_MORE_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

953

((INREG( regs, RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

956

tmp = Radeon_INPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

958

Radeon_OUTPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

963

tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

972

Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

975

tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c

979

Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

170

OUTREG( di->regs, RADEON_DMA_VID_TABLE_ADDR, di->si->memory[mt_local].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

176

while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

39

OUTREGP( di->regs, RADEON_GEN_INT_CNTL, RADEON_VIDDMA_MASK, ~RADEON_VIDDMA_MASK );

src/add-ons/kernel/drivers/graphics/radeon/DMA.c

41

OUTREG( di->regs, RADEON_GEN_INT_STATUS, RADEON_VIDDMA_AK );

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

283

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

294

OUTREG( regs, RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

296

INREG( regs, RADEON_CP_CSQ_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

299

OUTREGP( regs, RADEON_BUS_CNTL, RADEON_BUS_MASTER_DIS, ~RADEON_BUS_MASTER_DIS );

src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c

301

OUTREGP( regs, RADEON_AIC_CNTL, 0, ~RADEON_PCIGART_TRANSLATE_EN );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

629

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

632

((INREG( regs, RADEON_FP_VERT_STRETCH ) & RADEON_VERT_PANEL_SIZE)

src/add-ons/kernel/drivers/graphics/radeon/bios.c

636

(((INREG( regs, RADEON_FP_HORZ_STRETCH ) & RADEON_HORZ_PANEL_SIZE)

src/add-ons/kernel/drivers/graphics/radeon/bios.c

647

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

652

r = INREG( regs, RADEON_FP_CRTC_H_TOTAL_DISP );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

660

r = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

672

r = INREG( regs, RADEON_FP_CRTC_V_TOTAL_DISP );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

679

r = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

685

r = INREG( regs, RADEON_CRTC_H_TOTAL_DISP );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

692

r = INREG( regs, RADEON_CRTC_H_SYNC_STRT_WID );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

702

r = INREG( regs, RADEON_CRTC_V_TOTAL_DISP );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

709

r = INREG( regs, RADEON_CRTC_V_SYNC_STRT_WID );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

885

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

888

uint32 aper_size = INREG( regs, RADEON_CONFIG_APER_SIZE );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

896

OUTREGP( regs, RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,

src/add-ons/kernel/drivers/graphics/radeon/bios.c

914

if (INREG( regs, RADEON_HOST_PATH_CNTL ) & RADEON_HDP_APER_CNTL )

src/add-ons/kernel/drivers/graphics/radeon/bios.c

924

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

930

tom = INREG( regs, RADEON_NB_TOM );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

932

OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size * 1024);

src/add-ons/kernel/drivers/graphics/radeon/bios.c

934

di->local_mem_size = INREG( regs, RADEON_CONFIG_MEMSIZE ) & RADEON_CONFIG_MEMSIZE_MASK;

src/add-ons/kernel/drivers/graphics/radeon/bios.c

940

OUTREG( regs, RADEON_CONFIG_MEMSIZE, di->local_mem_size);

src/add-ons/kernel/drivers/graphics/radeon/bios.c

965

tmp = INREG( regs, RADEON_MEM_CNTL );

src/add-ons/kernel/drivers/graphics/radeon/bios.c

990

uint32 mem_type = INREG( regs, RADEON_MEM_SDRAM_MODE_REG ) & RADEON_MEM_CFG_TYPE_MASK;

src/add-ons/kernel/drivers/graphics/radeon/init.c

313

di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 );

src/add-ons/kernel/drivers/graphics/radeon/init.c

316

si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/init.c

317

si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/init.c

323

INREG( di->regs, RADEON_LVDS_GEN_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

325

INREG( di->regs, RADEON_LVDS_PLL_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

327

INREG( di->regs, RADEON_TMDS_PLL_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

329

INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

331

INREG( di->regs, RADEON_FP_GEN_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

333

INREG( di->regs, RADEON_FP2_GEN_CNTL ));

src/add-ons/kernel/drivers/graphics/radeon/init.c

335

INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi

src/add-ons/kernel/drivers/graphics/radeon/init.c

40

int regs = 2;

src/add-ons/kernel/drivers/graphics/radeon/init.c

443

OUTREG( di->regs, RADEON_DAC_CNTL2, di->dac2_cntl );

src/add-ons/kernel/drivers/graphics/radeon/init.c

65

di->pcii.u.h0.base_registers[regs],

src/add-ons/kernel/drivers/graphics/radeon/init.c

66

di->pcii.u.h0.base_registers[regs] + di->pcii.u.h0.base_register_sizes[regs] - 1 );

src/add-ons/kernel/drivers/graphics/radeon/init.c

74

di->pcii.u.h0.base_registers[regs],

src/add-ons/kernel/drivers/graphics/radeon/init.c

75

di->pcii.u.h0.base_register_sizes[regs],

src/add-ons/kernel/drivers/graphics/radeon/init.c

80

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/radeon/irq.c

106

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

110

full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

111

int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

116

handled = Radeon_ThreadInterruptWork(regs, di, int_status);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

119

OUTREG(regs, RADEON_GEN_INT_STATUS, int_status);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

128

cap_status = INREG(regs, RADEON_CAP_INT_STATUS);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

129

cap_status &= INREG(regs, RADEON_CAP_INT_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

134

cap_handled = Radeon_HandleCaptureInterrupt(regs, di, cap_status);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

154

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/irq.c

171

result = Radeon_ThreadInterruptWork(regs, di,

src/add-ons/kernel/drivers/graphics/radeon/irq.c

21

OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);

src/add-ons/kernel/drivers/graphics/radeon/irq.c

30

Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status)

src/add-ons/kernel/drivers/graphics/radeon/irq.c

71

Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status)

src/add-ons/kernel/drivers/graphics/radeon/irq.c

93

OUTREG(regs, RADEON_CAP_INT_STATUS, cap_status);

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

119

tom = INREG( di->regs, RADEON_NB_TOM );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

140

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

159

OUTREGP( regs, RADEON_AIC_CNTL, RADEON_PCIGART_TRANSLATE_EN,

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

163

OUTREG( regs, RADEON_AIC_PT_BASE, di->pci_gart.GATT.phys );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

167

OUTREG( regs, RADEON_AIC_LO_ADDR, si->memory[mt_PCI].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

168

OUTREG( regs, RADEON_AIC_HI_ADDR, si->memory[mt_PCI].virtual_addr_start +

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

172

OUTREG( regs, RADEON_MC_AGP_LOCATION, 0xffffffc0 /* EK magic numbers from X.org

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

177

OUTREG( regs, RADEON_AGP_COMMAND, 0 );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

182

OUTREG( regs, RADEON_MC_FB_LOCATION,

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

188

OUTREG( regs, RADEON_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

189

OUTREG( regs, RADEON_CRTC2_DISPLAY_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

190

OUTREG( regs, RADEON_OV0_BASE_ADDRESS, si->memory[mt_local].virtual_addr_start );

src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c

42

uint32 aper0 = INREG( di->regs, RADEON_CONFIG_APER_0_BASE );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

16

void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic )

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

24

INREG( regs, RADEON_CLOCK_CNTL_DATA);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

25

INREG( regs, RADEON_CRTC_GEN_CNTL);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

28

void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic )

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

50

save = INREG( regs, RADEON_CLOCK_CNTL_INDEX );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

52

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

53

tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

54

OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

59

uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr )

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

63

OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, addr & 0x3f );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

64

RADEONPllErrataAfterIndex(regs, asic);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

65

res = INREG( regs, RADEON_CLOCK_CNTL_DATA );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

66

RADEONPllErrataAfterData(regs, asic);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

71

void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val )

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

75

OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f ) |

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

77

RADEONPllErrataAfterIndex(regs, asic);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

78

OUTREG( regs, RADEON_CLOCK_CNTL_DATA, val );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

79

RADEONPllErrataAfterData(regs, asic);

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

84

void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr,

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

87

uint32 tmp = Radeon_INPLL( regs, asic, addr );

src/add-ons/kernel/drivers/graphics/radeon/pll_access.c

90

Radeon_OUTPLL( regs, asic, addr, tmp );

src/add-ons/kernel/drivers/graphics/radeon/radeon_driver.h

103

vuint8 *regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

114

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x3000);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

127

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

128

INREG( regs, RADEON_VIPH_TIMEOUT_STAT) &

src/add-ons/kernel/drivers/graphics/radeon/vip.c

135

INREG( regs, RADEON_VIPH_REG_DATA);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

144

tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

145

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

151

*buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

154

*(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

157

*(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

166

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

167

(INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

193

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

196

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

203

OUTREG( regs, RADEON_VIPH_REG_DATA, data );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

231

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

240

OUTREG( regs, RADEON_VIPH_REG_ADDR,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

258

OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

297

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

310

OUTREG( regs, RADEON_VIPH_CONTROL, 4 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

312

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

314

OUTREG( regs, RADEON_VIPH_DV_LAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

32

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

320

OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

321

OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

323

OUTREG( regs, RADEON_VIPH_CONTROL, 9 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

325

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |

src/add-ons/kernel/drivers/graphics/radeon/vip.c

327

OUTREG( regs, RADEON_VIPH_DV_LAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

333

OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

334

OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));

src/add-ons/kernel/drivers/graphics/radeon/vip.c

349

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

355

timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

358

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

36

OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

360

return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

362

return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

367

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

370

timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

373

OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);

src/add-ons/kernel/drivers/graphics/radeon/vip.c

374

return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

376

return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK ;

src/add-ons/kernel/drivers/graphics/radeon/vip.c

43

OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

48

INREG( regs, RADEON_VIPH_REG_DATA );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

57

OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

62

*data = INREG( regs, RADEON_VIPH_REG_DATA );

src/add-ons/kernel/drivers/graphics/radeon/vip.c

72

OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,

src/add-ons/kernel/drivers/graphics/radeon/vip.c

99

vuint8 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

249

(void**)(&(di.regs)));

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

307

di.regs = NULL;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

515

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

516

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

517

regs.ebx = 0; // 0 = report DDC service

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

518

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

519

regs.es = 0;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

520

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

522

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

526

if (regs.eax != 0x4f)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

530

if ((regs.ebx & 3) == 0)

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

542

regs.eax = 0x4f15;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

543

regs.ebx = 1; // 1 = read EDID

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

544

regs.ecx = 0;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

545

regs.edx = 0;

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

546

regs.es = ADDRESS_SEGMENT(edid);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

547

regs.edi = ADDRESS_OFFSET(edid);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

549

status = biosModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

551

if (regs.eax != 0x4f) {

src/add-ons/kernel/drivers/graphics/s3/driver.cpp

99

vuint8* regs; // pointer to memory mapped registers

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

146

static int caused_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

153

static void clear_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

158

static void enable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

168

static void disable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

383

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

384

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

521

di->regs = NULL;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

577

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

58

vuint32 *regs; /* kernel's pointer to memory mapped registers */

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

597

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

604

regs = di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

607

if (caused_vbi(regs)) {

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

609

clear_vbi(regs);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

611

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

628

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

713

regs = di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

716

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

804

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

814

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

891

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

893

enable_vbi(regs);

src/add-ons/kernel/drivers/graphics/skeleton/driver.c

895

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

136

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

137

regs.eax = 0x4f01;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

138

regs.ecx = mode;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

139

regs.es = physicalAddress >> 4;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

140

regs.edi = physicalAddress - (regs.es << 4);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

142

status_t status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

149

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

151

"0x%04" B_PRIx32 "\n", mode, regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

163

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

164

regs.eax = 0x4f02;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

165

regs.ebx = (mode & SET_MODE_MASK) | SET_MODE_LINEAR_BUFFER;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

167

status_t status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

174

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

176

"\n", mode, regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

206

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

207

regs.eax = 0x4f10;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

208

regs.ebx = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

209

regs.esi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

210

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

212

status_t status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

219

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

221

"0x%04" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

225

vbeMode = regs.ebx >> 8;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

236

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

237

regs.eax = 0x4f08;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

238

regs.ebx = (bits << 8) | 1;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

240

status_t status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

247

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

249

"0x%04" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

253

info.bits_per_gun = regs.ebx >> 8;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

268

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

269

regs.eax = 0x4f00;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

270

regs.es = physicalAddress >> 4;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

271

regs.edi = physicalAddress - (regs.es << 4);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

273

status_t status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

280

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

282

"0x%04" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

542

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

543

regs.eax = 0x4f10;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

544

regs.ebx = 2;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

545

regs.esi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

546

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

548

status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

555

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

557

"0x%" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

562

mode = vbe_to_system_dpms(regs.ebx >> 8);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

592

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

593

regs.eax = 0x4f10;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

594

regs.ebx = (vbeMode << 8) | 1;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

595

regs.esi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

596

regs.edi = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

598

status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

605

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

607

"0x%04" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

622

bios_regs regs = {};

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

659

regs.eax = 0x4f09;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

660

regs.ebx = 0;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

661

regs.ecx = count;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

662

regs.edx = first;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

663

regs.es = physicalAddress >> 4;

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

664

regs.edi = physicalAddress - (regs.es << 4);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

666

status = sBIOSModule->interrupt(state, 0x10, &regs);

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

673

if ((regs.eax & 0xffff) != 0x4f) {

src/add-ons/kernel/drivers/graphics/vesa/vesa.cpp

675

"0x%04" B_PRIx32 "\n", regs.eax & 0xffff);

src/add-ons/kernel/drivers/graphics/via/driver.c

151

static int caused_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/via/driver.c

158

static void clear_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/via/driver.c

163

static void enable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/via/driver.c

173

static void disable_vbi(vuint32 * regs)

src/add-ons/kernel/drivers/graphics/via/driver.c

392

(void **)&(di->regs));

src/add-ons/kernel/drivers/graphics/via/driver.c

393

si->clone_bugfix_regs = (uint32 *) di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

530

di->regs = NULL;

src/add-ons/kernel/drivers/graphics/via/driver.c

58

vuint32 *regs; /* kernel's pointer to memory mapped registers */

src/add-ons/kernel/drivers/graphics/via/driver.c

586

static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) {

src/add-ons/kernel/drivers/graphics/via/driver.c

606

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

613

regs = di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

616

if (caused_vbi(regs)) {

src/add-ons/kernel/drivers/graphics/via/driver.c

618

clear_vbi(regs);

src/add-ons/kernel/drivers/graphics/via/driver.c

620

handled = thread_interrupt_work(flags, regs, si);

src/add-ons/kernel/drivers/graphics/via/driver.c

637

vuint32 *regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

701

regs = di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

704

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/via/driver.c

792

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

802

disable_vbi(regs);

src/add-ons/kernel/drivers/graphics/via/driver.c

879

vuint32 *regs = di->regs;

src/add-ons/kernel/drivers/graphics/via/driver.c

881

enable_vbi(regs);

src/add-ons/kernel/drivers/graphics/via/driver.c

883

disable_vbi(regs);

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c

1936

rge_write_mac_ocp(sc, bps->regs[i],

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c

1955

rge_write_mac_ocp(sc, bps->regs[i],

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c

1960

rge_write_mac_ocp(sc, bps->regs[i],

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c

1978

rge_write_mac_ocp(sc, bps->regs[i],

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rge.c

1983

rge_write_mac_ocp(sc, bps->regs[i],

src/add-ons/kernel/drivers/network/ether/rtl8125/dev/pci/if_rgereg.h

666

const uint16_t *regs;

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

951

ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

958

uint32_t r = regs[i].start;

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

959

uint32_t e = regs[i].end;

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

973

ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space)

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

976

OS_REG_WRITE(ah, regs->addr, regs->value);

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c

977

regs++, space -= sizeof(HAL_REGWRITE);

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

615

ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs,

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

625

if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) ==

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

630

if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) ==

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

636

if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state)

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

640

if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state)

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

644

if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state)

src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/ar5416_misc.c

648

if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state)

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

106

#define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

107

#define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

109

#define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

110

#define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1262

struct rf_saveregs regs;

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1271

bzero(&regs, sizeof(regs));

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1274

SAVE_PHY_REG(mac, &regs, 429);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1275

SAVE_PHY_REG(mac, &regs, 802);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1277

PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1278

PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1285

SAVE_PHY_REG(mac, &regs, 15);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1286

SAVE_PHY_REG(mac, &regs, 2a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1287

SAVE_PHY_REG(mac, &regs, 35);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1288

SAVE_PHY_REG(mac, &regs, 60);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1289

SAVE_RF_REG(mac, &regs, 43);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1290

SAVE_RF_REG(mac, &regs, 7a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1291

SAVE_RF_REG(mac, &regs, 52);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1293

SAVE_PHY_REG(mac, &regs, 811);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1294

SAVE_PHY_REG(mac, &regs, 812);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1295

SAVE_PHY_REG(mac, &regs, 814);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1296

SAVE_PHY_REG(mac, &regs, 815);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1303

PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1304

PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1315

PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1316

RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1321

PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1322

PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1334

devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1362

RESTORE_PHY_REG(mac, &regs, 15);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1363

RESTORE_PHY_REG(mac, &regs, 2a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1364

RESTORE_PHY_REG(mac, &regs, 35);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1365

RESTORE_PHY_REG(mac, &regs, 60);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1367

RESTORE_RF_REG(mac, &regs, 43);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1368

RESTORE_RF_REG(mac, &regs, 7a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1370

regs.rf_52 &= 0xf0;

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1371

regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1372

RF_WRITE(mac, 0x52, regs.rf_52);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1377

RESTORE_PHY_REG(mac, &regs, 811);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1378

RESTORE_PHY_REG(mac, &regs, 812);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1379

RESTORE_PHY_REG(mac, &regs, 814);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1380

RESTORE_PHY_REG(mac, &regs, 815);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1381

RESTORE_PHY_REG(mac, &regs, 429);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

1382

RESTORE_PHY_REG(mac, &regs, 802);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2573

struct rf_saveregs regs;

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2580

bzero(&regs, sizeof(regs));

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2586

SAVE_PHY_REG(mac, &regs, 15);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2589

SAVE_PHY_REG(mac, &regs, 0a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2590

SAVE_PHY_REG(mac, &regs, 2a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2591

SAVE_PHY_REG(mac, &regs, 35);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2592

SAVE_PHY_REG(mac, &regs, 03);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2593

SAVE_PHY_REG(mac, &regs, 01);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2594

SAVE_PHY_REG(mac, &regs, 30);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2596

SAVE_RF_REG(mac, &regs, 43);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2597

SAVE_RF_REG(mac, &regs, 7a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2601

SAVE_RF_REG(mac, &regs, 52);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2602

regs.rf_52 &= 0xf0;

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2606

PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2607

RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2670

RESTORE_PHY_REG(mac, &regs, 0a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2671

RESTORE_PHY_REG(mac, &regs, 2a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2672

RESTORE_PHY_REG(mac, &regs, 35);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2673

RESTORE_PHY_REG(mac, &regs, 03);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2674

RESTORE_PHY_REG(mac, &regs, 01);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2675

RESTORE_PHY_REG(mac, &regs, 30);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2677

RESTORE_RF_REG(mac, &regs, 43);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2678

RESTORE_RF_REG(mac, &regs, 7a);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2680

RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52);

src/add-ons/kernel/drivers/network/wlan/broadcom43xx/dev/bwi/bwirf.c

2684

RESTORE_PHY_REG(mac, &regs, 15);

src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c

2271

mwl_hal_getregdump(struct mwl_hal_priv *mh, const MWL_DIAG_REGRANGE *regs,

src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c

2278

u_int r = regs[i].start;

src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/mwlhal.c

2279

u_int e = regs[i].end;

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

128

const uint16_t regs[], int size)

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

136

vals[i] = rtwn_bb_read(sc, regs[i]);

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

141

const uint16_t regs[], int size)

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

149

rtwn_bb_write(sc, regs[i], vals[i]);

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

154

const uint8_t regs[], int size)

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

163

vals[c * size + i] = rtwn_rf_read(sc, c, regs[i]);

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

168

const uint8_t regs[], int size)

src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/rtl8812a/r12a_calib.c

177

rtwn_rf_write(sc, c, regs[i], vals[c * size + i]);

src/add-ons/kernel/drivers/network/wlan/zydwifi1211/dev/usb/wlan/if_zyd.c

852

uint16_t regs[2];

src/add-ons/kernel/drivers/network/wlan/zydwifi1211/dev/usb/wlan/if_zyd.c

855

regs[0] = htole16(ZYD_REG32_HI(reg));

src/add-ons/kernel/drivers/network/wlan/zydwifi1211/dev/usb/wlan/if_zyd.c

856

regs[1] = htole16(ZYD_REG32_LO(reg));

src/add-ons/kernel/drivers/network/wlan/zydwifi1211/dev/usb/wlan/if_zyd.c

857

error = zyd_cmd(sc, ZYD_CMD_IORD, regs, sizeof(regs), tmp, sizeof(tmp),

src/add-ons/kernel/drivers/nvmm/nvmm_haiku.cpp

48

descriptors->eax = info.regs.eax;

src/add-ons/kernel/drivers/nvmm/nvmm_haiku.cpp

49

descriptors->ebx = info.regs.ebx;

src/add-ons/kernel/drivers/nvmm/nvmm_haiku.cpp

50

descriptors->ecx = info.regs.ecx;

src/add-ons/kernel/drivers/nvmm/nvmm_haiku.cpp

51

descriptors->edx = info.regs.edx;

src/add-ons/kernel/drivers/timer/hpet.h

23

#define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)

src/add-ons/kernel/drivers/timer/hpet.h

24

#define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)

src/add-ons/kernel/drivers/timer/hpet.h

25

#define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)

src/add-ons/kernel/drivers/timer/hpet.h

26

#define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)

src/add-ons/kernel/drivers/timer/hpet.h

27

#define HPET_GET_VENDOR_ID(regs) (((regs)->capabilities & HPET_CAP_MASK_VENDOR_ID) >> 16)

src/add-ons/kernel/drivers/timer/hpet.h

28

#define HPET_GET_PERIOD(regs) (((regs)->capabilities & HPET_CAP_MASK_PERIOD) >> 32)

src/add-ons/kernel/drivers/timer/hpet.h

35

#define HPET_IS_ENABLED(regs) ((regs)->config & HPET_CONF_MASK_ENABLED)

src/add-ons/kernel/drivers/timer/hpet.h

36

#define HPET_IS_LEGACY(regs) (((regs)->config & HPET_CONF_MASK_LEGACY) >> 1)

src/add-ons/kernel/generic/bios/bios.cpp

279

bios_interrupt(bios_state* state, uint8 vector, bios_regs* regs)

src/add-ons/kernel/generic/bios/bios.cpp

299

M.x86.R_EAX = regs->eax;

src/add-ons/kernel/generic/bios/bios.cpp

300

M.x86.R_EBX = regs->ebx;

src/add-ons/kernel/generic/bios/bios.cpp

301

M.x86.R_ECX = regs->ecx;

src/add-ons/kernel/generic/bios/bios.cpp

302

M.x86.R_EDX = regs->edx;

src/add-ons/kernel/generic/bios/bios.cpp

303

M.x86.R_EDI = regs->edi;

src/add-ons/kernel/generic/bios/bios.cpp

304

M.x86.R_ESI = regs->esi;

src/add-ons/kernel/generic/bios/bios.cpp

305

M.x86.R_EBP = regs->ebp;

src/add-ons/kernel/generic/bios/bios.cpp

306

M.x86.R_EFLG = regs->eflags | X86_EFLAGS_INTERRUPT | X86_EFLAGS_RESERVED1;

src/add-ons/kernel/generic/bios/bios.cpp

309

M.x86.R_DS = regs->ds;

src/add-ons/kernel/generic/bios/bios.cpp

310

M.x86.R_ES = regs->es;

src/add-ons/kernel/generic/bios/bios.cpp

311

M.x86.R_FS = regs->fs;

src/add-ons/kernel/generic/bios/bios.cpp

312

M.x86.R_GS = regs->gs;

src/add-ons/kernel/generic/bios/bios.cpp

323

regs->eax = M.x86.R_EAX;

src/add-ons/kernel/generic/bios/bios.cpp

324

regs->ebx = M.x86.R_EBX;

src/add-ons/kernel/generic/bios/bios.cpp

325

regs->ecx = M.x86.R_ECX;

src/add-ons/kernel/generic/bios/bios.cpp

326

regs->edx = M.x86.R_EDX;

src/add-ons/kernel/generic/bios/bios.cpp

327

regs->edi = M.x86.R_EDI;

src/add-ons/kernel/generic/bios/bios.cpp

328

regs->esi = M.x86.R_ESI;

src/add-ons/kernel/generic/bios/bios.cpp

329

regs->ebp = M.x86.R_EBP;

src/add-ons/kernel/generic/bios/bios.cpp

330

regs->eflags = M.x86.R_EFLG;

src/add-ons/kernel/generic/bios/bios.cpp

331

regs->ds = M.x86.R_DS;

src/add-ons/kernel/generic/bios/bios.cpp

332

regs->es = M.x86.R_ES;

src/add-ons/kernel/generic/bios/bios.cpp

333

regs->fs = M.x86.R_FS;

src/add-ons/kernel/generic/bios/bios.cpp

334

regs->gs = M.x86.R_GS;

src/add-ons/kernel/power/cpuidle/x86_cstates/x86_cstates.cpp

148

uint32 minMonitorLineSize = cpuid.regs.eax & 0xffff;

src/add-ons/kernel/power/cpuidle/x86_cstates/x86_cstates.cpp

150

uint32 mwaitSubStates = cpuid.regs.edx;

src/add-ons/kernel/power/cpuidle/x86_cstates/x86_cstates.cpp

162

if ((cpuid.regs.ecx & CPUID_MWAIT_ECX_SUPPORT) != CPUID_MWAIT_ECX_SUPPORT) {

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

754

uint8 regs[SN9C102_REG_COUNT];

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

758

err = ReadReg(0, regs, SN9C102_REG_COUNT);

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

762

regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7]);

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

764

regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15]);

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

766

regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23]);

src/add-ons/media/media-add-ons/usb_webcam/addons/sonix/SonixCamDevice.cpp

768

regs[24], regs[25], regs[26], regs[27], regs[28], regs[29], regs[30], regs[31]);

src/bin/keymap/Keymap.cpp

1048

Keymap::_ComputeChars(const char* buffer, struct re_registers& regs, int i,

src/bin/keymap/Keymap.cpp

1055

if (strncmp(buffer + regs.start[i], "''", regs.end[i] - regs.start[i])

src/bin/keymap/Keymap.cpp

1058

} else if (sscanf(buffer + regs.start[i], "'%s'", current) > 0) {

src/bin/keymap/Keymap.cpp

1064

} else if (sscanf(buffer + regs.start[i], "0x%s", hexChars) > 0) {

src/bin/keymap/Keymap.cpp

1076

Keymap::_ComputeTables(const char* buffer, struct re_registers& regs,

src/bin/keymap/Keymap.cpp

1080

int32 length = regs.end[i] - regs.start[i];

src/bin/keymap/Keymap.cpp

1084

const char* start = buffer + regs.start[i];

src/bin/keymap/Keymap.cpp

362

struct re_registers regs;

src/bin/keymap/Keymap.cpp

364

if (re_search(&versionBuf, buffer, length, 0, length, &regs) >= 0) {

src/bin/keymap/Keymap.cpp

365

sscanf(buffer + regs.start[1], "%" B_SCNu32, &fKeys.version);

src/bin/keymap/Keymap.cpp

366

} else if (re_search(&capslockBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

368

sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.caps_key);

src/bin/keymap/Keymap.cpp

369

} else if (re_search(&scrolllockBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

371

sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.scroll_key);

src/bin/keymap/Keymap.cpp

372

} else if (re_search(&numlockBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

374

sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.num_key);

src/bin/keymap/Keymap.cpp

375

} else if (re_search(&lshiftBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

377

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

379

} else if (re_search(&rshiftBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

381

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

383

} else if (re_search(&lcommandBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

385

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

387

} else if (re_search(&rcommandBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

389

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

391

} else if (re_search(&lcontrolBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

393

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

395

} else if (re_search(&rcontrolBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

397

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

399

} else if (re_search(&loptionBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

401

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

403

} else if (re_search(&roptionBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

405

sscanf(buffer + regs.start[1], "0x%" B_SCNx32,

src/bin/keymap/Keymap.cpp

407

} else if (re_search(&menuBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

409

sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &fKeys.menu_key);

src/bin/keymap/Keymap.cpp

410

} else if (re_search(&locksettingsBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

414

const char* start = buffer + regs.start[i];

src/bin/keymap/Keymap.cpp

415

length = regs.end[i] - regs.start[i];

src/bin/keymap/Keymap.cpp

426

} else if (re_search(&keyBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

429

if (sscanf(buffer + regs.start[1], "0x%" B_SCNx32, &keyCode) > 0) {

src/bin/keymap/Keymap.cpp

432

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

435

} else if (re_search(&acuteBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

439

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

441

} else if (re_search(&graveBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

445

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

447

} else if (re_search(&circumflexBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

451

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

453

} else if (re_search(&diaeresisBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

457

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

459

} else if (re_search(&tildeBuf, buffer, length, 0, length, &regs) >= 0) {

src/bin/keymap/Keymap.cpp

462

_ComputeChars(buffer, regs, i, offset);

src/bin/keymap/Keymap.cpp

464

} else if (re_search(&acutetabBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

466

_ComputeTables(buffer, regs, fKeys.acute_tables);

src/bin/keymap/Keymap.cpp

467

} else if (re_search(&gravetabBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

469

_ComputeTables(buffer, regs, fKeys.grave_tables);

src/bin/keymap/Keymap.cpp

470

} else if (re_search(&circumflextabBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

472

_ComputeTables(buffer, regs, fKeys.circumflex_tables);

src/bin/keymap/Keymap.cpp

473

} else if (re_search(&diaeresistabBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

475

_ComputeTables(buffer, regs, fKeys.dieresis_tables);

src/bin/keymap/Keymap.cpp

476

} else if (re_search(&tildetabBuf, buffer, length, 0, length, &regs)

src/bin/keymap/Keymap.cpp

478

_ComputeTables(buffer, regs, fKeys.tilde_tables);

src/bin/keymap/Keymap.h

55

struct re_registers& regs, int i,

src/bin/keymap/Keymap.h

58

struct re_registers& regs, uint32& table);

src/bin/sysinfo.cpp

250

if ((info->regs.eax & 0x80000000) == 0) {

src/bin/sysinfo.cpp

258

if ((info->regs.ebx & 0x80000000) == 0) {

src/bin/sysinfo.cpp

267

if ((info->regs.edx & 0x80000000) == 0) {

src/bin/sysinfo.cpp

276

if ((info->regs.ecx & 0x80000000) == 0) {

src/bin/sysinfo.cpp

389

if (info.regs.eax)

src/bin/sysinfo.cpp

390

print_TLB(info.regs.eax, info.regs.ebx ? "2M/4M-byte" : NULL);

src/bin/sysinfo.cpp

391

if (info.regs.ebx)

src/bin/sysinfo.cpp

392

print_TLB(info.regs.ebx, info.regs.eax ? "4K-byte" : NULL);

src/bin/sysinfo.cpp

394

print_level1_cache(info.regs.ecx, "L1 inst cache");

src/bin/sysinfo.cpp

395

print_level1_cache(info.regs.edx, "L1 data cache");

src/bin/sysinfo.cpp

398

print_level2_cache(info.regs.ecx, "L2 cache");

src/bin/sysinfo.cpp

413

uint32 type = info.regs.eax & 0xf;

src/bin/sysinfo.cpp

414

uint32 level = (info.regs.eax & 0x70) >> 4;

src/bin/sysinfo.cpp

415

bool isFullyAssoc = info.regs.eax & 0x100;

src/bin/sysinfo.cpp

417

uint32 lineSize = (info.regs.ebx & 0xfff) + 1;

src/bin/sysinfo.cpp

418

uint32 linesPerTag = ((info.regs.ebx & 0x3ff000) >> 12) + 1;

src/bin/sysinfo.cpp

419

uint32 ways = ((info.regs.ebx & 0xffc00000) >> 22) + 1;

src/bin/sysinfo.cpp

438

uint32 sets = info.regs.ecx;

src/bin/sysinfo.cpp

579

memcpy(name, &nameInfo.regs.eax, 4);

src/bin/sysinfo.cpp

580

memcpy(name + 4, &nameInfo.regs.ebx, 4);

src/bin/sysinfo.cpp

581

memcpy(name + 8, &nameInfo.regs.ecx, 4);

src/bin/sysinfo.cpp

582

memcpy(name + 12, &nameInfo.regs.edx, 4);

src/bin/sysinfo.cpp

634

print_features(kAMDExtFeatures, cpuInfo.regs.edx);

src/bin/sysinfo.cpp

641

cpuInfo.regs.edx);

src/bin/sysinfo.cpp

642

print_features(kAMDExtFeaturesPower, cpuInfo.regs.edx);

src/bin/sysinfo.cpp

647

cpuInfo.regs.ebx);

src/bin/sysinfo.cpp

648

print_features(kAMDExtFeaturesTwo, cpuInfo.regs.ebx);

src/bin/sysinfo.cpp

651

print_transmeta_features(cpuInfo.regs.edx);

src/bin/sysinfo.cpp

658

" 0x%08" B_PRIx32 "\n", cpuInfo.regs.ebx, cpuInfo.regs.ecx, cpuInfo.regs.edx);

src/bin/sysinfo.cpp

659

print_features(kLeaf7EBXFeatures, cpuInfo.regs.ebx);

src/bin/sysinfo.cpp

660

print_features(kLeaf7ECXFeatures, cpuInfo.regs.ecx);

src/bin/sysinfo.cpp

661

print_features(kLeaf7EDXFeatures, cpuInfo.regs.edx);

src/bin/sysinfo.cpp

697

cpuInfo.regs.edx >> 16, cpuInfo.regs.edx & 0xffff,

src/bin/sysinfo.cpp

698

cpuInfo.regs.ecx >> 16, cpuInfo.regs.edx & 0xffff);

src/build/libgnuregex/regex.c

2811

re_set_registers (bufp, regs, num_regs, starts, ends)

src/build/libgnuregex/regex.c

2813

struct re_registers *regs;

src/build/libgnuregex/regex.c

2820

regs->num_regs = num_regs;

src/build/libgnuregex/regex.c

2821

regs->start = starts;

src/build/libgnuregex/regex.c

2822

regs->end = ends;

src/build/libgnuregex/regex.c

2827

regs->num_regs = 0;

src/build/libgnuregex/regex.c

2828

regs->start = regs->end = (regoff_t) 0;

src/build/libgnuregex/regex.c

2838

re_search (bufp, string, size, startpos, range, regs)

src/build/libgnuregex/regex.c

2842

struct re_registers *regs;

src/build/libgnuregex/regex.c

2845

regs, size);

src/build/libgnuregex/regex.c

2871

re_search_2 (bufp, string1, size1, string2, size2, startpos, range, regs, stop)

src/build/libgnuregex/regex.c

2877

struct re_registers *regs;

src/build/libgnuregex/regex.c

2962

startpos, regs, stop);

src/build/libgnuregex/regex.c

3130

re_match (bufp, string, size, pos, regs)

src/build/libgnuregex/regex.c

3134

struct re_registers *regs;

src/build/libgnuregex/regex.c

3136

return re_match_2 (bufp, NULL, 0, string, size, pos, regs, size);

src/build/libgnuregex/regex.c

3155

re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop)

src/build/libgnuregex/regex.c

3160

struct re_registers *regs;

src/build/libgnuregex/regex.c

3432

if (regs && !bufp->no_sub)

src/build/libgnuregex/regex.c

3439

regs->num_regs = MAX (RE_NREGS, num_regs + 1);

src/build/libgnuregex/regex.c

3440

regs->start = TALLOC (regs->num_regs, regoff_t);

src/build/libgnuregex/regex.c

3441

regs->end = TALLOC (regs->num_regs, regoff_t);

src/build/libgnuregex/regex.c

3442

if (regs->start == NULL || regs->end == NULL)

src/build/libgnuregex/regex.c

3450

if (regs->num_regs < num_regs + 1)

src/build/libgnuregex/regex.c

3452

regs->num_regs = num_regs + 1;

src/build/libgnuregex/regex.c

3453

RETALLOC (regs->start, regs->num_regs, regoff_t);

src/build/libgnuregex/regex.c

3454

RETALLOC (regs->end, regs->num_regs, regoff_t);

src/build/libgnuregex/regex.c

3455

if (regs->start == NULL || regs->end == NULL)

src/build/libgnuregex/regex.c

3465

if (regs->num_regs > 0)

src/build/libgnuregex/regex.c

3467

regs->start[0] = pos;

src/build/libgnuregex/regex.c

3468

regs->end[0] = (MATCHING_IN_FIRST_STRING ? d - string1

src/build/libgnuregex/regex.c

3474

for (mcnt = 1; mcnt < MIN (num_regs, regs->num_regs); mcnt++)

src/build/libgnuregex/regex.c

3477

regs->start[mcnt] = regs->end[mcnt] = -1;

src/build/libgnuregex/regex.c

3480

regs->start[mcnt] = POINTER_TO_OFFSET (regstart[mcnt]);

src/build/libgnuregex/regex.c

3481

regs->end[mcnt] = POINTER_TO_OFFSET (regend[mcnt]);

src/build/libgnuregex/regex.c

3490

for (mcnt = num_regs; mcnt < regs->num_regs; mcnt++)

src/build/libgnuregex/regex.c

3491

regs->start[mcnt] = regs->end[mcnt] = -1;

src/build/libgnuregex/regex.c

4813

struct re_registers regs;

src/build/libgnuregex/regex.c

4830

regs.num_regs = nmatch;

src/build/libgnuregex/regex.c

4831

regs.start = TALLOC (nmatch, regoff_t);

src/build/libgnuregex/regex.c

4832

regs.end = TALLOC (nmatch, regoff_t);

src/build/libgnuregex/regex.c

4833

if (regs.start == NULL || regs.end == NULL)

src/build/libgnuregex/regex.c

4840

want_reg_info ? &regs : (struct re_registers *) 0);

src/build/libgnuregex/regex.c

4851

pmatch[r].rm_so = regs.start[r];

src/build/libgnuregex/regex.c

4852

pmatch[r].rm_eo = regs.end[r];

src/build/libgnuregex/regex.c

4857

free (regs.start);

src/build/libgnuregex/regex.c

4858

free (regs.end);

src/build/libgnuregex/regex.h

429

int length, int start, int range, struct re_registers *regs));

src/build/libgnuregex/regex.h

437

int start, int range, struct re_registers *regs, int stop));

src/build/libgnuregex/regex.h

444

int length, int start, struct re_registers *regs));

src/build/libgnuregex/regex.h

451

int start, struct re_registers *regs, int stop));

src/build/libgnuregex/regex.h

467

_RE_ARGS ((struct re_pattern_buffer *buffer, struct re_registers *regs,

src/kits/mail/mail_util.cpp

1250

struct re_registers regs;

src/kits/mail/mail_util.cpp

1253

regs.num_regs = gNsub;

src/kits/mail/mail_util.cpp

1254

regs.start = (regoff_t*)malloc(gNsub*sizeof(regoff_t));

src/kits/mail/mail_util.cpp

1255

regs.end = (regoff_t*)malloc(gNsub*sizeof(regoff_t));

src/kits/mail/mail_util.cpp

1258

string.Length(), 0, string.Length(), &regs)) >= 0;) {

src/kits/mail/mail_util.cpp

1264

if (start == regs.start[1])

src/kits/mail/mail_util.cpp

1265

start = regs.start[2];

src/kits/mail/mail_util.cpp

1267

string.Remove(start,regs.end[0]-start);

src/kits/mail/mail_util.cpp

1273

if (regs.end[0] - start <= 1)

src/kits/mail/mail_util.cpp

1277

free(regs.start);

src/kits/mail/mail_util.cpp

1278

free(regs.end);

src/libs/nvmm/driver/nvmm_haiku.cpp

48

descriptors->eax = info.regs.eax;

src/libs/nvmm/driver/nvmm_haiku.cpp

49

descriptors->ebx = info.regs.ebx;

src/libs/nvmm/driver/nvmm_haiku.cpp

50

descriptors->ecx = info.regs.ecx;

src/libs/nvmm/driver/nvmm_haiku.cpp

51

descriptors->edx = info.regs.edx;

src/servers/app/drawing/Painter/Painter.cpp

157

uint32 maxStdFunc = cpuInfo.regs.eax;

src/servers/app/drawing/Painter/Painter.cpp

160

uint32 edx = cpuInfo.regs.edx;

src/system/boot/arch/x86/arch_cpu.cpp

327

&& (info.regs.ecx & IA32_FEATURE_EXT_HYPERVISOR) != 0) {

src/system/boot/arch/x86/arch_cpu.cpp

329

const uint32 maxVMM = info.regs.eax;

src/system/boot/arch/x86/arch_cpu.cpp

334

uint64 clockSpeed = uint64(info.regs.eax) * 1000;

src/system/boot/arch/x86/arch_cpu.cpp

335

gTimeConversionFactor = (uint64(1000) << 32) / info.regs.eax;

src/system/boot/arch/x86/arch_cpu.cpp

348

if (info.regs.eax == 0x31237648) {

src/system/boot/arch/x86/arch_cpu.cpp

352

if ((info.regs.eax & (1 << 11)) != 0) {

src/system/boot/platform/atari_m68k/devices.cpp

224

parameters->cylinders = (((regs.ecx & 0xc0) << 2) | ((regs.ecx >> 8) & 0xff)) + 1;

src/system/boot/platform/atari_m68k/devices.cpp

225

parameters->heads = ((regs.edx >> 8) & 0xff) + 1;

src/system/boot/platform/atari_m68k/devices.cpp

227

parameters->sectors_per_track = regs.ecx & 0x3f;

src/system/boot/platform/bios_ia32/apm.cpp

28

struct bios_regs regs;

src/system/boot/platform/bios_ia32/apm.cpp

29

regs.eax = BIOS_APM_CHECK;

src/system/boot/platform/bios_ia32/apm.cpp

30

regs.ebx = 0;

src/system/boot/platform/bios_ia32/apm.cpp

31

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/apm.cpp

33

if ((regs.flags & CARRY_FLAG) != 0

src/system/boot/platform/bios_ia32/apm.cpp

34

|| (regs.ebx & 0xffff) != 'PM') {

src/system/boot/platform/bios_ia32/apm.cpp

40

gKernelArgs.platform_args.apm.version = regs.eax & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

41

gKernelArgs.platform_args.apm.flags = regs.ecx & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

54

regs.eax = BIOS_APM_DISCONNECT;

src/system/boot/platform/bios_ia32/apm.cpp

55

regs.ebx = 0;

src/system/boot/platform/bios_ia32/apm.cpp

56

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/apm.cpp

62

regs.eax = BIOS_APM_CONNECT_32_BIT;

src/system/boot/platform/bios_ia32/apm.cpp

63

regs.ebx = 0;

src/system/boot/platform/bios_ia32/apm.cpp

64

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/apm.cpp

65

if ((regs.flags & CARRY_FLAG) != 0) {

src/system/boot/platform/bios_ia32/apm.cpp

71

gKernelArgs.platform_args.apm.code32_segment_base = regs.eax & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

72

gKernelArgs.platform_args.apm.code32_segment_offset = regs.ebx;

src/system/boot/platform/bios_ia32/apm.cpp

73

gKernelArgs.platform_args.apm.code32_segment_length = regs.esi & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

75

gKernelArgs.platform_args.apm.code16_segment_base = regs.ecx & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

76

gKernelArgs.platform_args.apm.code16_segment_length = regs.esi >> 16;

src/system/boot/platform/bios_ia32/apm.cpp

78

gKernelArgs.platform_args.apm.data_segment_base = regs.edx & 0xffff;

src/system/boot/platform/bios_ia32/apm.cpp

79

gKernelArgs.platform_args.apm.data_segment_length = regs.edi & 0xffff;

src/system/boot/platform/bios_ia32/bios.cpp

23

extern "C" void call_bios_internal(uint8 num, struct bios_regs* regs);

src/system/boot/platform/bios_ia32/bios.cpp

27

call_bios(uint8 num, struct bios_regs* regs)

src/system/boot/platform/bios_ia32/bios.cpp

34

num, regs->eax, regs->ebx, regs->ecx, regs->edx, regs->esi, regs->edi,

src/system/boot/platform/bios_ia32/bios.cpp

35

regs->es, regs->flags));

src/system/boot/platform/bios_ia32/bios.cpp

36

call_bios_internal(num, regs);

src/system/boot/platform/bios_ia32/bios.h

50

void call_bios(uint8 num, struct bios_regs* regs);

src/system/boot/platform/bios_ia32/devices.cpp

174

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

175

regs.eax = BIOS_BOOT_CD_GET_STATUS;

src/system/boot/platform/bios_ia32/devices.cpp

176

regs.edx = 0;

src/system/boot/platform/bios_ia32/devices.cpp

177

regs.esi = kDataSegmentScratch;

src/system/boot/platform/bios_ia32/devices.cpp

178

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

180

if ((regs.flags & CARRY_FLAG) != 0)

src/system/boot/platform/bios_ia32/devices.cpp

204

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

205

regs.eax = BIOS_IS_EXT_PRESENT;

src/system/boot/platform/bios_ia32/devices.cpp

206

regs.ebx = 0x55aa;

src/system/boot/platform/bios_ia32/devices.cpp

207

regs.edx = drive;

src/system/boot/platform/bios_ia32/devices.cpp

208

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

211

regs.flags & CARRY_FLAG, regs.ebx, regs.ecx));

src/system/boot/platform/bios_ia32/devices.cpp

212

return (regs.flags & CARRY_FLAG) == 0 && regs.ebx == 0xaa55

src/system/boot/platform/bios_ia32/devices.cpp

213

&& (regs.ecx & 0x01 /* supports device access using packet */) != 0;

src/system/boot/platform/bios_ia32/devices.cpp

225

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

226

regs.eax = BIOS_GET_EXT_DRIVE_PARAMETERS;

src/system/boot/platform/bios_ia32/devices.cpp

227

regs.edx = drive;

src/system/boot/platform/bios_ia32/devices.cpp

228

regs.esi = (addr_t)parameter - kDataSegmentBase;

src/system/boot/platform/bios_ia32/devices.cpp

229

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

232

if ((regs.flags & CARRY_FLAG) != 0

src/system/boot/platform/bios_ia32/devices.cpp

244

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

245

regs.eax = BIOS_GET_DRIVE_PARAMETERS;

src/system/boot/platform/bios_ia32/devices.cpp

246

regs.edx = drive;

src/system/boot/platform/bios_ia32/devices.cpp

247

regs.es = 0;

src/system/boot/platform/bios_ia32/devices.cpp

248

regs.edi = 0; // guard against faulty BIOS, see Ralf Brown's interrupt list

src/system/boot/platform/bios_ia32/devices.cpp

249

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

251

if ((regs.flags & CARRY_FLAG) != 0 || (regs.ecx & 0x3f) == 0)

src/system/boot/platform/bios_ia32/devices.cpp

257

parameters->cylinders = (((regs.ecx & 0xc0) << 2) | ((regs.ecx >> 8) & 0xff)) + 1;

src/system/boot/platform/bios_ia32/devices.cpp

258

parameters->heads = ((regs.edx >> 8) & 0xff) + 1;

src/system/boot/platform/bios_ia32/devices.cpp

260

parameters->sectors_per_track = regs.ecx & 0x3f;

src/system/boot/platform/bios_ia32/devices.cpp

272

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

273

regs.eax = BIOS_GET_DRIVE_PARAMETERS;

src/system/boot/platform/bios_ia32/devices.cpp

274

regs.edx = 0x80;

src/system/boot/platform/bios_ia32/devices.cpp

275

regs.es = 0;

src/system/boot/platform/bios_ia32/devices.cpp

276

regs.edi = 0;

src/system/boot/platform/bios_ia32/devices.cpp

277

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

279

if (regs.flags & CARRY_FLAG)

src/system/boot/platform/bios_ia32/devices.cpp

282

*_count = regs.edx & 0xff;

src/system/boot/platform/bios_ia32/devices.cpp

657

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

658

regs.eax = BIOS_EXT_READ;

src/system/boot/platform/bios_ia32/devices.cpp

659

regs.edx = fDriveID;

src/system/boot/platform/bios_ia32/devices.cpp

660

regs.esi = (addr_t)packet - kDataSegmentBase;

src/system/boot/platform/bios_ia32/devices.cpp

661

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

663

if (regs.flags & CARRY_FLAG)

src/system/boot/platform/bios_ia32/devices.cpp

686

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

691

regs.eax = BIOS_READ | blocksRead;

src/system/boot/platform/bios_ia32/devices.cpp

692

regs.edx = fDriveID | (head << 8);

src/system/boot/platform/bios_ia32/devices.cpp

693

regs.ecx = sector | ((cylinder >> 2) & 0xc0) | ((cylinder & 0xff) << 8);

src/system/boot/platform/bios_ia32/devices.cpp

694

regs.es = 0;

src/system/boot/platform/bios_ia32/devices.cpp

695

regs.ebx = kExtraSegmentScratch;

src/system/boot/platform/bios_ia32/devices.cpp

696

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

698

if ((regs.flags & CARRY_FLAG) == 0) {

src/system/boot/platform/bios_ia32/devices.cpp

708

regs.eax = BIOS_RESET_DISK_SYSTEM;

src/system/boot/platform/bios_ia32/devices.cpp

709

regs.edx = fDriveID;

src/system/boot/platform/bios_ia32/devices.cpp

710

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

785

struct bios_regs regs;

src/system/boot/platform/bios_ia32/devices.cpp

786

regs.eax = BIOS_EXT_WRITE; // al = 0x00 -- no write verify

src/system/boot/platform/bios_ia32/devices.cpp

787

regs.edx = fDriveID;

src/system/boot/platform/bios_ia32/devices.cpp

788

regs.esi = (addr_t)packet - kDataSegmentBase;

src/system/boot/platform/bios_ia32/devices.cpp

789

call_bios(0x13, &regs);

src/system/boot/platform/bios_ia32/devices.cpp

791

if (regs.flags & CARRY_FLAG)

src/system/boot/platform/bios_ia32/keyboard.cpp

19

bios_regs regs;

src/system/boot/platform/bios_ia32/keyboard.cpp

20

regs.eax = 0x0100;

src/system/boot/platform/bios_ia32/keyboard.cpp

21

call_bios(0x16, &regs);

src/system/boot/platform/bios_ia32/keyboard.cpp

24

if (regs.flags & ZERO_FLAG)

src/system/boot/platform/bios_ia32/keyboard.cpp

28

regs.eax = 0;

src/system/boot/platform/bios_ia32/keyboard.cpp

29

call_bios(0x16, &regs);

src/system/boot/platform/bios_ia32/keyboard.cpp

31

return regs.eax & 0xffff;

src/system/boot/platform/bios_ia32/keyboard.cpp

58

bios_regs regs;

src/system/boot/platform/bios_ia32/keyboard.cpp

61

regs.eax = 0x0200;

src/system/boot/platform/bios_ia32/keyboard.cpp

62

call_bios(0x16, &regs);

src/system/boot/platform/bios_ia32/keyboard.cpp

64

if ((regs.eax & 0x03) != 0) {

src/system/boot/platform/bios_ia32/long.cpp

131

&& (info.regs.ecx & IA32_FEATURE_LA57) != 0) {

src/system/boot/platform/bios_ia32/long.cpp

342

if ((info.regs.edx & (1 << 29)) == 0)

src/system/boot/platform/bios_ia32/mmu.cpp

299

bios_regs regs;

src/system/boot/platform/bios_ia32/mmu.cpp

304

regs.ecx = sizeof(extended_memory);

src/system/boot/platform/bios_ia32/mmu.cpp

305

regs.edi = (uint32)block;

src/system/boot/platform/bios_ia32/mmu.cpp

308

regs.eax = 0xe820;

src/system/boot/platform/bios_ia32/mmu.cpp

309

regs.edx = 'SMAP';

src/system/boot/platform/bios_ia32/mmu.cpp

311

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/mmu.cpp

312

if ((regs.flags & CARRY_FLAG) != 0)

src/system/boot/platform/bios_ia32/mmu.cpp

315

regs.edi += sizeof(extended_memory);

src/system/boot/platform/bios_ia32/mmu.cpp

317

} while (regs.ebx != 0);

src/system/boot/platform/bios_ia32/mmu.cpp

771

bios_regs regs;

src/system/boot/platform/bios_ia32/mmu.cpp

779

regs.eax = 0xe801; // AX

src/system/boot/platform/bios_ia32/mmu.cpp

780

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/mmu.cpp

781

if ((regs.flags & CARRY_FLAG) != 0) {

src/system/boot/platform/bios_ia32/mmu.cpp

782

regs.eax = 0x8800; // AH 88h

src/system/boot/platform/bios_ia32/mmu.cpp

783

call_bios(0x15, &regs);

src/system/boot/platform/bios_ia32/mmu.cpp

784

if ((regs.flags & CARRY_FLAG) != 0) {

src/system/boot/platform/bios_ia32/mmu.cpp

791

gKernelArgs.physical_memory_range[1].size = regs.eax * 1024;

src/system/boot/platform/bios_ia32/mmu.cpp

796

gKernelArgs.physical_memory_range[1].size = regs.ecx * 1024;

src/system/boot/platform/bios_ia32/mmu.cpp

798

gKernelArgs.physical_memory_range[2].size = regs.edx * 64 * 1024;

src/system/boot/platform/bios_ia32/smp.cpp

546

&& (info.regs.ecx & IA32_FEATURE_EXT_X2APIC) != 0) {

src/system/boot/platform/bios_ia32/smp.cpp

557

&& (info.regs.ebx & (IA32_FEATURE_SMEP

src/system/boot/platform/bios_ia32/smp.cpp

567

&& (info.regs.ecx & IA32_FEATURE_LA57) != 0) {

src/system/boot/platform/bios_ia32/smp.cpp

581

&& (info.regs.edx & IA32_FEATURE_PAT) != 0) {

src/system/boot/platform/bios_ia32/video.cpp

277

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

278

regs.eax = 0x4f14;

src/system/boot/platform/bios_ia32/video.cpp

279

regs.ebx = 0x0102;

src/system/boot/platform/bios_ia32/video.cpp

280

regs.ecx = scaling;

src/system/boot/platform/bios_ia32/video.cpp

281

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

371

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

372

regs.eax = 0x4f15;

src/system/boot/platform/bios_ia32/video.cpp

373

regs.ebx = 0;

src/system/boot/platform/bios_ia32/video.cpp

375

regs.ecx = 0;

src/system/boot/platform/bios_ia32/video.cpp

376

regs.es = 0;

src/system/boot/platform/bios_ia32/video.cpp

377

regs.edi = 0;

src/system/boot/platform/bios_ia32/video.cpp

378

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

380

TRACE(("EDID1: %x\n", regs.eax));

src/system/boot/platform/bios_ia32/video.cpp

383

if (regs.eax != 0x4f)

src/system/boot/platform/bios_ia32/video.cpp

386

TRACE(("EDID2: ebx %x\n", regs.ebx));

src/system/boot/platform/bios_ia32/video.cpp

388

if ((regs.ebx & 3) == 0)

src/system/boot/platform/bios_ia32/video.cpp

393

regs.eax = 0x4f15;

src/system/boot/platform/bios_ia32/video.cpp

394

regs.ebx = 1;

src/system/boot/platform/bios_ia32/video.cpp

396

regs.ecx = 0;

src/system/boot/platform/bios_ia32/video.cpp

397

regs.edx = 0;

src/system/boot/platform/bios_ia32/video.cpp

398

regs.es = ADDRESS_SEGMENT(&edidRaw);

src/system/boot/platform/bios_ia32/video.cpp

399

regs.edi = ADDRESS_OFFSET(&edidRaw);

src/system/boot/platform/bios_ia32/video.cpp

400

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

401

TRACE(("EDID3: %x\n", regs.eax));

src/system/boot/platform/bios_ia32/video.cpp

403

if (regs.eax != 0x4f)

src/system/boot/platform/bios_ia32/video.cpp

421

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

422

regs.eax = 0x4f01;

src/system/boot/platform/bios_ia32/video.cpp

423

regs.ecx = mode;

src/system/boot/platform/bios_ia32/video.cpp

424

regs.es = ADDRESS_SEGMENT(modeInfo);

src/system/boot/platform/bios_ia32/video.cpp

425

regs.edi = ADDRESS_OFFSET(modeInfo);

src/system/boot/platform/bios_ia32/video.cpp

426

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

429

if ((regs.eax & 0xff00) != 0)

src/system/boot/platform/bios_ia32/video.cpp

442

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

443

regs.eax = 0x4f00;

src/system/boot/platform/bios_ia32/video.cpp

444

regs.es = ADDRESS_SEGMENT(info);

src/system/boot/platform/bios_ia32/video.cpp

445

regs.edi = ADDRESS_OFFSET(info);

src/system/boot/platform/bios_ia32/video.cpp

446

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

449

if ((regs.eax & 0xff00) != 0)

src/system/boot/platform/bios_ia32/video.cpp

568

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

569

regs.eax = 0x4f03;

src/system/boot/platform/bios_ia32/video.cpp

570

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

572

if ((regs.eax & 0xffff) != 0x4f)

src/system/boot/platform/bios_ia32/video.cpp

575

*_mode = regs.ebx & 0xffff;

src/system/boot/platform/bios_ia32/video.cpp

584

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

585

regs.eax = 0x4f02;

src/system/boot/platform/bios_ia32/video.cpp

586

regs.ebx = (mode->mode & SET_MODE_MASK) | SET_MODE_LINEAR_BUFFER;

src/system/boot/platform/bios_ia32/video.cpp

589

regs.ebx |= SET_MODE_SPECIFY_CRTC;

src/system/boot/platform/bios_ia32/video.cpp

590

regs.es = ADDRESS_SEGMENT(mode->timing);

src/system/boot/platform/bios_ia32/video.cpp

591

regs.edi = ADDRESS_OFFSET(mode->timing);

src/system/boot/platform/bios_ia32/video.cpp

594

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

596

if ((regs.eax & 0xffff) != 0x4f)

src/system/boot/platform/bios_ia32/video.cpp

601

regs.eax = 0x4f08;

src/system/boot/platform/bios_ia32/video.cpp

602

regs.ebx = 8 << 8;

src/system/boot/platform/bios_ia32/video.cpp

603

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

618

struct bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

619

regs.eax = 0x4f09;

src/system/boot/platform/bios_ia32/video.cpp

620

regs.ebx = 0;

src/system/boot/platform/bios_ia32/video.cpp

621

regs.ecx = numEntries;

src/system/boot/platform/bios_ia32/video.cpp

622

regs.edx = firstIndex;

src/system/boot/platform/bios_ia32/video.cpp

623

regs.es = (addr_t)palette >> 4;

src/system/boot/platform/bios_ia32/video.cpp

624

regs.edi = (addr_t)palette & 0xf;

src/system/boot/platform/bios_ia32/video.cpp

625

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

627

if ((regs.eax & 0xffff) != 0x4f) {

src/system/boot/platform/bios_ia32/video.cpp

715

bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

716

regs.eax = 0x0012;

src/system/boot/platform/bios_ia32/video.cpp

717

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

718

return (regs.eax == 0x4f) ? B_OK : B_NOT_SUPPORTED;

src/system/boot/platform/bios_ia32/video.cpp

726

bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

727

regs.eax = 0x0003;

src/system/boot/platform/bios_ia32/video.cpp

728

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

737

bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

738

regs.eax = 0x0200;

src/system/boot/platform/bios_ia32/video.cpp

739

regs.ebx = 0;

src/system/boot/platform/bios_ia32/video.cpp

740

regs.edx = (y << 8) | x;

src/system/boot/platform/bios_ia32/video.cpp

741

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

748

bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

749

regs.eax = 0x0100;

src/system/boot/platform/bios_ia32/video.cpp

750

regs.ecx = 0x0607;

src/system/boot/platform/bios_ia32/video.cpp

751

call_bios(0x10, &regs);

src/system/boot/platform/bios_ia32/video.cpp

758

bios_regs regs;

src/system/boot/platform/bios_ia32/video.cpp

759

regs.eax = 0x0100;

src/system/boot/platform/bios_ia32/video.cpp

760

regs.ecx = 0x2000;

src/system/boot/platform/bios_ia32/video.cpp

761

call_bios(0x10, &regs);

src/system/boot/platform/efi/arch/arm/arch_dtb.cpp

128

timer.regs.start,

src/system/boot/platform/efi/arch/arm/arch_dtb.cpp

129

timer.regs.size);

src/system/boot/platform/efi/arch/arm/arch_dtb.cpp

96

dtb_get_reg(fdt, node, 0, timer.regs);

src/system/boot/platform/efi/arch/arm/arch_mmu.cpp

286

map_range_to_new_area(gKernelArgs.arch_args.uart.regs,

src/system/boot/platform/efi/arch/arm/arch_mmu.cpp

288

gUART->SetBase(gKernelArgs.arch_args.uart.regs.start);

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

23

gUART = new(sUART) ArchUARTPL011(uart.regs.start,

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

41

uart.regs.start = spcr->base_address.address;

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

42

uart.regs.size = B_PAGE_SIZE;

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

51

uart.regs.start, uart.irq, uart.clock);

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

69

uart.regs.start = base_addr->address;

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

70

uart.regs.size = *base_size;

src/system/boot/platform/efi/arch/arm64/arch_acpi.cpp

77

dprintf("discovered uart from dbg2 acpi: base=%lx\n", uart.regs.start);

src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp

347

uint64 regs_start = gKernelArgs.arch_args.uart.regs.start;

src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp

348

uint64 regs_size = ROUNDUP(gKernelArgs.arch_args.uart.regs.size, B_PAGE_SIZE);

src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp

358

gKernelArgs.arch_args.uart.regs.start = base;

src/system/boot/platform/efi/arch/riscv64/arch_mmu.cpp

433

MapRange(gKernelArgs.arch_args.uart.regs.start,

src/system/boot/platform/efi/arch/riscv64/arch_mmu.cpp

434

gKernelArgs.arch_args.uart.regs.start,

src/system/boot/platform/efi/arch/riscv64/arch_mmu.cpp

435

gKernelArgs.arch_args.uart.regs.size,

src/system/boot/platform/efi/arch/riscv64/arch_mmu.cpp

437

MapAddrRange(gKernelArgs.arch_args.uart.regs,

src/system/boot/platform/efi/arch/x86/arch_smp.cpp

356

&& (info.regs.ecx & IA32_FEATURE_EXT_X2APIC) != 0) {

src/system/boot/platform/efi/arch/x86/arch_smp.cpp

364

&& ((info.regs.ebx & (IA32_FEATURE_SMEP

src/system/boot/platform/efi/arch/x86/arch_smp.cpp

376

&& (info.regs.edx & IA32_FEATURE_PAT) != 0) {

src/system/boot/platform/efi/dtb.cpp

566

dtb_get_reg(fdt, node, 0, uart.regs);

src/system/boot/platform/efi/dtb.cpp

570

gUART = kSupportedUarts[i].uart_driver_init(uart.regs.start,

src/system/boot/platform/efi/dtb.cpp

669

dprintf(" regs: %#" B_PRIx64 ", %#" B_PRIx64 "\n", uart.regs.start, uart.regs.size);

src/system/boot/platform/riscv/fdt.cpp

163

sUart.regs.start = fdt64_to_cpu(*(reg + 0));

src/system/boot/platform/riscv/fdt.cpp

164

sUart.regs.size = fdt64_to_cpu(*(reg + 1));

src/system/boot/platform/riscv/mmu.cpp

280

MapAddrRange(gKernelArgs.arch_args.uart.regs,

src/system/boot/platform/riscv/virtio.cpp

218

VirtioRegs* volatile regs = (VirtioRegs* volatile)base;

src/system/boot/platform/riscv/virtio.cpp

222

dprintf(" signature: 0x%" B_PRIx32 "\n", regs->signature);

src/system/boot/platform/riscv/virtio.cpp

223

dprintf(" version: %" B_PRIu32 "\n", regs->version);

src/system/boot/platform/riscv/virtio.cpp

224

dprintf(" device id: %" B_PRIu32 "\n", regs->deviceId);

src/system/boot/platform/riscv/virtio.cpp

230

gVirtioDevList[gVirtioDevListLen].regs = regs;

src/system/boot/platform/riscv/virtio.cpp

246

VirtioRegs* volatile regs = devRes->regs;

src/system/boot/platform/riscv/virtio.cpp

247

regs->config[0] = kVirtioInputCfgIdName;

src/system/boot/platform/riscv/virtio.cpp

248

dprintf("virtio_input[%d]: %s\n", i, (const char*)(&regs->config[8]));

src/system/boot/platform/riscv/virtio.cpp

53

VirtioRegs* volatile regs = gVirtioDevList[i].regs;

src/system/boot/platform/riscv/virtio.cpp

54

if (regs->signature != kVirtioSignature) continue;

src/system/boot/platform/riscv/virtio.cpp

55

if (regs->deviceId == deviceId) {

src/system/boot/platform/riscv/virtio.cpp

85

VirtioDevice::VirtioDevice(const VirtioResources& devRes): fRegs(devRes.regs)

src/system/boot/platform/riscv/virtio.h

16

VirtioRegs* volatile regs;

src/system/kernel/arch/arm/arch_debug_console.cpp

104

sArchDebugUART = arch_get_uart_pl011(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm/arch_debug_console.cpp

108

sArchDebugUART = arch_get_uart_8250_omap(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm/arch_debug_console.cpp

112

sArchDebugUART = arch_get_uart_8250(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm/arch_timer.cpp

64

OMAP3Timer::Init(args->arch_args.timer.regs.start,

src/system/kernel/arch/arm/arch_timer.cpp

68

PXATimer::Init(args->arch_args.timer.regs.start);

src/system/kernel/arch/arm64/arch_debug_console.cpp

102

sArchDebugUART = arch_get_uart_linflex(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm64/arch_debug_console.cpp

110

sArchDebugUART = arch_get_uart_8250(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm64/arch_debug_console.cpp

114

sArchDebugUART = arch_get_uart_samsung(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm64/arch_debug_console.cpp

98

sArchDebugUART = arch_get_uart_pl011(args->arch_args.uart.regs.start,

src/system/kernel/arch/arm64/arch_thread.cpp

184

memcpy(signalFrameData->context.uc_mcontext.fp_q, frame->fpu.regs,

src/system/kernel/arch/arm64/arch_thread.cpp

230

memcpy(frame->fpu.regs, signalFrameData->context.uc_mcontext.fp_q,

src/system/kernel/arch/arm64/arch_thread.cpp

73

thread->arch_info.regs[10] = (uint64_t)data;

src/system/kernel/arch/arm64/arch_thread.cpp

74

thread->arch_info.regs[11] = (uint64_t)function;

src/system/kernel/arch/arm64/arch_thread.cpp

75

thread->arch_info.regs[12] = (uint64_t)_stackTop;

src/system/kernel/arch/arm64/arch_vm_translation_map.cpp

106

address = (void*)args->arch_args.uart.regs.start;

src/system/kernel/arch/arm64/arch_vm_translation_map.cpp

109

ROUNDUP(args->arch_args.uart.regs.size, B_PAGE_SIZE), 0);

src/system/kernel/arch/riscv64/arch_debug.cpp

392

uint64* regs = &frame->ra;

src/system/kernel/arch/riscv64/arch_debug.cpp

399

registerNames[i + 0], regs[i + 0],

src/system/kernel/arch/riscv64/arch_debug.cpp

400

registerNames[i + 1], regs[i + 1],

src/system/kernel/arch/riscv64/arch_debug.cpp

401

registerNames[i + 2], regs[i + 2],

src/system/kernel/arch/riscv64/arch_debug.cpp

402

registerNames[i + 3], regs[i + 3]

src/system/kernel/arch/riscv64/arch_debug_console.cpp

102

sArchDebugUART = arch_get_uart_8250(args->arch_args.uart.regs.start,

src/system/kernel/arch/riscv64/arch_debug_console.cpp

106

sArchDebugUART = arch_get_uart_sifive(args->arch_args.uart.regs.start,

src/system/kernel/arch/x86/32/apm.cpp

106

: "=a" (regs->eax), "=b" (regs->ebx), "=c" (regs->ecx), "=d" (regs->edx),

src/system/kernel/arch/x86/32/apm.cpp

107

"=S" (regs->esi), "=m" (regs->flags)

src/system/kernel/arch/x86/32/apm.cpp

108

: "a" (regs->eax), "b" (regs->ebx), "c" (regs->ecx)

src/system/kernel/arch/x86/32/apm.cpp

111

if (regs->flags & CARRY_FLAG)

src/system/kernel/arch/x86/32/apm.cpp

124

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

125

regs.eax = BIOS_APM_GET_EVENT;

src/system/kernel/arch/x86/32/apm.cpp

127

if (call_apm_bios(&regs) != B_OK)

src/system/kernel/arch/x86/32/apm.cpp

130

event = regs.ebx & 0xffff;

src/system/kernel/arch/x86/32/apm.cpp

131

info = regs.ecx & 0xffff;

src/system/kernel/arch/x86/32/apm.cpp

139

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

140

regs.eax = BIOS_APM_SET_STATE;

src/system/kernel/arch/x86/32/apm.cpp

141

regs.ebx = device;

src/system/kernel/arch/x86/32/apm.cpp

142

regs.ecx = state;

src/system/kernel/arch/x86/32/apm.cpp

144

status_t status = call_apm_bios(&regs);

src/system/kernel/arch/x86/32/apm.cpp

148

TRACE(("apm_set_state() error: %s\n", apm_error(regs.eax)));

src/system/kernel/arch/x86/32/apm.cpp

156

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

157

regs.eax = BIOS_APM_ENABLE;

src/system/kernel/arch/x86/32/apm.cpp

158

regs.ebx = device;

src/system/kernel/arch/x86/32/apm.cpp

159

regs.ecx = enable ? 0x01 : 0x00;

src/system/kernel/arch/x86/32/apm.cpp

161

return call_apm_bios(&regs);

src/system/kernel/arch/x86/32/apm.cpp

168

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

169

regs.eax = BIOS_APM_ENGAGE;

src/system/kernel/arch/x86/32/apm.cpp

170

regs.ebx = device;

src/system/kernel/arch/x86/32/apm.cpp

171

regs.ecx = engage ? 0x01 : 0x00;

src/system/kernel/arch/x86/32/apm.cpp

173

return call_apm_bios(&regs);

src/system/kernel/arch/x86/32/apm.cpp

181

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

182

regs.eax = BIOS_APM_VERSION;

src/system/kernel/arch/x86/32/apm.cpp

183

regs.ecx = version;

src/system/kernel/arch/x86/32/apm.cpp

185

if (call_apm_bios(&regs) != B_OK)

src/system/kernel/arch/x86/32/apm.cpp

188

dprintf("eax: %x, flags: %x\n", regs.eax, regs.flags);

src/system/kernel/arch/x86/32/apm.cpp

209

bios_regs regs;

src/system/kernel/arch/x86/32/apm.cpp

210

regs.eax = BIOS_APM_GET_POWER_STATUS;

src/system/kernel/arch/x86/32/apm.cpp

211

regs.ebx = APM_ALL_DEVICES;

src/system/kernel/arch/x86/32/apm.cpp

212

regs.ecx = 0;

src/system/kernel/arch/x86/32/apm.cpp

214

status_t status = call_apm_bios(&regs);

src/system/kernel/arch/x86/32/apm.cpp

218

uint16 lineStatus = (regs.ebx >> 8) & 0xff;

src/system/kernel/arch/x86/32/apm.cpp

223

info->percent = regs.ecx & 0xff;

src/system/kernel/arch/x86/32/apm.cpp

227

info->time_left = info->percent >= 0 ? (int32)(regs.edx & 0xffff) : -1;

src/system/kernel/arch/x86/32/apm.cpp

92

call_apm_bios(bios_regs *regs)

src/system/kernel/arch/x86/64/cpuid.cpp

16

__cpuid_count(eax, ecx, info->regs.eax, info->regs.ebx, info->regs.ecx,

src/system/kernel/arch/x86/64/cpuid.cpp

17

info->regs.edx);

src/system/kernel/arch/x86/arch_cpu.cpp

1070

uint32 signature = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1186

uint32 signature = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1329

return cpuid.regs.eax >> X86_HYBRID_CPU_TYPE_ID_SHIFT;

src/system/kernel/arch/x86/arch_cpu.cpp

1417

temp = cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

1418

cpuid.regs.edx = cpuid.regs.ecx;

src/system/kernel/arch/x86/arch_cpu.cpp

1419

cpuid.regs.ecx = temp;

src/system/kernel/arch/x86/arch_cpu.cpp

1423

temp = cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

1424

cpuid.regs.edx = cpuid.regs.ecx;

src/system/kernel/arch/x86/arch_cpu.cpp

1425

cpuid.regs.ecx = temp;

src/system/kernel/arch/x86/arch_cpu.cpp

1430

temp = cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

1431

cpuid.regs.edx = cpuid.regs.ecx;

src/system/kernel/arch/x86/arch_cpu.cpp

1432

cpuid.regs.ecx = temp;

src/system/kernel/arch/x86/arch_cpu.cpp

1464

cpu->arch.feature[FEATURE_EXT_AMD_ECX] = cpuid.regs.ecx; // ecx

src/system/kernel/arch/x86/arch_cpu.cpp

1465

cpu->arch.feature[FEATURE_EXT_AMD] = cpuid.regs.edx; // edx

src/system/kernel/arch/x86/arch_cpu.cpp

1472

cpu->arch.feature[FEATURE_6_EAX] = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1473

cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx;

src/system/kernel/arch/x86/arch_cpu.cpp

1478

cpu->arch.feature[FEATURE_7_EBX] = cpuid.regs.ebx;

src/system/kernel/arch/x86/arch_cpu.cpp

1479

cpu->arch.feature[FEATURE_7_ECX] = cpuid.regs.ecx;

src/system/kernel/arch/x86/arch_cpu.cpp

1480

cpu->arch.feature[FEATURE_7_EDX] = cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

1482

cpu->arch.feature[FEATURE_7_1_EAX] = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1487

cpu->arch.feature[FEATURE_D_1_EAX] = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1492

cpu->arch.feature[FEATURE_EXT_7_EDX] = cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

1497

cpu->arch.feature[FEATURE_EXT_8_EBX] = cpuid.regs.ebx;

src/system/kernel/arch/x86/arch_cpu.cpp

1668

if (cpuid.regs.eax == 0 || cpuid.regs.ebx == 0)

src/system/kernel/arch/x86/arch_cpu.cpp

1670

uint32 khz = cpuid.regs.ecx / 1000;

src/system/kernel/arch/x86/arch_cpu.cpp

1671

uint32 denominator = cpuid.regs.eax;

src/system/kernel/arch/x86/arch_cpu.cpp

1672

uint32 numerator = cpuid.regs.ebx;

src/system/kernel/arch/x86/arch_cpu.cpp

1681

khz = cpuid.regs.eax * 1000 * denominator / numerator;

src/system/kernel/arch/x86/arch_cpu.cpp

1947

gXsaveMask |= (cpuid.regs.eax & IA32_XCR0_AVX);

src/system/kernel/arch/x86/arch_cpu.cpp

1949

gXsaveMask |= cpuid.regs.eax

src/system/kernel/arch/x86/arch_cpu.cpp

1954

gFPUSaveLength = cpuid.regs.ebx;

src/system/kernel/arch/x86/arch_cpu.cpp

738

return cpuid.regs.ebx >> 24;

src/system/kernel/arch/x86/arch_cpu.cpp

749

int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff);

src/system/kernel/arch/x86/arch_cpu.cpp

754

maxCoreID = (cpuid.regs.ecx >> 12) & 0xf;

src/system/kernel/arch/x86/arch_cpu.cpp

758

maxCoreID = next_power_of_2((cpuid.regs.edx & 0xf) + 1);

src/system/kernel/arch/x86/arch_cpu.cpp

792

cacheType = cpuid.regs.eax & 0x1f;

src/system/kernel/arch/x86/arch_cpu.cpp

796

int cacheLevel = (cpuid.regs.eax >> 5) & 0x7;

src/system/kernel/arch/x86/arch_cpu.cpp

797

int coresCount = next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1);

src/system/kernel/arch/x86/arch_cpu.cpp

816

return cpuid.regs.edx;

src/system/kernel/arch/x86/arch_cpu.cpp

828

if (cpuid.regs.ebx != 0)

src/system/kernel/arch/x86/arch_cpu.cpp

833

if (cpuid.regs.ebx != 0)

src/system/kernel/arch/x86/arch_cpu.cpp

846

int levelType = (cpuid.regs.ecx >> 8) & 0xff;

src/system/kernel/arch/x86/arch_cpu.cpp

847

int levelValue = cpuid.regs.eax & 0x1f;

src/system/kernel/arch/x86/arch_cpu.cpp

895

int maxLogicalID = next_power_of_2((cpuid.regs.ebx >> 16) & 0xff);

src/system/kernel/arch/x86/arch_cpu.cpp

900

maxCoreID = next_power_of_2((cpuid.regs.eax >> 26) + 1);

src/system/kernel/arch/x86/arch_cpu.cpp

924

cacheType = cpuid.regs.eax & 0x1f;

src/system/kernel/arch/x86/arch_cpu.cpp

928

int cacheLevel = (cpuid.regs.eax >> 5) & 0x7;

src/system/kernel/arch/x86/arch_cpu.cpp

930

= next_power_of_2(((cpuid.regs.eax >> 14) & 0x3f) + 1);

src/system/kernel/arch/x86/arch_system_info.cpp

108

if (cpuid.regs.eax != 0) {

src/system/kernel/arch/x86/arch_system_info.cpp

109

sCPUClockSpeed = cpuid.regs.eax * 1000000LL;

src/system/kernel/arch/x86/timers/x86_apic.cpp

142

const uint32 maxVMM = info.regs.eax;

src/system/kernel/arch/x86/timers/x86_apic.cpp

146

uint32 freq = info.regs.ebx * 1000;

src/system/libroot/os/arch/arm/stdatomic.c

48

register_t regs; \

src/system/libroot/os/arch/arm/stdatomic.c

50

regs = intr_disable(); \

src/system/libroot/os/arch/arm/stdatomic.c

52

intr_restore(regs); \

src/system/libroot/os/arch/x86_64/system_info.cpp

16

__cpuid_count(eax, 0, info->regs.eax, info->regs.ebx, info->regs.ecx,

src/system/libroot/os/arch/x86_64/system_info.cpp

17

info->regs.edx);

src/system/libroot/os/arch/x86_64/system_time.cpp

72

if ((cpuInfo.regs.edx & IA32_FEATURE_AMD_EXT_RDTSCP)!= 0) {

src/system/libroot/posix/glibc/regex/regex.c

46

# define re_match_2(bufp, string1, size1, string2, size2, pos, regs, stop) \

src/system/libroot/posix/glibc/regex/regex.c

47

__re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop)

src/system/libroot/posix/glibc/regex/regex.c

48

# define re_match(bufp, string, size, pos, regs) \

src/system/libroot/posix/glibc/regex/regex.c

49

__re_match (bufp, string, size, pos, regs)

src/system/libroot/posix/glibc/regex/regex.c

50

# define re_search(bufp, string, size, startpos, range, regs) \

src/system/libroot/posix/glibc/regex/regex.c

51

__re_search (bufp, string, size, startpos, range, regs)

src/system/libroot/posix/glibc/regex/regex.c

55

# define re_search_2(bufp, st1, s1, st2, s2, startpos, range, regs, stop) \

src/system/libroot/posix/glibc/regex/regex.c

56

__re_search_2 (bufp, st1, s1, st2, s2, startpos, range, regs, stop)

src/system/libroot/posix/glibc/regex/regex_internal.h

686

regmatch_t *regs;

src/system/libroot/posix/glibc/regex/regexec.c

1227

proceed_next_node (const re_match_context_t *mctx, Idx nregs, regmatch_t *regs,

src/system/libroot/posix/glibc/regex/regexec.c

1261

&& push_fail_stack (fs, *pidx, candidate, nregs, regs,

src/system/libroot/posix/glibc/regex/regexec.c

1284

naccepted = regs[subexp_idx].rm_eo - regs[subexp_idx].rm_so;

src/system/libroot/posix/glibc/regex/regexec.c

1287

if (regs[subexp_idx].rm_so == -1 || regs[subexp_idx].rm_eo == -1)

src/system/libroot/posix/glibc/regex/regexec.c

1293

|| (memcmp (buf + regs[subexp_idx].rm_so, buf + *pidx,

src/system/libroot/posix/glibc/regex/regexec.c

1332

Idx nregs, regmatch_t *regs, re_node_set *eps_via_nodes)

src/system/libroot/posix/glibc/regex/regexec.c

1348

fs->stack[num].regs = re_malloc (regmatch_t, nregs);

src/system/libroot/posix/glibc/regex/regexec.c

1349

if (fs->stack[num].regs == NULL)

src/system/libroot/posix/glibc/regex/regexec.c

1351

memcpy (fs->stack[num].regs, regs, sizeof (regmatch_t) * nregs);

src/system/libroot/posix/glibc/regex/regexec.c

1358

regmatch_t *regs, re_node_set *eps_via_nodes)

src/system/libroot/posix/glibc/regex/regexec.c

1363

memcpy (regs, fs->stack[num].regs, sizeof (regmatch_t) * nregs);

src/system/libroot/posix/glibc/regex/regexec.c

1365

re_free (fs->stack[num].regs);

src/system/libroot/posix/glibc/regex/regexec.c

1491

re_free (fs->stack[fs_idx].regs);

src/system/libroot/posix/glibc/regex/regexec.c

277

Idx start, struct re_registers *regs)

src/system/libroot/posix/glibc/regex/regexec.c

279

return re_search_stub (bufp, string, length, start, 0, length, regs, true);

src/system/libroot/posix/glibc/regex/regexec.c

287

Idx start, regoff_t range, struct re_registers *regs)

src/system/libroot/posix/glibc/regex/regexec.c

289

return re_search_stub (bufp, string, length, start, range, length, regs,

src/system/libroot/posix/glibc/regex/regexec.c

299

struct re_registers *regs, Idx stop)

src/system/libroot/posix/glibc/regex/regexec.c

302

start, 0, regs, stop, true);

src/system/libroot/posix/glibc/regex/regexec.c

311

struct re_registers *regs, Idx stop)

src/system/libroot/posix/glibc/regex/regexec.c

314

start, range, regs, stop, false);

src/system/libroot/posix/glibc/regex/regexec.c

323

regoff_t range, struct re_registers *regs,

src/system/libroot/posix/glibc/regex/regexec.c

357

rval = re_search_stub (bufp, str, len, start, range, stop, regs,

src/system/libroot/posix/glibc/regex/regexec.c

370

Idx start, regoff_t range, Idx stop, struct re_registers *regs,

src/system/libroot/posix/glibc/regex/regexec.c

399

regs = NULL;

src/system/libroot/posix/glibc/regex/regexec.c

402

if (regs == NULL)

src/system/libroot/posix/glibc/regex/regexec.c

405

&& regs->num_regs <= bufp->re_nsub, 0))

src/system/libroot/posix/glibc/regex/regexec.c

407

nregs = regs->num_regs;

src/system/libroot/posix/glibc/regex/regexec.c

411

regs = NULL;

src/system/libroot/posix/glibc/regex/regexec.c

43

struct re_registers *regs,

src/system/libroot/posix/glibc/regex/regexec.c

432

else if (regs != NULL)

src/system/libroot/posix/glibc/regex/regexec.c

435

bufp->regs_allocated = re_copy_regs (regs, pmatch, nregs,

src/system/libroot/posix/glibc/regex/regexec.c

458

re_copy_regs (struct re_registers *regs, regmatch_t *pmatch, Idx nregs,

src/system/libroot/posix/glibc/regex/regexec.c

470

regs->start = re_malloc (regoff_t, need_regs);

src/system/libroot/posix/glibc/regex/regexec.c

471

if (BE (regs->start == NULL, 0))

src/system/libroot/posix/glibc/regex/regexec.c

473

regs->end = re_malloc (regoff_t, need_regs);

src/system/libroot/posix/glibc/regex/regexec.c

474

if (BE (regs->end == NULL, 0))

src/system/libroot/posix/glibc/regex/regexec.c

476

re_free (regs->start);

src/system/libroot/posix/glibc/regex/regexec.c

479

regs->num_regs = need_regs;

src/system/libroot/posix/glibc/regex/regexec.c

48

struct re_registers *regs,

src/system/libroot/posix/glibc/regex/regexec.c

485

if (BE (need_regs > regs->num_regs, 0))

src/system/libroot/posix/glibc/regex/regexec.c

487

regoff_t *new_start = re_realloc (regs->start, regoff_t, need_regs);

src/system/libroot/posix/glibc/regex/regexec.c

491

new_end = re_realloc (regs->end, regoff_t, need_regs);

src/system/libroot/posix/glibc/regex/regexec.c

497

regs->start = new_start;

src/system/libroot/posix/glibc/regex/regexec.c

498

regs->end = new_end;

src/system/libroot/posix/glibc/regex/regexec.c

499

regs->num_regs = need_regs;

src/system/libroot/posix/glibc/regex/regexec.c

50

static unsigned re_copy_regs (struct re_registers *regs, regmatch_t *pmatch,

src/system/libroot/posix/glibc/regex/regexec.c

506

assert (regs->num_regs >= nregs);

src/system/libroot/posix/glibc/regex/regexec.c

513

regs->start[i] = pmatch[i].rm_so;

src/system/libroot/posix/glibc/regex/regexec.c

514

regs->end[i] = pmatch[i].rm_eo;

src/system/libroot/posix/glibc/regex/regexec.c

516

for ( ; i < regs->num_regs; ++i)

src/system/libroot/posix/glibc/regex/regexec.c

517

regs->start[i] = regs->end[i] = -1;

src/system/libroot/posix/glibc/regex/regexec.c

536

re_set_registers (struct re_pattern_buffer *bufp, struct re_registers *regs,

src/system/libroot/posix/glibc/regex/regexec.c

542

regs->num_regs = num_regs;

src/system/libroot/posix/glibc/regex/regexec.c

543

regs->start = starts;

src/system/libroot/posix/glibc/regex/regexec.c

544

regs->end = ends;

src/system/libroot/posix/glibc/regex/regexec.c

549

regs->num_regs = 0;

src/system/libroot/posix/glibc/regex/regexec.c

550

regs->start = regs->end = NULL;

src/system/libroot/posix/glibc/regex/regexec.c

62

regmatch_t *regs,

src/tests/add-ons/accelerants/intel_extreme/intel_reg.cpp

108

void* regs;

src/tests/add-ons/accelerants/intel_extreme/intel_reg.cpp

110

area_id clone = clone_area("clone regs", &regs, B_ANY_ADDRESS, protection, area);

src/tests/add-ons/accelerants/intel_extreme/intel_reg.cpp

142

addr_t addr = (addr_t)regs + address + i * sizeof(uint32);

src/tests/system/libroot/posix/signal_test.cpp

46

sigHandler(int signal, void *userData, vregs *regs)