pci_write_config
void pci_write_config(uint8 virtualBus, uint8 device, uint8 function,
.write_pci_config = pci_write_config,
&pci_write_config
pci_write_config(sc->xl_dev,
pci_write_config(sc->alc_dev,
pci_write_config(sc->alc_dev,
pci_write_config(sc->alc_dev,
pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(sc->ale_dev,
pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
pci_write_config(dev, BGE_PCI_MISC_CTL,
pci_write_config(dev, 0xC4, val | (1 << 15), 4);
pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
pci_write_config(dev, BGE_PCI_MISC_CTL,
pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
pci_write_config(dev, BGE_PCI_CMD, command, 4);
pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
pci_write_config(dev,
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
pci_write_config(dev, DC_PCI_CFDD, command, 4);
pci_write_config(dev, PCI_CFDA, cfdainfo, 4);
pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(dev, offset + reg, *value, 2);
pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
pci_write_config(dev, reg, link_ctrl, 2);
pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(sc->jme_dev,
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
pci_write_config(sc->msk_dev, PCIR_STATUS, status |
pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
pci_write_config(sc->msk_dev,
pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(dev, reg + 0x08, v, 2);
pci_write_config(sc->rl_dev,
pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(dev, sc->rl_expcap +
pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(dev, 0x48, reg & ~0x02, 1);
pci_write_config(dev, 0x48, reg, 1);
pci_write_config(sc->sis_dev,
pci_write_config(bridge, 0x48, reg|0x40, 1);
pci_write_config(bridge, 0x48, reg & ~0x40, 1);
pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2);
pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
pci_write_config(dev, VR_PCI_MODE2,
pci_write_config(dev, VR_PCI_MODE2,
pci_write_config(dev, VR_PCI_MODE3,
pci_write_config(dev, VR_PCI_MODE2,
pci_write_config(dev, VR_PCI_MODE2,
pci_write_config(sc->vge_dev,
pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS,
pci_write_config(dev, PCIR_CACHELNSZ,
pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1);
pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, 0x41, 0, 1);
pci_write_config(dev, cap_off + PCIER_LINK_CTL, lcsr, 4);
void pci_write_config(device_t dev, int reg, uint32_t val, int width);
pci_write_config(dev, PCI_command, command | bit, 2);
pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
pci_write_config(dev, capabilityRegister + PCIR_POWER_STATUS,
pci_write_config(SC_DEV_FOR_PCI, reg, val, sizeof(pcireg_t))