pci_read_config
uint32 pci_read_config(uint8 virtualBus, uint8 device, uint8 function,
status = pci_read_config(info->bus, info->device, info->function, PCI_status, 2);
cap_ptr = pci_read_config(info->bus, info->device, info->function, PCI_capabilities_ptr, 1);
cap_ptr = pci_read_config(info->bus, info->device, info->function, PCI_capabilities_ptr_2, 1);
cap_id = pci_read_config(info->bus, info->device, info->function, cap_ptr, 1);
cap_ptr = pci_read_config(info->bus, info->device, info->function, cap_ptr + 1, 1);
uint32 capability = pci_read_config(info->bus, info->device,
capability = pci_read_config(info->bus, info->device, info->function,
.read_pci_config = pci_read_config,
&pci_read_config,
pmstat = pci_read_config(sc->xl_dev,
pmstat = pci_read_config(sc->alc_dev,
pmstat = pci_read_config(sc->alc_dev,
pmstat = pci_read_config(sc->alc_dev,
pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
pmstat = pci_read_config(sc->ale_dev,
burst = pci_read_config(dev, i + 0x08, 2);
pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
burst = pci_read_config(dev, i + 0x08, 2);
pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
id = pci_read_config(dev,
id = pci_read_config(dev,
id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
command = pci_read_config(dev, BGE_PCI_CMD, 4);
val = pci_read_config(dev, 0xC4, 4);
devctl = pci_read_config(dev,
devctl = pci_read_config(dev,
val = pci_read_config(dev,
val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
uint32 notInterrupted = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4)
command = pci_read_config(dev, DC_PCI_CFDD, 4);
cfdainfo = pci_read_config(dev, PCI_CFDA, 4);
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
pci_read_config(dev, PCIR_SUBVEND_0, 2);
pci_read_config(dev, PCIR_SUBDEV_0, 2);
status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
*value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);
*value = pci_read_config(dev, offset + reg, 2);
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
val = pci_read_config(dev, rid, 4);
hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
link_cap = pci_read_config(dev, reg, 2);
link_ctrl = pci_read_config(dev, reg, 2);
pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
pmstat = pci_read_config(sc->jme_dev,
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
pcix_cmd = pci_read_config(sc->msk_dev,
v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2);
v = pci_read_config(dev, reg + 0x08, 2);
v = pci_read_config(dev, reg + 0x0c, 2);
width = pci_read_config(dev, reg + 0x12, 2);
if (chip_id == pci_read_config(dev,
pmstat = pci_read_config(sc->rl_dev,
pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
cap = pci_read_config(dev, sc->rl_expcap +
ctl = pci_read_config(dev, sc->rl_expcap +
pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
reg = pci_read_config(dev, 0x48, 1);
pci_read_config(dev, 0x48, 1);
if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0)
pmstat = pci_read_config(sc->sis_dev,
reg = pci_read_config(bridge, 0x48, 1);
sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2);
pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2);
pci_read_config(dev, VR_PCI_MODE2, 1) |
pci_read_config(dev, VR_PCI_MODE2, 1) |
pci_read_config(dev, VR_PCI_MODE3, 1) |
pci_read_config(dev, VR_PCI_MODE2, 1) |
pci_read_config(dev, VR_PCI_MODE2, 1) |
pmstat = pci_read_config(sc->vge_dev,
pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap +
cz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2);
(void) pci_read_config(dev, PCIR_COMMAND, 4);
val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
lcsr = pci_read_config(dev, cap_off + PCIER_LINK_CTL, 4);
uint8 irq = pci_read_config(dev, PCI_interrupt_line, 1);
uint32_t pci_read_config(device_t dev, int reg, int width);
return pci_read_config(dev, PCI_subsystem_vendor_id, 2);
return pci_read_config(dev, PCI_subsystem_id, 2);
return pci_read_config(dev, PCI_revision, 1);
return pci_read_config(dev, PCI_device_id, 2) << 16 |
pci_read_config(dev, PCI_vendor_id, 2);
return pci_read_config(dev, PCI_line_size, 1);
uint16_t command = pci_read_config(dev, PCI_command, 2);
if (pci_read_config(dev, PCI_command, 2) & bit)
val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2);
status = pci_read_config(dev, capabilityRegister + PCIR_POWER_STATUS, 2);
currentPowerManagementStatus = pci_read_config(dev, capabilityRegister
powerManagementCapabilities = pci_read_config(dev, capabilityRegister
return pci_read_config(dev, PCI_vendor_id, 2);
return pci_read_config(dev, PCI_device_id, 2);
pci_read_config(SC_DEV_FOR_PCI, reg, sizeof(pcireg_t))
*value = pci_read_config(dev, *offset, sizeof(pcireg_t));
return (_PCI_MAPREG_TYPEBITS(pci_read_config(dev, reg, sizeof(pcireg_t))));