#ifndef _CXGB3_OFFLOAD_CTL_DEFS_H
#define _CXGB3_OFFLOAD_CTL_DEFS_H
enum {
GET_MAX_OUTSTANDING_WR,
GET_TX_MAX_CHUNK,
GET_TID_RANGE,
GET_STID_RANGE,
GET_RTBL_RANGE,
GET_L2T_CAPACITY,
GET_MTUS,
GET_WR_LEN,
GET_IFF_FROM_MAC,
GET_DDP_PARAMS,
GET_PORTS,
ULP_ISCSI_GET_PARAMS,
ULP_ISCSI_SET_PARAMS,
RDMA_GET_PARAMS,
RDMA_CQ_OP,
RDMA_CQ_SETUP,
RDMA_CQ_DISABLE,
RDMA_CTRL_QP_SETUP,
RDMA_GET_MEM,
FAILOVER = 30,
FAILOVER_DONE = 31,
FAILOVER_CLEAR = 32,
GET_CPUIDX_OF_QSET = 40,
GET_RX_PAGE_INFO = 50,
};
struct tid_range {
unsigned int base;
unsigned int num;
};
struct mtutab {
unsigned int size;
const unsigned short *mtus;
};
struct iff_mac {
if_t dev;
const unsigned char *mac_addr;
u16 vlan_tag;
};
struct pci_dev;
struct ddp_params {
unsigned int llimit;
unsigned int ulimit;
unsigned int tag_mask;
struct pci_dev *pdev;
};
struct adap_ports {
unsigned int nports;
if_t devs[MAX_NPORTS];
};
struct ulp_iscsi_info {
unsigned int offset;
unsigned int llimit;
unsigned int ulimit;
unsigned int tagmask;
unsigned int pgsz3;
unsigned int pgsz2;
unsigned int pgsz1;
unsigned int pgsz0;
unsigned int max_rxsz;
unsigned int max_txsz;
struct pci_dev *pdev;
};
struct ofld_page_info {
unsigned int page_size;
unsigned int num;
};
struct rdma_info {
unsigned int tpt_base;
unsigned int tpt_top;
unsigned int pbl_base;
unsigned int pbl_top;
unsigned int rqt_base;
unsigned int rqt_top;
unsigned int udbell_len;
unsigned long udbell_physbase;
void *kdb_addr;
device_t pdev;
};
struct rdma_cq_op {
unsigned int id;
unsigned int op;
unsigned int credits;
};
struct rdma_cq_setup {
unsigned int id;
unsigned long long base_addr;
unsigned int size;
unsigned int credits;
unsigned int credit_thres;
unsigned int ovfl_mode;
};
struct rdma_ctrlqp_setup {
unsigned long long base_addr;
unsigned int size;
};
#endif