#define MXGE_ETH_STOPPED 0
#define MXGE_ETH_STOPPING 1
#define MXGE_ETH_STARTING 2
#define MXGE_ETH_RUNNING 3
#define MXGE_ETH_OPEN_FAILED 4
#define MXGE_FW_OFFSET 1024*1024
#define MXGE_EEPROM_STRINGS_SIZE 256
#define MXGE_MAX_SEND_DESC 128
#ifndef VLAN_CAPABILITIES
#define VLAN_CAPABILITIES(ifp)
#define mxge_vlans_active(sc) (sc)->ifp->if_nvlans
#else
#define mxge_vlans_active(sc) if_getvlantrunk((sc)->ifp)
#endif
#ifndef VLAN_TAG_VALUE
#define MXGE_NEW_VLAN_API
#endif
#ifndef IFCAP_LRO
#define IFCAP_LRO 0
#endif
#ifndef IFCAP_TSO
#define IFCAP_TSO 0
#endif
#ifndef IFCAP_TSO4
#define IFCAP_TSO4 0
#endif
#ifndef IFCAP_TSO6
#define IFCAP_TSO6 0
#endif
#ifndef IFCAP_TXCSUM_IPV6
#define IFCAP_TXCSUM_IPV6 0
#endif
#ifndef IFCAP_RXCSUM_IPV6
#define IFCAP_RXCSUM_IPV6 0
#endif
#ifndef CSUM_TSO
#define CSUM_TSO 0
#endif
#ifndef CSUM_TCP_IPV6
#define CSUM_TCP_IPV6 0
#endif
#ifndef CSUM_UDP_IPV6
#define CSUM_UDP_IPV6 0
#endif
#ifndef CSUM_DELAY_DATA_IPV6
#define CSUM_DELAY_DATA_IPV6 0
#endif
typedef struct {
void *addr;
bus_addr_t bus_addr;
bus_dma_tag_t dmat;
bus_dmamap_t map;
} mxge_dma_t;
typedef struct {
mcp_slot_t *entry;
mxge_dma_t dma;
int cnt;
int idx;
int mask;
} mxge_rx_done_t;
typedef struct
{
uint32_t data0;
uint32_t data1;
uint32_t data2;
} mxge_cmd_t;
struct mxge_rx_buffer_state {
struct mbuf *m;
bus_dmamap_t map;
};
struct mxge_tx_buffer_state {
struct mbuf *m;
bus_dmamap_t map;
int flag;
};
typedef struct
{
volatile mcp_kreq_ether_recv_t *lanai;
mcp_kreq_ether_recv_t *shadow;
struct mxge_rx_buffer_state *info;
bus_dma_tag_t dmat;
bus_dmamap_t extra_map;
int cnt;
int nbufs;
int cl_size;
int alloc_fail;
int mask;
int mlen;
} mxge_rx_ring_t;
typedef struct
{
struct mtx mtx;
struct buf_ring *br;
volatile mcp_kreq_ether_send_t *lanai;
volatile uint32_t *send_go;
volatile uint32_t *send_stop;
mcp_kreq_ether_send_t *req_list;
char *req_bytes;
bus_dma_segment_t *seg_list;
struct mxge_tx_buffer_state *info;
bus_dma_tag_t dmat;
int req;
int mask;
int done;
int pkt_done;
int max_desc;
int queue_active;
int activate;
int deactivate;
int stall;
int wake;
int watchdog_req;
int watchdog_done;
int watchdog_rx_pause;
int defrag;
char mtx_name[16];
} mxge_tx_ring_t;
struct mxge_softc;
typedef struct mxge_softc mxge_softc_t;
struct mxge_slice_state {
mxge_softc_t *sc;
mxge_tx_ring_t tx;
mxge_rx_ring_t rx_small;
mxge_rx_ring_t rx_big;
mxge_rx_done_t rx_done;
mcp_irq_data_t *fw_stats;
volatile uint32_t *irq_claim;
u_long ipackets;
u_long opackets;
u_long obytes;
u_long omcasts;
u_long oerrors;
int if_drv_flags;
struct lro_ctrl lc;
mxge_dma_t fw_stats_dma;
struct sysctl_oid *sysctl_tree;
struct sysctl_ctx_list sysctl_ctx;
char scratch[256];
};
struct mxge_softc {
if_t ifp;
struct mxge_slice_state *ss;
int tx_boundary;
int lro_cnt;
bus_dma_tag_t parent_dmat;
volatile uint8_t *sram;
int sram_size;
volatile uint32_t *irq_deassert;
mcp_cmd_response_t *cmd;
mxge_dma_t cmd_dma;
mxge_dma_t zeropad_dma;
struct pci_dev *pdev;
int legacy_irq;
int link_state;
unsigned int rdma_tags_available;
int intr_coal_delay;
volatile uint32_t *intr_coal_delay_ptr;
int wc;
struct mtx cmd_mtx;
struct mtx driver_mtx;
int wake_queue;
int stop_queue;
int down_cnt;
int watchdog_resets;
int watchdog_countdown;
int pause;
struct resource *mem_res;
struct resource *irq_res;
struct resource **msix_irq_res;
struct resource *msix_table_res;
struct resource *msix_pba_res;
void *ih;
void **msix_ih;
char *fw_name;
char eeprom_strings[MXGE_EEPROM_STRINGS_SIZE];
char fw_version[128];
int fw_ver_major;
int fw_ver_minor;
int fw_ver_tiny;
int adopted_rx_filter_bug;
device_t dev;
struct ifmedia media;
int read_dma;
int write_dma;
int read_write_dma;
int fw_multicast_support;
int link_width;
int max_mtu;
int throttle;
int tx_defrag;
int media_flags;
int need_media_probe;
int num_slices;
int rx_ring_size;
int dying;
int connector;
int current_media;
int max_tso6_hlen;
mxge_dma_t dmabench_dma;
struct callout co_hdl;
struct taskqueue *tq;
struct task watchdog_task;
struct sysctl_oid *slice_sysctl_tree;
struct sysctl_ctx_list slice_sysctl_ctx;
char *mac_addr_string;
uint8_t mac_addr[6];
uint16_t pectl;
char product_code_string[64];
char serial_number_string[64];
char cmd_mtx_name[16];
char driver_mtx_name[16];
};
#define MXGE_PCI_VENDOR_MYRICOM 0x14c1
#define MXGE_PCI_DEVICE_Z8E 0x0008
#define MXGE_PCI_DEVICE_Z8E_9 0x0009
#define MXGE_PCI_REV_Z8E 0
#define MXGE_PCI_REV_Z8ES 1
#define MXGE_XFP_COMPLIANCE_BYTE 131
#define MXGE_SFP_COMPLIANCE_BYTE 3
#define MXGE_MIN_THROTTLE 416
#define MXGE_MAX_THROTTLE 4096
#define MXGE_CX4 0
#define MXGE_XFP 1
#define MXGE_SFP 2
#define MXGE_QRF 3
#define MXGE_HIGHPART_TO_U32(X) \
(sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0)
#define MXGE_LOWPART_TO_U32(X) ((uint32_t)(X))
struct mxge_media_type
{
int flag;
uint8_t bitmask;
char *name;
};
struct mxge_pkt_info {
int ip_off;
int ip_hlen;
struct ip *ip;
struct ip6_hdr *ip6;
struct tcphdr *tcp;
};
static inline void
mxge_pio_copy(volatile void *to_v, void *from_v, size_t size)
{
register volatile uintptr_t *to;
volatile uintptr_t *from;
size_t i;
to = (volatile uintptr_t *) to_v;
from = from_v;
for (i = (size / sizeof (uintptr_t)); i; i--) {
*to = *from;
to++;
from++;
}
}
void mxge_lro_flush(struct mxge_slice_state *ss, struct lro_entry *lro);
int mxge_lro_rx(struct mxge_slice_state *ss, struct mbuf *m_head,
uint32_t csum);