sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

247

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

249

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);

sys/dev/ath/ath_hal/ar5210/ar5210_attach.c

250

revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf;

sys/dev/ath/ath_hal/ar5210/ar5210_misc.c

385

nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;

sys/dev/ath/ath_hal/ar5210/ar5210phy.h

28

#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

195

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

197

OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

198

val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff;

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

288

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

290

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

321

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

326

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_attach.c

392

uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };

sys/dev/ath/ath_hal/ar5211/ar5211_misc.c

179

OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1240

OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1243

OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1244

(OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1246

OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1247

(OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1249

OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1250

(OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1253

OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1258

OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1259

(OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1261

OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2),

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1262

(OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) |

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

1478

addr = AR_PHY_BASE + (608 << 2);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

284

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007);

sys/dev/ath/ath_hal/ar5211/ar5211_reset.c

286

OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047);

sys/dev/ath/ath_hal/ar5211/ar5211phy.h

28

#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))

sys/dev/ath/ath_hal/ar5212/ar5212_attach.c

606

uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };

sys/dev/ath/ath_hal/ar5212/ar5212phy.h

24

#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))

sys/dev/ath/ath_hal/ar5416/ar5416_reset.c

2317

regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;

sys/dev/otus/if_otusreg.h

123

#define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)

sys/dev/otus/if_otusreg.h

124

#define AR_PHY_TURBO (AR_PHY_BASE + 0x0004)

sys/dev/otus/if_otusreg.h

125

#define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028)

sys/dev/otus/if_otusreg.h

126

#define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034)

sys/dev/otus/if_otusreg.h

127

#define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044)

sys/dev/otus/if_otusreg.h

128

#define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048)

sys/dev/otus/if_otusreg.h

129

#define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050)

sys/dev/otus/if_otusreg.h

130

#define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058)

sys/dev/otus/if_otusreg.h

131

#define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c)

sys/dev/otus/if_otusreg.h

132

#define AR_PHY_SFCORR (AR_PHY_BASE + 0x0068)

sys/dev/otus/if_otusreg.h

133

#define AR_PHY_SFCORR_LOW (AR_PHY_BASE + 0x006c)

sys/dev/otus/if_otusreg.h

134

#define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120)

sys/dev/otus/if_otusreg.h

135

#define AR_PHY_TIMING5 (AR_PHY_BASE + 0x0124)

sys/dev/otus/if_otusreg.h

136

#define AR_PHY_POWER_TX_RATE1 (AR_PHY_BASE + 0x0134)

sys/dev/otus/if_otusreg.h

137

#define AR_PHY_POWER_TX_RATE2 (AR_PHY_BASE + 0x0138)

sys/dev/otus/if_otusreg.h

138

#define AR_PHY_POWER_TX_RATE_MAX (AR_PHY_BASE + 0x013c)

sys/dev/otus/if_otusreg.h

139

#define AR_PHY_SWITCH_CHAIN_0 (AR_PHY_BASE + 0x0160)

sys/dev/otus/if_otusreg.h

140

#define AR_PHY_SWITCH_COM (AR_PHY_BASE + 0x0164)

sys/dev/otus/if_otusreg.h

141

#define AR_PHY_HEAVY_CLIP_ENABLE (AR_PHY_BASE + 0x01e0)

sys/dev/otus/if_otusreg.h

142

#define AR_PHY_CCK_DETECT (AR_PHY_BASE + 0x0a08)

sys/dev/otus/if_otusreg.h

143

#define AR_PHY_GAIN_2GHZ (AR_PHY_BASE + 0x0a0c)

sys/dev/otus/if_otusreg.h

144

#define AR_PHY_POWER_TX_RATE3 (AR_PHY_BASE + 0x0a34)

sys/dev/otus/if_otusreg.h

145

#define AR_PHY_POWER_TX_RATE4 (AR_PHY_BASE + 0x0a38)

sys/dev/otus/if_otusreg.h

146

#define AR_PHY_TPCRG1 (AR_PHY_BASE + 0x0a58)

sys/dev/otus/if_otusreg.h

147

#define AR_PHY_POWER_TX_RATE5 (AR_PHY_BASE + 0x0b8c)

sys/dev/otus/if_otusreg.h

148

#define AR_PHY_POWER_TX_RATE6 (AR_PHY_BASE + 0x0b90)

sys/dev/otus/if_otusreg.h

149

#define AR_PHY_POWER_TX_RATE7 (AR_PHY_BASE + 0x0bcc)

sys/dev/otus/if_otusreg.h

150

#define AR_PHY_POWER_TX_RATE8 (AR_PHY_BASE + 0x0bd0)

sys/dev/otus/if_otusreg.h

151

#define AR_PHY_POWER_TX_RATE9 (AR_PHY_BASE + 0x0bd4)

sys/dev/otus/if_otusreg.h

152

#define AR_PHY_CCA (AR_PHY_BASE + 0x3064)

tools/tools/ath/athdecode/main.c

400

} else if (AR_PHY_BASE <= r->reg) {

tools/tools/ath/athdecode/main.c

402

(r->reg - AR_PHY_BASE) >> 2, r->reg);