sys/dev/uart/uart_dev_imx.c

100

GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),

sys/dev/uart/uart_dev_imx.c

101

GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));

sys/dev/uart/uart_dev_imx.c

131

i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >>

sys/dev/uart/uart_dev_imx.c

134

ubir = GETREG(bas, REG(UBIR)) + 1;

sys/dev/uart/uart_dev_imx.c

135

ubmr = GETREG(bas, REG(UBMR)) + 1;

sys/dev/uart/uart_dev_imx.c

203

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

215

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

253

c = GETREG(bas, REG(URXD));

sys/dev/uart/uart_dev_imx.c

455

bes = GETREG(&sc->sc_bas, REG(USR2));

sys/dev/uart/uart_dev_imx.c

504

usr1 = GETREG(bas, REG(USR1));

sys/dev/uart/uart_dev_imx.c

505

usr2 = GETREG(bas, REG(USR2));

sys/dev/uart/uart_dev_imx.c

510

ucr1 = GETREG(bas, REG(UCR1));

sys/dev/uart/uart_dev_imx.c

511

ucr2 = GETREG(bas, REG(UCR2));

sys/dev/uart/uart_dev_imx.c

512

ucr4 = GETREG(bas, REG(UCR4));

sys/dev/uart/uart_dev_imx.c

595

xc = GETREG(bas, REG(URXD));

sys/dev/uart/uart_dev_imx.c

99

GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),

sys/dev/uart/uart_dev_imx.h

207

SETREG((_bas), (_r), GETREG((_bas), (_r)) & ~(_b))

sys/dev/uart/uart_dev_imx.h

209

SETREG((_bas), (_r), GETREG((_bas), (_r)) | (_b))

sys/dev/uart/uart_dev_imx.h

211

((GETREG((_bas), (_r)) & (_b)) ? 1 : 0)

sys/dev/uart/uart_dev_lowrisc.c

107

while (GETREG(bas, UART_DR) & DR_TX_FIFO_FULL)

sys/dev/uart/uart_dev_lowrisc.c

117

if (GETREG(bas, UART_DR) & DR_RX_FIFO_EMPTY)

sys/dev/uart/uart_dev_lowrisc.c

130

reg = GETREG(bas, UART_DR);

sys/dev/uart/uart_dev_lowrisc.c

274

if ((GETREG(bas, UART_DR) & DR_RX_FIFO_EMPTY) == 0)

sys/dev/uart/uart_dev_lowrisc.c

333

reg = GETREG(bas, UART_DR);

sys/dev/uart/uart_dev_lowrisc.c

360

while (GETREG(bas, UART_DR) & DR_TX_FIFO_FULL)

sys/dev/uart/uart_dev_msm.c

461

isr = GETREG(bas, UART_DM_MISR);

usr.sbin/bhyve/amd64/task_switch.c

340

sel = GETREG(vcpu, segment);

usr.sbin/bhyve/amd64/task_switch.c

395

cs = GETREG(vcpu, VM_REG_GUEST_CS);

usr.sbin/bhyve/amd64/task_switch.c

439

tss->tss_eax = GETREG(vcpu, VM_REG_GUEST_RAX);

usr.sbin/bhyve/amd64/task_switch.c

440

tss->tss_ecx = GETREG(vcpu, VM_REG_GUEST_RCX);

usr.sbin/bhyve/amd64/task_switch.c

441

tss->tss_edx = GETREG(vcpu, VM_REG_GUEST_RDX);

usr.sbin/bhyve/amd64/task_switch.c

442

tss->tss_ebx = GETREG(vcpu, VM_REG_GUEST_RBX);

usr.sbin/bhyve/amd64/task_switch.c

443

tss->tss_esp = GETREG(vcpu, VM_REG_GUEST_RSP);

usr.sbin/bhyve/amd64/task_switch.c

444

tss->tss_ebp = GETREG(vcpu, VM_REG_GUEST_RBP);

usr.sbin/bhyve/amd64/task_switch.c

445

tss->tss_esi = GETREG(vcpu, VM_REG_GUEST_RSI);

usr.sbin/bhyve/amd64/task_switch.c

446

tss->tss_edi = GETREG(vcpu, VM_REG_GUEST_RDI);

usr.sbin/bhyve/amd64/task_switch.c

449

tss->tss_es = GETREG(vcpu, VM_REG_GUEST_ES);

usr.sbin/bhyve/amd64/task_switch.c

450

tss->tss_cs = GETREG(vcpu, VM_REG_GUEST_CS);

usr.sbin/bhyve/amd64/task_switch.c

451

tss->tss_ss = GETREG(vcpu, VM_REG_GUEST_SS);

usr.sbin/bhyve/amd64/task_switch.c

452

tss->tss_ds = GETREG(vcpu, VM_REG_GUEST_DS);

usr.sbin/bhyve/amd64/task_switch.c

453

tss->tss_fs = GETREG(vcpu, VM_REG_GUEST_FS);

usr.sbin/bhyve/amd64/task_switch.c

454

tss->tss_gs = GETREG(vcpu, VM_REG_GUEST_GS);

usr.sbin/bhyve/amd64/task_switch.c

457

tss->tss_eflags = GETREG(vcpu, VM_REG_GUEST_RFLAGS);

usr.sbin/bhyve/amd64/task_switch.c

635

cr0 = GETREG(vcpu, VM_REG_GUEST_CR0);

usr.sbin/bhyve/amd64/task_switch.c

636

rflags = GETREG(vcpu, VM_REG_GUEST_RFLAGS);

usr.sbin/bhyve/amd64/task_switch.c

637

stacksel = GETREG(vcpu, VM_REG_GUEST_SS);

usr.sbin/bhyve/amd64/task_switch.c

663

esp = GETREG(vcpu, VM_REG_GUEST_RSP);

usr.sbin/bhyve/amd64/task_switch.c

803

ot_sel = GETREG(vcpu, VM_REG_GUEST_TR);

usr.sbin/bhyve/amd64/task_switch.c

872

cr0 = GETREG(vcpu, VM_REG_GUEST_CR0);