sys/dev/sfxge/common/ef10_phy.c

392

PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,

sys/dev/sfxge/common/ef10_phy.c

97

mask |= (1 << EFX_PHY_CAP_ASYM);

sys/dev/sfxge/common/efx_mac.c

343

1 << EFX_PHY_CAP_ASYM);

sys/dev/sfxge/common/efx_mac.c

346

1 << EFX_PHY_CAP_ASYM);

sys/dev/sfxge/common/efx_mac.c

349

epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);

sys/dev/sfxge/common/efx_mac.c

393

if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))

sys/dev/sfxge/common/siena_phy.c

299

PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,

sys/dev/sfxge/common/siena_phy.c

64

mask |= (1 << EFX_PHY_CAP_ASYM);

sys/dev/sfxge/sfxge_port.c

947

*phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM));

sys/dev/sfxge/sfxge_port.c

965

mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM);