sys/dev/sfxge/common/ef10_phy.c

393

PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);

sys/dev/sfxge/common/ef10_phy.c

99

mask |= (1 << EFX_PHY_CAP_AN);

sys/dev/sfxge/common/efx_mac.c

326

if (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))

sys/dev/sfxge/common/siena_phy.c

163

if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))

sys/dev/sfxge/common/siena_phy.c

300

PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);

sys/dev/sfxge/common/siena_phy.c

66

mask |= (1 << EFX_PHY_CAP_AN);

sys/dev/sfxge/sfxge_port.c

1078

if (cap_mask & (1 << EFX_PHY_CAP_AN)) {

sys/dev/sfxge/sfxge_port.c

944

KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) &&

sys/dev/sfxge/sfxge_port.c

960

mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN);