sys/arm/nvidia/tegra124/tegra124_clk_pll.c

508

val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

509

val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

510

val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

733

reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

734

reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

735

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

920

reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

921

reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

922

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1154

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1191

reg = set_masked(reg, n, mnp_bits->n_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1209

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

701

val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

702

val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

703

val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

931

reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

932

reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

933

reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,