bin/sh/eval.c

1019

shellparam.reset = 1;

bin/sh/eval.c

495

saveoptreset = shellparam.reset;

bin/sh/eval.c

510

shellparam.reset = saveoptreset;

bin/sh/eval.c

659

saveoptreset = shellparam.reset;

bin/sh/eval.c

670

shellparam.reset = saveoptreset;

bin/sh/eval.c

681

shellparam.reset = saveoptreset;

bin/sh/main.c

107

reset();

bin/sh/main.c

73

static void reset(void);

bin/sh/options.c

116

shellparam.reset = 1;

bin/sh/options.c

337

shellparam.reset = 1;

bin/sh/options.c

386

shellparam.reset = 1;

bin/sh/options.c

419

shellparam.reset = 1;

bin/sh/options.c

438

if (shellparam.reset == 1) {

bin/sh/options.c

456

shellparam.reset = 0;

bin/sh/options.h

38

unsigned char reset; /* if getopts has been reset */

crypto/heimdal/appl/ftp/ftp/cmdtab.c

171

{ "reset", resethelp, 0, 1, 1, reset },

crypto/heimdal/appl/ftp/ftp/extern.h

116

void reset (int, char **);

crypto/krb5/src/include/net-server.h

68

void (*reset)(void *));

crypto/krb5/src/kprop/kproplog.c

432

bool_t headeronly = FALSE, reset = FALSE;

crypto/krb5/src/kprop/kproplog.c

451

reset = TRUE;

crypto/krb5/src/kprop/kproplog.c

475

if (reset) {

crypto/krb5/src/lib/apputils/net-server.c

242

void (*reset)(void *);

crypto/krb5/src/lib/apputils/net-server.c

252

if (sc->reset)

crypto/krb5/src/lib/apputils/net-server.c

253

sc->reset(sc->handle);

crypto/krb5/src/lib/apputils/net-server.c

263

loop_setup_signals(verto_ctx *ctx, void *handle, void (*reset)(void *))

crypto/krb5/src/lib/apputils/net-server.c

283

sc->reset = reset;

crypto/openssl/crypto/evp/kdf_lib.c

116

if (ctx->meth->reset != NULL)

crypto/openssl/crypto/evp/kdf_lib.c

117

ctx->meth->reset(ctx->algctx);

crypto/openssl/crypto/evp/kdf_meth.c

96

if (kdf->reset != NULL)

crypto/openssl/crypto/evp/kdf_meth.c

98

kdf->reset = OSSL_FUNC_kdf_reset(fns);

crypto/openssl/crypto/hmac/hmac.c

100

if (reset) {

crypto/openssl/crypto/hmac/hmac.c

28

int rv = 0, reset = 0;

crypto/openssl/crypto/hmac/hmac.c

59

reset = 1;

crypto/openssl/include/crypto/evp.h

242

OSSL_FUNC_kdf_reset_fn *reset;

crypto/openssl/include/internal/quic_cc.h

94

void (*reset)(OSSL_CC_DATA *ccdata);

crypto/openssl/ssl/record/rec_layer_d1.c

283

* reset by ssl3_get_finished */

crypto/openssl/ssl/record/rec_layer_s3.c

733

* reset by ssl3_get_finished */

crypto/openssl/test/quic_cc_test.c

371

ccm->reset(cc);

crypto/openssl/test/quic_cc_test.c

508

ccm->reset(cc);

lib/clang/liblldb/LLDBWrapLua.cpp

3015

void reset(T *p) { T* oldptr = ptr; ptr = 0; delete oldptr; ptr = p; }

lib/clang/liblldb/LLDBWrapLua.cpp

3029

static void reset(SwigValueWrapper& t, T *p) { t.pointer.reset(p); }

lib/libutil++/libutil++.hh

101

reset(other.release());

lib/libutil++/libutil++.hh

109

reset(newfd);

lib/libutil++/libutil++.hh

166

~pidfile() { reset(); }

lib/libutil++/libutil++.hh

205

reset(other.release());

lib/libutil++/libutil++.hh

213

reset(newpfh);

lib/libutil++/libutil++.hh

77

~fd_up() { reset(); }

lib/libutil++/stringf.cc

41

fp.reset(nullptr);

lib/libutil++/tests/up_test.cc

23

f.reset();

sbin/bectl/bectl.c

122

bool temp, reset;

sbin/bectl/bectl.c

125

reset = false;

sbin/bectl/bectl.c

129

if (reset)

sbin/bectl/bectl.c

136

reset = true;

sbin/bectl/bectl.c

148

if (argc != 1 && (!reset || argc != 0)) {

sbin/bectl/bectl.c

153

if (reset) {

sbin/bectl/bectl.c

154

if ((err = be_deactivate(be, NULL, reset)) == 0)

sbin/devd/devd.hh

147

virtual ~config() { reset(); }

sbin/devd/devd.hh

154

void reset();

sbin/nvmecontrol/reset.c

78

.fn = reset,

sbin/restore/interactive.c

107

if (setjmp(reset) != 0) {

sbin/restore/interactive.c

55

static jmp_buf reset;

sbin/restore/interactive.c

758

longjmp(reset, 1);

sys/arm/allwinner/aw_reset.c

101

*reset = (reg_value & (1 << RESET_SHIFT(id))) != 0 ? false : true;

sys/arm/allwinner/aw_reset.c

70

aw_reset_assert(device_t dev, intptr_t id, bool reset)

sys/arm/allwinner/aw_reset.c

79

if (reset)

sys/arm/allwinner/aw_reset.c

90

aw_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/arm/nvidia/drm2/tegra_host1x.c

103

hwreset_t reset;

sys/arm/nvidia/drm2/tegra_host1x.c

478

rv = hwreset_get_by_ofw_name(sc->dev, 0, "host1x", &sc->reset);

sys/arm/nvidia/drm2/tegra_host1x.c

494

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/drm2/tegra_host1x.c

606

if (sc->reset != NULL)

sys/arm/nvidia/drm2/tegra_host1x.c

607

hwreset_release(sc->reset);

sys/arm/nvidia/tegra124/tegra124_car.h

332

bool reset);

sys/arm/nvidia/tegra124/tegra124_clk_per.c

791

tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)

sys/arm/nvidia/tegra124/tegra124_clk_per.c

799

CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);

sys/arm/nvidia/tegra_efuse.c

467

rv = hwreset_get_by_ofw_name(sc->dev, 0, "fuse", &sc->reset);

sys/arm/nvidia/tegra_efuse.c

472

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_efuse.c

491

if (sc->reset != NULL)

sys/arm/nvidia/tegra_efuse.c

492

hwreset_release(sc->reset);

sys/arm/nvidia/tegra_efuse.c

513

if (sc->reset != NULL)

sys/arm/nvidia/tegra_efuse.c

514

hwreset_release(sc->reset);

sys/arm/nvidia/tegra_efuse.c

59

hwreset_t reset;

sys/arm/nvidia/tegra_ehci.c

175

rv = hwreset_get_by_ofw_name(dev, 0, "usb", &sc->reset);

sys/arm/nvidia/tegra_ehci.c

208

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_ehci.c

81

hwreset_t reset;

sys/arm/nvidia/tegra_i2c.c

225

hwreset_t reset;

sys/arm/nvidia/tegra_i2c.c

320

rv = hwreset_assert(sc->reset);

sys/arm/nvidia/tegra_i2c.c

326

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_i2c.c

671

rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset);

sys/arm/nvidia/tegra_sdhci.c

109

hwreset_t reset;

sys/arm/nvidia/tegra_sdhci.c

290

rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);

sys/arm/nvidia/tegra_sdhci.c

295

rv = hwreset_assert(sc->reset);

sys/arm/nvidia/tegra_sdhci.c

332

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_sdhci.c

405

if (sc->reset != NULL)

sys/arm/nvidia/tegra_sdhci.c

406

hwreset_release(sc->reset);

sys/arm/nvidia/tegra_soctherm.c

174

hwreset_t reset;

sys/arm/nvidia/tegra_soctherm.c

731

rv = hwreset_get_by_ofw_name(dev, 0, "soctherm", &sc->reset);

sys/arm/nvidia/tegra_soctherm.c

747

rv = hwreset_assert(sc->reset);

sys/arm/nvidia/tegra_soctherm.c

762

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_soctherm.c

794

if (sc->reset != NULL)

sys/arm/nvidia/tegra_soctherm.c

795

hwreset_release(sc->reset);

sys/arm/nvidia/tegra_soctherm.c

817

if (sc->reset != NULL)

sys/arm/nvidia/tegra_soctherm.c

818

hwreset_release(sc->reset);

sys/arm/nvidia/tegra_uart.c

193

rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset);

sys/arm/nvidia/tegra_uart.c

198

rv = hwreset_deassert(sc->reset);

sys/arm/nvidia/tegra_uart.c

61

hwreset_t reset;

sys/arm/ti/am335x/am335x_pmic.c

171

device_printf(dev, " Charger reset: %s\n", i_a[reg1.reset]);

sys/arm/ti/am335x/tps65217x.h

85

unsigned int reset:1;

sys/arm64/nvidia/tegra210/tegra210_car.h

524

bool reset);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

906

tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx, bool reset)

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

913

reset ? DFLL_BASE_DVFS_DFLL_RESET : 0);

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

917

reset_reg = (reset) ? RST_DEV_Y_SET: RST_DEV_Y_CLR;

sys/arm64/nvidia/tegra210/tegra210_clk_per.c

925

CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

1705

&pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

422

hwreset_t reset;

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

562

rv = hwreset_deassert(pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

740

hwreset_deassert(pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

752

rv = hwreset_assert(pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

786

rv = hwreset_deassert(pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

972

hwreset_deassert(pad->reset);

sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c

984

rv = hwreset_assert(pad->reset);

sys/cam/ata/ata_pmp.c

100

int reset;

sys/cam/ata/ata_pmp.c

550

softc->reset = 0;

sys/cam/ata/ata_pmp.c

703

softc->reset |= ~softc->found;

sys/cam/ata/ata_pmp.c

797

if (softc->reset & softc->found) {

sys/cam/ata/ata_pmp.c

833

if ((softc->reset & softc->found & (1 << i)) != 0)

sys/compat/linuxkpi/common/include/linux/platform_data/brcmfmac.h

100

void (*reset)(void);

sys/dev/ahci/ahci.c

1377

int i, ccs, port, reset = 0;

sys/dev/ahci/ahci.c

1416

reset = ahci_phy_check_events(ch, serr);

sys/dev/ahci/ahci.c

1420

if ((istatus & AHCI_P_IX_CPD) && !reset)

sys/dev/al_eth/al_init_eth_lm.c

216

int (*reset)(struct al_eth_lm_context *lm_context, uint32_t channel);

sys/dev/al_eth/al_init_eth_lm.c

224

.reset = NULL, .cdr_lock = NULL, .rx_adaptation = NULL},

sys/dev/al_eth/al_init_eth_lm.c

226

.reset = NULL, .cdr_lock = NULL, .rx_adaptation = NULL},

sys/dev/al_eth/al_init_eth_lm.c

229

.reset = al_eth_lm_retimer_ds25_cdr_reset,

sys/dev/al_eth/al_init_eth_lm.c

947

if (retimer[lm_context->retimer_type].reset) {

sys/dev/al_eth/al_init_eth_lm.c

948

retimer[lm_context->retimer_type].reset(lm_context,

sys/dev/aq/aq_fw.h

62

int (*reset)(struct aq_hw* hal);

sys/dev/aq/aq_fw1x.c

316

.reset = fw1x_reset,

sys/dev/aq/aq_fw2x.c

514

.reset = fw2x_reset,

sys/dev/aq/aq_hw.c

382

if (hw->fw_ops && hw->fw_ops->reset)

sys/dev/aq/aq_hw.c

383

hw->fw_ops->reset(hw);

sys/dev/aq/aq_main.c

371

if (hw->fw_ops && hw->fw_ops->reset)

sys/dev/aq/aq_main.c

372

hw->fw_ops->reset(hw);

sys/dev/ata/ata-all.h

366

void (*reset)(device_t dev);

sys/dev/ata/ata-pci.c

535

ch->dma.reset = ata_pci_dmareset;

sys/dev/ata/ata-pci.c

706

if (ch->dma.reset)

sys/dev/ata/ata-pci.c

707

ch->dma.reset(dev);

sys/dev/ata/ata-pci.c

710

if (ctlr->reset)

sys/dev/ata/ata-pci.c

711

ctlr->reset(dev);

sys/dev/ata/ata-pci.h

65

void (*reset)(device_t);

sys/dev/ata/chipsets/ata-acerlabs.c

157

ctlr->reset = ata_ali_reset;

sys/dev/ata/chipsets/ata-intel.c

237

ctlr->reset = ata_intel_31244_reset;

sys/dev/ata/chipsets/ata-intel.c

264

ctlr->reset = ata_intel_reset;

sys/dev/ata/chipsets/ata-jmicron.c

103

ctlr->reset = ata_generic_reset;

sys/dev/ata/chipsets/ata-jmicron.c

121

ctlr->reset = ata_generic_reset;

sys/dev/ata/chipsets/ata-marvell.c

136

ctlr->reset = ata_generic_reset;

sys/dev/ata/chipsets/ata-nvidia.c

210

ctlr->reset = ata_nvidia_reset;

sys/dev/ata/chipsets/ata-promise.c

289

ctlr->reset = ata_promise_mio_reset;

sys/dev/ata/chipsets/ata-promise.c

340

ctlr->reset = ata_promise_mio_reset;

sys/dev/ata/chipsets/ata-promise.c

367

ch->dma.reset = ata_promise_dmareset;

sys/dev/ata/chipsets/ata-serverworks.c

142

ctlr->reset = ata_serverworks_sata_reset;

sys/dev/ata/chipsets/ata-siliconimage.c

149

ctlr->reset = ata_sii_reset;

sys/dev/ata/chipsets/ata-sis.c

188

ctlr->reset = ata_sis_reset;

sys/dev/ata/chipsets/ata-via.c

157

ctlr->reset = ata_via_sata_reset;

sys/dev/ata/chipsets/ata-via.c

168

ctlr->reset = ata_via_reset;

sys/dev/axgbe/xgbe-mdio.c

1511

ret = pdata->phy_if.phy_impl.reset(pdata);

sys/dev/axgbe/xgbe-phy-v1.c

680

phy_impl->reset = xgbe_phy_reset;

sys/dev/axgbe/xgbe-phy-v2.c

4039

phy_impl->reset = xgbe_phy_reset;

sys/dev/axgbe/xgbe.h

849

int (*reset)(struct xgbe_prv_data *);

sys/dev/bge/if_bge.c

4011

uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;

sys/dev/bge/if_bge.c

4072

reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;

sys/dev/bge/if_bge.c

4084

reset |= 1 << 29;

sys/dev/bge/if_bge.c

4103

reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;

sys/dev/bge/if_bge.c

4106

write_op(sc, BGE_MISC_CFG, reset);

sys/dev/bnxt/bnxt_en/bnxt_ioctl.h

176

struct bnxt_ioctl_hwrm_fw_reset reset;

sys/dev/bnxt/bnxt_en/if_bnxt.c

4071

&iod->reset;

sys/dev/bnxt/bnxt_re/bnxt_re.h

946

int bnxt_re_setup_cnp_cos(struct bnxt_re_dev *rdev, bool reset);

sys/dev/bxe/bxe_elink.c

5109

uint8_t reset)

sys/dev/bxe/bxe_elink.c

5115

if (reset)

sys/dev/clk/allwinner/aw_ccung.c

117

aw_ccung_reset_assert(device_t dev, intptr_t id, bool reset)

sys/dev/clk/allwinner/aw_ccung.c

124

dprintf("%sassert reset id %ld\n", reset ? "" : "De", id);

sys/dev/clk/allwinner/aw_ccung.c

131

if (reset)

sys/dev/clk/allwinner/aw_ccung.c

143

aw_ccung_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/clk/allwinner/aw_ccung.c

156

*reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true;

sys/dev/clk/rockchip/rk_cru.c

110

rk_cru_reset_assert(device_t dev, intptr_t id, bool reset)

sys/dev/clk/rockchip/rk_cru.c

127

if (reset)

sys/dev/clk/rockchip/rk_cru.c

136

rk_cru_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/clk/rockchip/rk_cru.c

154

*reset = false;

sys/dev/clk/rockchip/rk_cru.c

156

*reset = true;

sys/dev/clk/starfive/jh7110_clk.c

82

jh7110_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/clk/starfive/jh7110_clk.c

97

*reset = (regvalue & bitmask) == 0;

sys/dev/clk/starfive/jh7110_clk.h

69

int jh7110_reset_is_asserted(device_t dev, intptr_t id, bool *reset);

sys/dev/clk/xilinx/zynqmp_reset.c

178

zynqmp_reset_assert(device_t dev, intptr_t id, bool reset)

sys/dev/clk/xilinx/zynqmp_reset.c

186

rv = ZYNQMP_FIRMWARE_RESET_ASSERT(sc->parent, id, reset);

sys/dev/clk/xilinx/zynqmp_reset.c

191

zynqmp_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/clk/xilinx/zynqmp_reset.c

199

rv = ZYNQMP_FIRMWARE_RESET_GET_STATUS(sc->parent, id, reset);

sys/dev/cxgb/common/cxgb_ael1002.c

1373

.reset = ael2005_reset,

sys/dev/cxgb/common/cxgb_ael1002.c

2125

.reset = ael2020_reset,

sys/dev/cxgb/common/cxgb_ael1002.c

2204

.reset = ael1006_reset,

sys/dev/cxgb/common/cxgb_ael1002.c

2285

.reset = xaui_direct_reset,

sys/dev/cxgb/common/cxgb_ael1002.c

333

.reset = ael1002_reset,

sys/dev/cxgb/common/cxgb_ael1002.c

415

.reset = ael1006_reset,

sys/dev/cxgb/common/cxgb_aq100x.c

448

.reset = aq100x_reset,

sys/dev/cxgb/common/cxgb_common.h

553

int (*reset)(struct cphy *phy, int wait);

sys/dev/cxgb/common/cxgb_common.h

731

int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);

sys/dev/cxgb/common/cxgb_mv88e1xxx.c

282

.reset = mv88e1xxx_reset,

sys/dev/cxgb/common/cxgb_t3_hw.c

1538

phy->ops->reset(phy, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

1702

phy->ops->reset(phy, 0);

sys/dev/cxgb/common/cxgb_t3_hw.c

4459

const struct adapter_info *ai, int reset)

sys/dev/cxgb/common/cxgb_t3_hw.c

4493

if (reset && t3_reset_adapter(adapter))

sys/dev/cxgb/common/cxgb_tn1010.c

198

.reset = tn1010_reset,

sys/dev/cxgb/common/cxgb_vsc8211.c

352

.reset = vsc8211_reset,

sys/dev/cxgb/common/cxgb_vsc8211.c

366

.reset = vsc8211_reset,

sys/dev/cxgb/cxgb_main.c

2340

uint32_t cause, reset;

sys/dev/cxgb/cxgb_main.c

2390

reset = 0;

sys/dev/cxgb/cxgb_main.c

2393

reset |= F_RXFIFO_OVERFLOW;

sys/dev/cxgb/cxgb_main.c

2395

t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset);

sys/dev/cxgbe/common/common.h

891

int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);

sys/dev/cxgbe/common/t4_hw.c

9415

int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)

sys/dev/cxgbe/common/t4_hw.c

9421

c.val = cpu_to_be32(reset);

sys/dev/cxgbe/tom/t4_listen.c

1657

reset:

sys/dev/cxgbe/tom/t4_listen.c

1672

goto reset;

sys/dev/cxgbe/tom/t4_listen.c

1691

goto reset; /* RST without a CLIP entry? */

sys/dev/cxgbe/tom/t4_listen.c

1711

goto reset;

sys/dev/drm2/drm_crtc.c

3629

if (crtc->funcs->reset)

sys/dev/drm2/drm_crtc.c

3630

crtc->funcs->reset(crtc);

sys/dev/drm2/drm_crtc.c

3633

if (encoder->funcs->reset)

sys/dev/drm2/drm_crtc.c

3634

encoder->funcs->reset(encoder);

sys/dev/drm2/drm_crtc.c

3639

if (connector->funcs->reset)

sys/dev/drm2/drm_crtc.c

3640

connector->funcs->reset(connector);

sys/dev/drm2/drm_crtc.h

327

void (*reset)(struct drm_crtc *crtc);

sys/dev/drm2/drm_crtc.h

442

void (*reset)(struct drm_connector *connector);

sys/dev/drm2/drm_crtc.h

467

void (*reset)(struct drm_encoder *encoder);

sys/dev/e1000/e1000_80003es2lan.c

114

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82540.c

83

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82541.c

104

phy->ops.reset = e1000_phy_hw_reset_82541;

sys/dev/e1000/e1000_82543.c

1078

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_82543.c

113

phy->ops.reset = (hw->mac.type == e1000_82543)

sys/dev/e1000/e1000_82543.c

127

ret_val = phy->ops.reset(hw);

sys/dev/e1000/e1000_82571.c

108

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_82575.c

1437

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_82575.c

189

phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;

sys/dev/e1000/e1000_82575.c

192

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/e1000/e1000_api.c

1178

if (hw->phy.ops.reset)

sys/dev/e1000/e1000_api.c

1179

return hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_hw.h

801

s32 (*reset)(struct e1000_hw *);

sys/dev/e1000/e1000_ich8lan.c

1540

hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_ich8lan.c

475

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/e1000/e1000_ich8lan.c

5532

hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_ich8lan.c

569

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/e1000/e1000_phy.c

1062

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_phy.c

1379

ret_val = hw->phy.ops.reset(hw);

sys/dev/e1000/e1000_phy.c

90

phy->ops.reset = e1000_null_ops_generic;

sys/dev/enic/vnic_dev.c

1168

bool reset, uint64_t *packets, uint64_t *bytes)

sys/dev/enic/vnic_dev.c

1171

u64 a1 = reset ? 1 : 0;

sys/dev/enic/vnic_dev.c

1174

if (reset) {

sys/dev/enic/vnic_dev.h

170

bool reset, uint64_t *packets, uint64_t *bytes);

sys/dev/fb/vesa.c

671

int reset;

sys/dev/fb/vesa.c

683

ftable[i].set : ftable[i].reset;

sys/dev/gve/gve_main.c

200

goto reset;

sys/dev/gve/gve_main.c

205

goto reset;

sys/dev/gve/gve_main.c

209

goto reset;

sys/dev/gve/gve_main.c

226

reset:

sys/dev/gve/gve_main.c

249

goto reset;

sys/dev/gve/gve_main.c

252

goto reset;

sys/dev/gve/gve_main.c

256

goto reset;

sys/dev/gve/gve_main.c

265

reset:

sys/dev/hpt27xx/ldm.h

312

void (*reset)(PVDEV vd);

sys/dev/hptnr/ldm.h

311

void (*reset)(PVDEV vd);

sys/dev/hptrr/ldm.h

306

void (*reset)(PVDEV vd);

sys/dev/ice/ice_lib.c

6386

char reset[6] = "";

sys/dev/ice/ice_lib.c

6398

ret = sysctl_handle_string(oidp, reset, sizeof(reset), req);

sys/dev/ice/ice_lib.c

6402

if (strcmp(reset, "pfr") == 0) {

sys/dev/ice/ice_lib.c

6405

} else if (strcmp(reset, "corer") == 0) {

sys/dev/ice/ice_lib.c

6408

} else if (strcmp(reset, "globr") == 0) {

sys/dev/ice/ice_lib.c

6411

} else if (strcmp(reset, "empr") == 0) {

sys/dev/ice/ice_lib.c

6417

device_printf(sc->dev, "%s is not a valid reset request\n", reset);

sys/dev/ice/if_ice_iflib.c

1336

u32 reset;

sys/dev/ice/if_ice_iflib.c

1338

reset = (rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_RESET_TYPE_M) >>

sys/dev/ice/if_ice_iflib.c

1341

if (reset == ICE_RESET_CORER)

sys/dev/ice/if_ice_iflib.c

1343

else if (reset == ICE_RESET_GLOBR)

sys/dev/ichiic/ig4_iic.c

137

static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);

sys/dev/ichiic/ig4_iic.c

913

ig4iic_set_config(ig4iic_softc_t *sc, bool reset)

sys/dev/ichiic/ig4_iic.c

922

reset = true;

sys/dev/ichiic/ig4_iic.c

925

if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {

sys/dev/ichiic/ig4_iic.c

928

} else if (IG4_HAS_ADDREGS(sc->version) && reset) {

sys/dev/igc/igc_api.c

532

if (hw->phy.ops.reset)

sys/dev/igc/igc_api.c

533

return hw->phy.ops.reset(hw);

sys/dev/igc/igc_hw.h

391

s32 (*reset)(struct igc_hw *);

sys/dev/igc/igc_i225.c

156

phy->ops.reset = igc_phy_hw_reset_generic;

sys/dev/igc/igc_i225.c

165

ret_val = hw->phy.ops.reset(hw);

sys/dev/igc/igc_phy.c

34

phy->ops.reset = igc_null_ops_generic;

sys/dev/irdma/icrdma.c

365

iwdev->rf->reset = true;

sys/dev/irdma/icrdma.c

373

iwdev->rf->reset = true;

sys/dev/irdma/icrdma.c

375

if (iwdev->rf->reset)

sys/dev/irdma/icrdma.c

379

iwdev->rf->reset = true;

sys/dev/irdma/icrdma.c

747

if (iwdev && iwdev->rf->reset)

sys/dev/irdma/irdma_cm.c

3604

last_ae == IRDMA_AE_LLP_CONNECTION_RESET || iwdev->rf->reset || !cm_id) {

sys/dev/irdma/irdma_cm.c

4445

if (iwdev->rf->reset)

sys/dev/irdma/irdma_cm.c

755

irdma_active_open_err(struct irdma_cm_node *cm_node, bool reset)

sys/dev/irdma/irdma_cm.c

759

if (reset) {

sys/dev/irdma/irdma_cm.c

777

irdma_passive_open_err(struct irdma_cm_node *cm_node, bool reset)

sys/dev/irdma/irdma_cm.c

784

if (reset)

sys/dev/irdma/irdma_hmc.c

376

bool reset)

sys/dev/irdma/irdma_hmc.c

383

if (!reset)

sys/dev/irdma/irdma_hmc.c

420

struct irdma_hmc_del_obj_info *info, bool reset)

sys/dev/irdma/irdma_hmc.c

511

return irdma_finish_del_sd_reg(dev, info, reset);

sys/dev/irdma/irdma_hmc.h

181

struct irdma_hmc_del_obj_info *info, bool reset);

sys/dev/irdma/irdma_hw.c

152

if (!cq || rf->reset) {

sys/dev/irdma/irdma_hw.c

1641

iwdev->rf->reset = true;

sys/dev/irdma/irdma_hw.c

1798

iwdev->rf->reset);

sys/dev/irdma/irdma_hw.c

1804

iwdev->rf->reset);

sys/dev/irdma/irdma_hw.c

1905

rf->reset, rf->rdma_ver);

sys/dev/irdma/irdma_hw.c

1908

irdma_destroy_cqp(rf, !rf->reset);

sys/dev/irdma/irdma_hw.c

238

rf->reset = true;

sys/dev/irdma/irdma_hw.c

684

if (rf->reset)

sys/dev/irdma/irdma_hw.c

713

if (rf->reset)

sys/dev/irdma/irdma_hw.c

810

if (!rf->reset)

sys/dev/irdma/irdma_hw.c

829

bool privileged, bool reset)

sys/dev/irdma/irdma_hw.c

837

if (irdma_sc_del_hmc_obj(dev, &info, reset))

sys/dev/irdma/irdma_hw.c

853

bool reset, enum irdma_vers vers)

sys/dev/irdma/irdma_hw.c

860

hmc_info, privileged, reset);

sys/dev/irdma/irdma_kcompat.c

515

if (timeout && !rf->reset) {

sys/dev/irdma/irdma_kcompat.c

516

rf->reset = true;

sys/dev/irdma/irdma_kcompat.c

949

if (!iwdev->rf->reset && irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp))

sys/dev/irdma/irdma_main.h

280

bool reset:1;

sys/dev/irdma/irdma_main.h

609

bool reset, enum irdma_vers vers);

sys/dev/irdma/irdma_puda.c

945

bool reset)

sys/dev/irdma/irdma_puda.c

986

if (!reset)

sys/dev/irdma/irdma_puda.c

992

if (!reset)

sys/dev/irdma/irdma_puda.h

195

bool reset);

sys/dev/irdma/irdma_utils.c

2258

if (qp->iwdev->rf->reset)

sys/dev/irdma/irdma_utils.c

574

if (!rf->reset) {

sys/dev/irdma/irdma_utils.c

575

rf->reset = true;

sys/dev/irdma/irdma_utils.c

588

if (!rf->reset) {

sys/dev/irdma/irdma_utils.c

589

rf->reset = true;

sys/dev/irdma/irdma_utils.c

699

if (rf->reset)

sys/dev/ixgbe/if_ix.c

4311

ret = hw->phy.ops.reset(hw);

sys/dev/ixgbe/if_ix.c

4368

err = hw->phy.ops.reset(hw);

sys/dev/ixgbe/ixgbe_82598.c

218

phy->ops.reset = ixgbe_reset_phy_nl;

sys/dev/ixgbe/ixgbe_82598.c

871

hw->phy.ops.reset(hw);

sys/dev/ixgbe/ixgbe_82599.c

1092

if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)

sys/dev/ixgbe/ixgbe_82599.c

1093

hw->phy.ops.reset(hw);

sys/dev/ixgbe/ixgbe_82599.c

149

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_82599.c

183

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_api.c

545

status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),

sys/dev/ixgbe/ixgbe_phy.c

255

phy->ops.reset = ixgbe_reset_phy_generic;

sys/dev/ixgbe/ixgbe_type.h

4153

s32 (*reset)(struct ixgbe_hw *);

sys/dev/ixgbe/ixgbe_x540.c

85

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

1555

hw->phy.ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2273

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2290

phy->ops.reset = NULL;

sys/dev/ixgbe/ixgbe_x550.c

2312

phy->ops.reset = ixgbe_reset_phy_t_X550em;

sys/dev/ixgbe/ixgbe_x550.c

2319

phy->ops.reset = ixgbe_reset_phy_fw;

sys/dev/ixgbe/ixgbe_x550.c

2422

if (!hw->phy.reset_disable && hw->phy.ops.reset) {

sys/dev/ixgbe/ixgbe_x550.c

2423

if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)

sys/dev/mana/shm_channel.c

112

if (reset && last_dword == SHMEM_VF_RESET_STATE)

sys/dev/mana/shm_channel.c

98

mana_smc_poll_register(void __iomem *base, bool reset)

sys/dev/mlx4/cmd.h

307

struct mlx4_counter *counter_stats, int reset);

sys/dev/mlx4/mlx4_core/mlx4_cmd.c

3177

struct mlx4_counter *counter_stats, int reset)

sys/dev/mlx4/mlx4_core/mlx4_cmd.c

3196

if (reset)

sys/dev/mlx4/mlx4_core/mlx4_reset.c

104

sem = readl(reset + MLX4_SEM_OFFSET);

sys/dev/mlx4/mlx4_core/mlx4_reset.c

114

iounmap(reset);

sys/dev/mlx4/mlx4_core/mlx4_reset.c

119

writel(MLX4_RESET_VALUE, reset + MLX4_RESET_OFFSET);

sys/dev/mlx4/mlx4_core/mlx4_reset.c

120

iounmap(reset);

sys/dev/mlx4/mlx4_core/mlx4_reset.c

44

void __iomem *reset;

sys/dev/mlx4/mlx4_core/mlx4_reset.c

92

reset = ioremap(pci_resource_start(dev->persist->pdev, 0) +

sys/dev/mlx4/mlx4_core/mlx4_reset.c

95

if (!reset) {

sys/dev/mlx4/mlx4_en/en.h

859

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);

sys/dev/mlx4/mlx4_en/mlx4_en_netdev.c

1584

goto reset;

sys/dev/mlx4/mlx4_en/mlx4_en_netdev.c

1588

reset:

sys/dev/mlx4/mlx4_en/mlx4_en_port.c

185

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)

sys/dev/mlx4/mlx4_en/mlx4_en_port.c

194

u64 in_mod = reset << 8 | port;

sys/dev/mlx4/mlx4_en/mlx4_en_port.c

338

&tmp_vport_stats, reset);

sys/dev/mlx4/mlx4_en/mlx4_en_port.c

349

if (reset == 0) {

sys/dev/mlx4/stats.h

157

int reset, int *read_counters);

sys/dev/mlx5/cmd.h

46

bool reset, void *out, int out_size);

sys/dev/mlx5/mlx5_core/mlx5_cmd.c

1659

bool reset, void *out, int out_size)

sys/dev/mlx5/mlx5_core/mlx5_cmd.c

1665

MLX5_SET(query_cong_statistics_in, in, clear, reset);

sys/dev/mlx5/mlx5_core/mlx5_vport.c

181

int reset,

sys/dev/mlx5/mlx5_core/mlx5_vport.c

188

MLX5_SET(query_q_counter_in, in, clear, reset);

sys/dev/mlx5/vport.h

43

int reset,

sys/dev/mmc/mmc.c

197

static int mmc_retune(device_t busdev, device_t dev, bool reset);

sys/dev/mmc/mmc.c

2364

mmc_retune(device_t busdev, device_t dev, bool reset)

sys/dev/mmc/mmc.c

2389

if (reset == false)

sys/dev/mmc/mmc.c

2396

err = mmcbr_retune(busdev, reset);

sys/dev/mmc/mmcbrvar.h

146

mmcbr_retune(device_t dev, bool reset)

sys/dev/mmc/mmcbrvar.h

149

return (MMCBR_RETUNE(device_get_parent(dev), dev, reset));

sys/dev/mpi3mr/mpi3mr.c

3336

if (sc->reset.type == MPI3MR_TRIGGER_SOFT_RESET) {

sys/dev/mpi3mr/mpi3mr.c

3338

mpi3mr_soft_reset_handler(sc, sc->reset.reason, 1);

sys/dev/mpi3mr/mpi3mr.c

6314

(sc->reset.ioctl_reset_snapdump != true))

sys/dev/mpi3mr/mpi3mr.c

6325

sc->reset.type = MPI3MR_NO_RESET;

sys/dev/mpi3mr/mpi3mr.c

6326

sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON;

sys/dev/mpi3mr/mpi3mr.c

6327

sc->reset.status = -1;

sys/dev/mpi3mr/mpi3mr.c

6328

sc->reset.ioctl_reset_snapdump = false;

sys/dev/mpi3mr/mpi3mr.c

6430

sc->reset.type = MPI3MR_NO_RESET;

sys/dev/mpi3mr/mpi3mr.c

6431

sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON;

sys/dev/mpi3mr/mpi3mr.c

6432

sc->reset.status = retval;

sys/dev/mpi3mr/mpi3mr.c

6433

sc->reset.ioctl_reset_snapdump = false;

sys/dev/mpi3mr/mpi3mr.h

564

struct mpi3mr_reset reset;

sys/dev/mpi3mr/mpi3mr_app.c

1099

sc->reset.type = MPI3MR_TRIGGER_SOFT_RESET;

sys/dev/mpi3mr/mpi3mr_app.c

1100

sc->reset.reason = MPI3MR_RESET_FROM_IOCTL_TIMEOUT;

sys/dev/mpi3mr/mpi3mr_app.c

1238

sc->reset.type = MPI3MR_TRIGGER_SOFT_RESET;

sys/dev/mpi3mr/mpi3mr_app.c

1239

sc->reset.reason = MPI3MR_RESET_FROM_IOCTL;

sys/dev/mpi3mr/mpi3mr_app.c

1270

if ((!timeout || sc->reset.status))

sys/dev/mpi3mr/mpi3mr_app.c

1313

sc->reset.ioctl_reset_snapdump = false;

sys/dev/mpi3mr/mpi3mr_app.c

1316

sc->reset.ioctl_reset_snapdump = true;

sys/dev/mpi3mr/mpi3mr_app.c

1611

sc->reset.type = MPI3MR_TRIGGER_SOFT_RESET;

sys/dev/mpi3mr/mpi3mr_app.c

1612

sc->reset.reason = MPI3MR_RESET_FROM_PELABORT_TIMEOUT;

sys/dev/mpi3mr/mpi3mr_cam.c

494

sc->reset.type = reset_type;

sys/dev/mpi3mr/mpi3mr_cam.c

495

sc->reset.reason = reset_reason;

sys/dev/mpi3mr/mpi3mr_pci.c

157

OID_AUTO, "reset", CTLFLAG_RW, &sc->reset.type, 0,

sys/dev/mpi3mr/mpi3mr_pci.c

179

sc->reset.type = 0;

sys/dev/mpi3mr/mpi3mr_pci.c

187

TUNABLE_INT_FETCH("hw.mpi3mr.ctrl_reset", &sc->reset.type);

sys/dev/mpi3mr/mpi3mr_pci.c

198

TUNABLE_INT_FETCH(tmpstr, &sc->reset.type);

sys/dev/mpt/mpt.c

1177

pers->reset(mpt, ret);

sys/dev/mpt/mpt.c

205

.reset = mpt_stdreset,

sys/dev/mpt/mpt.c

226

.reset = mpt_core_ioc_reset,

sys/dev/mpt/mpt.h

191

mpt_reset_handler_t *reset; /* Re-init after reset. */

sys/dev/mpt/mpt_cam.c

178

.reset = mpt_cam_ioc_reset,

sys/dev/mpt/mpt_raid.c

93

.reset = mpt_raid_ioc_reset,

sys/dev/mpt/mpt_user.c

74

.reset = mpt_user_reset,

sys/dev/mthca/mthca_reset.c

159

void __iomem *reset = ioremap(pci_resource_start(mdev->pdev, 0) +

sys/dev/mthca/mthca_reset.c

162

if (!reset) {

sys/dev/mthca/mthca_reset.c

169

writel(MTHCA_RESET_VALUE, reset);

sys/dev/mthca/mthca_reset.c

170

iounmap(reset);

sys/dev/oce/oce_sysctl.c

1505

int rc = 0, reset = 0;

sys/dev/oce/oce_sysctl.c

1520

rc = oce_mbox_get_pport_stats(sc, &sc->stats_mem, reset);

sys/dev/ocs_fc/ocs_hw.c

1314

ocs_hw_reset(ocs_hw_t *hw, ocs_hw_reset_e reset)

sys/dev/ocs_fc/ocs_hw.c

1351

switch(reset) {

sys/dev/ocs_fc/sli4.c

1773

sli4_req_common_function_reset_t *reset = NULL;

sys/dev/ocs_fc/sli4.c

1786

reset = (sli4_req_common_function_reset_t *)((uint8_t *)buf + sli_config_off);

sys/dev/ocs_fc/sli4.c

1788

reset->hdr.opcode = SLI4_OPC_COMMON_FUNCTION_RESET;

sys/dev/ocs_fc/sli4.c

1789

reset->hdr.subsystem = SLI4_SUBSYSTEM_COMMON;

sys/dev/qat_c2xxx/qat_ae.c

1035

uint32_t times, reset, clock, reg, mask;

sys/dev/qat_c2xxx/qat_ae.c

1038

reset = qat_cap_global_read_4(sc, CAP_GLOBAL_CTL_RESET);

sys/dev/qat_c2xxx/qat_ae.c

1039

reset &= ~(__SHIFTIN(sc->sc_ae_mask, CAP_GLOBAL_CTL_RESET_AE_MASK));

sys/dev/qat_c2xxx/qat_ae.c

1040

reset &= ~(__SHIFTIN(sc->sc_accel_mask, CAP_GLOBAL_CTL_RESET_ACCEL_MASK));

sys/dev/qat_c2xxx/qat_ae.c

1043

qat_cap_global_write_4(sc, CAP_GLOBAL_CTL_RESET, reset);

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

131

qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset)

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

145

if (reset)

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

155

qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

169

*reset = true;

sys/dev/qcom_gcc/qcom_gcc_ipq4018_reset.c

171

*reset = false;

sys/dev/qcom_gcc/qcom_gcc_reset.c

52

qcom_gcc_hwreset_assert(device_t dev, intptr_t id, bool reset)

sys/dev/qcom_gcc/qcom_gcc_reset.c

55

return (sc->sc_cb.hw_reset_assert(dev, id, reset));

sys/dev/qcom_gcc/qcom_gcc_reset.c

59

qcom_gcc_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/dev/qcom_gcc/qcom_gcc_reset.c

63

return (sc->sc_cb.hw_reset_is_asserted(dev, id, reset));

sys/dev/qcom_gcc/qcom_gcc_var.h

63

bool reset);

sys/dev/qcom_gcc/qcom_gcc_var.h

65

bool *reset);

sys/dev/qlnx/qlnxe/ecore_iscsi.h

143

bool reset,

sys/dev/rtsx/rtsx.c

279

static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused);

sys/dev/rtsx/rtsx.c

3422

rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused)

sys/dev/scc/scc_dev_quicc.c

82

quicc_bfe_attach(struct scc_softc *sc __unused, int reset __unused)

sys/dev/scc/scc_dev_z8530.c

102

z8530_bfe_attach(struct scc_softc *sc __unused, int reset __unused)

sys/dev/sdhci/sdhci.c

1536

sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset)

sys/dev/sdhci/sdhci.c

1549

err = sdhci_exec_tuning(slot, reset);

sys/dev/sdhci/sdhci.c

1570

sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)

sys/dev/sdhci/sdhci.c

1597

if (reset)

sys/dev/sdhci/sdhci.c

98

static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);

sys/dev/sdhci/sdhci.h

436

int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset);

sys/dev/sdhci/sdhci_fsl_fdt.c

1306

sdhci_fsl_fdt_retune(device_t bus, device_t child, bool reset)

sys/dev/sdhci/sdhci_fsl_fdt.c

1329

if (!reset)

sys/dev/sound/pcm/channel.c

129

chn_vpc_proc(int reset, int db)

sys/dev/sound/pcm/channel.c

147

if (reset != 0)

sys/dev/uart/uart_dev_snps.c

163

hwreset_t reset;

sys/dev/uart/uart_dev_snps.c

185

if (hwreset_get_by_ofw_idx(dev, 0, 0, &reset) == 0) {

sys/dev/uart/uart_dev_snps.c

186

error = hwreset_deassert(reset);

sys/dev/uart/uart_dev_snps.c

231

sc->reset = reset;

sys/dev/uart/uart_dev_snps.c

257

hwreset_t reset;

sys/dev/uart/uart_dev_snps.c

263

reset = sc->reset;

sys/dev/uart/uart_dev_snps.c

269

if (reset != NULL) {

sys/dev/uart/uart_dev_snps.c

270

error = hwreset_assert(reset);

sys/dev/uart/uart_dev_snps.c

275

hwreset_release(reset);

sys/dev/uart/uart_dev_snps.c

51

hwreset_t reset;

sys/dev/usb/controller/musb_otg_allwinner.c

122

hwreset_t reset;

sys/dev/usb/controller/musb_otg_allwinner.c

429

(void)hwreset_get_by_ofw_idx(dev, 0, 0, &sc->reset);

sys/dev/usb/controller/musb_otg_allwinner.c

437

if (sc->reset != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

438

error = hwreset_deassert(sc->reset);

sys/dev/usb/controller/musb_otg_allwinner.c

551

if (sc->reset != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

552

hwreset_assert(sc->reset);

sys/dev/usb/controller/musb_otg_allwinner.c

553

hwreset_release(sc->reset);

sys/dev/usb/controller/musb_otg_allwinner.c

585

if (sc->reset != NULL) {

sys/dev/usb/controller/musb_otg_allwinner.c

586

if (hwreset_assert(sc->reset) != 0)

sys/dev/usb/controller/musb_otg_allwinner.c

588

hwreset_release(sc->reset);

sys/dev/usb/controller/ohci.c

196

goto reset;

sys/dev/usb/controller/ohci.c

200

reset:

sys/dev/usb/wlan/if_uath.c

1424

struct uath_cmd_reset reset;

sys/dev/usb/wlan/if_uath.c

1426

memset(&reset, 0, sizeof(reset));

sys/dev/usb/wlan/if_uath.c

1428

reset.flags |= htobe32(UATH_CHAN_2GHZ);

sys/dev/usb/wlan/if_uath.c

1430

reset.flags |= htobe32(UATH_CHAN_5GHZ);

sys/dev/usb/wlan/if_uath.c

1433

reset.flags |= htobe32(UATH_CHAN_OFDM);

sys/dev/usb/wlan/if_uath.c

1435

reset.flags |= htobe32(UATH_CHAN_CCK);

sys/dev/usb/wlan/if_uath.c

1438

reset.flags |= htobe32(UATH_CHAN_TURBO);

sys/dev/usb/wlan/if_uath.c

1439

reset.freq = htobe32(c->ic_freq);

sys/dev/usb/wlan/if_uath.c

1440

reset.maxrdpower = htobe32(50); /* XXX */

sys/dev/usb/wlan/if_uath.c

1441

reset.channelchange = htobe32(1);

sys/dev/usb/wlan/if_uath.c

1442

reset.keeprccontent = htobe32(0);

sys/dev/usb/wlan/if_uath.c

1446

be32toh(reset.flags), be32toh(reset.freq));

sys/dev/usb/wlan/if_uath.c

1447

return uath_cmd_write(sc, WDCMSG_RESET, &reset, sizeof reset, 0);

sys/dev/vnic/nicvf_queues.c

1393

cq_cfg.reset = 0;

sys/dev/vnic/nicvf_queues.c

1442

sq_cfg.reset = 0;

sys/dev/vnic/nicvf_queues.c

1472

rbdr_cfg.reset = 0;

sys/dev/vnic/q_struct.h

623

uint64_t reset:1;

sys/dev/vnic/q_struct.h

637

uint64_t reset:1;

sys/dev/vnic/q_struct.h

648

uint64_t reset:1;

sys/dev/vnic/q_struct.h

660

uint64_t reset:1;

sys/dev/vnic/q_struct.h

671

uint64_t reset:1;

sys/dev/vnic/q_struct.h

687

uint64_t reset:1;

sys/fs/tarfs/tarfs_io.c

337

bool reset = false;

sys/fs/tarfs/tarfs_io.c

343

reset = true;

sys/fs/tarfs/tarfs_io.c

351

reset = true;

sys/fs/tarfs/tarfs_io.c

355

if (reset) {

sys/fs/tarfs/tarfs_io.c

89

SYSCTL_PROC(_vfs_tarfs_zio, OID_AUTO, reset,

sys/kern/kern_boottrace.c

130

SYSCTL_PROC(_kern_boottrace, OID_AUTO, reset,

sys/kern/kern_switch.c

143

SYSCTL_PROC(_kern_sched_stats, OID_AUTO, reset,

sys/kern/kern_tc.c

2092

cpu_tick_calibrate(int reset)

sys/kern/kern_tc.c

2100

if (reset) {

sys/kern/link_elf.c

805

preload_protect1(elf_file_t ef, vm_prot_t prot, bool reset)

sys/kern/link_elf.c

822

if (!reset) {

sys/kern/subr_compressor.c

248

.reset = gz_reset,

sys/kern/subr_compressor.c

494

.reset = zstdio_reset,

sys/kern/subr_compressor.c

52

void (* const reset)(void *);

sys/kern/subr_compressor.c

551

stream->methods->reset(stream->priv);

sys/kern/subr_lock.c

737

SYSCTL_PROC(_debug_lock_prof, OID_AUTO, reset,

sys/kern/subr_sleepqueue.c

1433

SYSCTL_PROC(_debug_sleepq, OID_AUTO, reset,

sys/kern/uipc_ktls.c

263

SYSCTL_COUNTER_U64(_kern_ipc_tls_ifnet, OID_AUTO, reset, CTLFLAG_RD,

sys/netgraph/bluetooth/drivers/ubt/ng_ubt_intel.c

197

ng_hci_reset_rp reset;

sys/netgraph/bluetooth/drivers/ubt/ng_ubt_intel.c

222

&reset, sizeof(reset)) != USB_ERR_NORMAL_COMPLETION)

sys/netgraph/bluetooth/drivers/ubt/ng_ubt_intel.c

224

if (reset.status != 0)

sys/netgraph/ng_async.c

515

goto reset;

sys/netgraph/ng_async.c

521

goto reset;

sys/netgraph/ng_async.c

534

goto reset;

sys/netgraph/ng_async.c

549

reset:

sys/netipsec/key.c

3381

goto reset;

sys/netipsec/key.c

3416

reset:

sys/powerpc/powermac/ata_dbdma.c

272

sc->sc_ch.dma.reset = ata_dbdma_reset;

sys/powerpc/powermac/platform_powermac.c

348

int res, reset, timeout;

sys/powerpc/powermac/platform_powermac.c

351

res = OF_getprop(cpu, "soft-reset", &reset, sizeof(reset));

sys/powerpc/powermac/platform_powermac.c

353

reset = 0x58;

sys/powerpc/powermac/platform_powermac.c

357

reset += 0x03;

sys/powerpc/powermac/platform_powermac.c

360

reset += 0x04;

sys/powerpc/powermac/platform_powermac.c

363

reset += 0x0f;

sys/powerpc/powermac/platform_powermac.c

366

reset += 0x10;

sys/powerpc/powermac/platform_powermac.c

378

rstvec = rstvec_virtbase + reset;

sys/riscv/cvitek/cvitek_reset.c

107

if (reset)

sys/riscv/cvitek/cvitek_reset.c

95

cvitek_reset_assert(device_t dev, intptr_t id, bool reset)

sys/riscv/eswin/eswin_reset.c

112

eswin_rst_reset_assert(device_t dev, intptr_t id, bool reset)

sys/riscv/eswin/eswin_reset.c

126

if (reset)

sys/riscv/eswin/eswin_reset.c

137

eswin_rst_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/riscv/eswin/eswin_reset.c

151

*reset = (reg & (1 << bit)) == 0;

sys/riscv/sifive/sifive_prci.c

628

prci_reset_assert(device_t dev, intptr_t id, bool reset)

sys/riscv/sifive/sifive_prci.c

640

if (reset)

sys/riscv/sifive/sifive_prci.c

651

prci_reset_is_asserted(device_t dev, intptr_t id, bool *reset)

sys/riscv/sifive/sifive_prci.c

663

*reset = (reg & (1u << id)) == 0;

tools/tools/ath/athstats/athstats.c

703

case S_ANI_RESET: ANISTAT(reset);

tools/tools/ath/athstats/athstats.c

956

case S_ANI_RESET: ANISTAT(reset);

usr.bin/dtc/fdt.cc

1347

p.reset(new property("linux,phandle"));

usr.bin/dtc/fdt.cc

1353

p.reset(new property("phandle"));

usr.bin/dtc/input_buffer.cc

599

lhs.reset(new_left);

usr.bin/dtc/input_buffer.cc

928

lhs.reset(new terminal_expr(l, leftVal));

usr.bin/dtc/input_buffer.cc

935

lhs.reset(new terminal_expr(l, leftVal));

usr.bin/dtc/input_buffer.cc

945

lhs.reset(new paren_expression(l, std::move(subexpr)));

usr.bin/dtc/input_buffer.cc

964

lhs.reset(new unary_operator<'+', unary_plus<valty>>(l, std::move(subexpr)));

usr.bin/dtc/input_buffer.cc

975

lhs.reset(new unary_operator<'-', std::negate<valty>>(l, std::move(subexpr)));

usr.bin/dtc/input_buffer.cc

986

lhs.reset(new unary_operator<'!', std::logical_not<valty>>(l, std::move(subexpr)));

usr.bin/dtc/input_buffer.cc

997

lhs.reset(new unary_operator<'~', bit_not<valty>>(l, std::move(subexpr)));

usr.bin/mail/lex.c

545

reset(0);

usr.bin/mail/lex.c

565

reset(0);

usr.bin/mail/quit.c

426

reset(0);

usr.bin/mail/quit.c

433

reset(0);

usr.bin/mail/quit.c

444

reset(0);

usr.bin/mail/quit.c

453

reset(0);

usr.bin/mail/quit.c

464

reset(0);

usr.bin/mail/quit.c

477

reset(0);

usr.bin/patch/util.c

297

set_signals(int reset)

usr.bin/patch/util.c

301

if (!reset) {

usr.bin/systat/extern.h

182

void reset ## name(void); \

usr.sbin/bhyve/hda_codec.c

852

.reset = hda_codec_reset,

usr.sbin/bhyve/pci_ahci.c

145

int reset;

usr.sbin/bhyve/pci_ahci.c

1906

p->reset = 1;

usr.sbin/bhyve/pci_ahci.c

1907

else if (p->reset) {

usr.sbin/bhyve/pci_ahci.c

1908

p->reset = 0;

usr.sbin/bhyve/pci_ahci.c

2684

SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);

usr.sbin/bhyve/pci_hda.c

538

if (codec->reset)

usr.sbin/bhyve/pci_hda.c

539

codec->reset(hci);

usr.sbin/bhyve/pci_hda.h

76

int (*reset)(struct hda_codec_inst *hci);

usr.sbin/ctld/ctld.cc

1023

s.reset();

usr.sbin/ctld/ctld.cc

1044

s.reset();

usr.sbin/ctld/ctld.cc

2571

conf.reset();

usr.sbin/ctld/ctld.cc

2602

conf.reset();

usr.sbin/ctld/ctld.cc

2741

oldconf.reset();

usr.sbin/ctld/ctld.cc

2771

oldconf.reset();

usr.sbin/ctld/ctld.cc

2787

oldconf.reset();

usr.sbin/ctld/ctld.cc

887

s.reset();

usr.sbin/ctld/ctld.cc

997

s.reset();

usr.sbin/ctld/ctld.hh

166

void close() { p_socket.reset(); }

usr.sbin/ctld/nvmf.cc

182

p_association.reset(nvmf_allocate_association(NVMF_TRTYPE_TCP, true,

usr.sbin/ctld/nvmf_discovery.cc

511

nc_guard.reset();

usr.sbin/dconschat/dconschat.c

162

if (dc->reset == 0)

usr.sbin/dconschat/dconschat.c

167

(intmax_t)dc->reset);

usr.sbin/dconschat/dconschat.c

170

dwrite(dc, (void *)buf, PAGE_SIZE, dc->reset);

usr.sbin/dconschat/dconschat.c

327

dc->reset = ((off_t)reset_hi << 24) | reset_lo;

usr.sbin/dconschat/dconschat.c

790

&& (dc->reset != 0)) {

usr.sbin/dconschat/dconschat.c

95

off_t reset;

usr.sbin/devctl/devctl.c

420

DEVCTL_COMMAND(top, reset, reset);

usr.sbin/jail/state.c

157

int reset, depfrom, depto, ndeps, rev;

usr.sbin/jail/state.c

188

reset = 0;

usr.sbin/jail/state.c

191

reset = 1;

usr.sbin/jail/state.c

209

reset = 1;

usr.sbin/jail/state.c

216

if (reset)

usr.sbin/moused/moused/moused.c

487

static void reset(int sig);

usr.sbin/moused/moused/moused.c

784

signal(SIGHUP , reset);

usr.sbin/moused/moused/moused.c

785

signal(SIGINT , reset);

usr.sbin/moused/moused/moused.c

786

signal(SIGQUIT, reset);

usr.sbin/moused/moused/moused.c

787

signal(SIGTERM, reset);