reg_addr - FreeBSD

sys/arm/arm/debug_monitor.c

550

uint32_t reg_addr, reg_ctrl;

sys/arm/arm/debug_monitor.c

556

reg_addr = DBG_REG_BASE_BVR;

sys/arm/arm/debug_monitor.c

561

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

570

if ((dbg_wb_read_reg(reg_addr, i) == addr) &&

sys/arm/arm/debug_monitor.c

620

uint32_t reg_ctrl, reg_addr, ctrl, addr;

sys/arm/arm/debug_monitor.c

679

reg_addr = DBG_REG_BASE_BVR;

sys/arm/arm/debug_monitor.c

700

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

706

dbg_wb_write_reg(reg_addr, i, addr);

sys/arm/arm/debug_monitor.c

737

uint32_t reg_ctrl, reg_addr, addr;

sys/arm/arm/debug_monitor.c

751

reg_addr = DBG_REG_BASE_BVR;

sys/arm/arm/debug_monitor.c

759

reg_addr = DBG_REG_BASE_WVR;

sys/arm/arm/debug_monitor.c

763

dbg_wb_write_reg(reg_addr, i, 0);

sys/arm64/arm64/debug_monitor.c

416

uint64_t *reg_addr, *reg_ctrl;

sys/arm64/arm64/debug_monitor.c

422

reg_addr = monitor->dbg_bvr;

sys/arm64/arm64/debug_monitor.c

427

reg_addr = monitor->dbg_wvr;

sys/arm64/arm64/debug_monitor.c

436

if (reg_addr[i] == addr &&

sys/dev/al_eth/al_init_eth_lm.c

730

uint8_t reg_addr,

sys/dev/al_eth/al_init_eth_lm.c

740

reg_addr,

sys/dev/al_eth/al_init_eth_lm.c

752

reg_addr,

sys/dev/al_eth/al_init_eth_lm.h

174

uint8_t reg_addr, uint8_t *val);

sys/dev/al_eth/al_init_eth_lm.h

176

uint8_t reg_addr, uint8_t val);

sys/dev/al_eth/al_init_eth_lm.h

252

uint8_t reg_addr, uint8_t *val);

sys/dev/al_eth/al_init_eth_lm.h

254

uint8_t reg_addr, uint8_t val);

sys/dev/bnxt/bnxt_en/hsi_struct_def.h

31789

uint16_t reg_addr;

sys/dev/bnxt/bnxt_en/hsi_struct_def.h

31868

uint16_t reg_addr;

sys/dev/bxe/bxe.c

17700

uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

sys/dev/bxe/bxe.c

17702

val = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

17704

REG_WR(sc, reg_addr, val);

sys/dev/bxe/bxe.c

1807

uint32_t reg_addr)

sys/dev/bxe/bxe.c

1809

return (REG_RD(sc, reg_addr));

sys/dev/bxe/bxe.c

1814

uint32_t reg_addr,

sys/dev/bxe/bxe.c

1817

REG_WR(sc, reg_addr, val);

sys/dev/bxe/bxe.c

18717

static const struct reg_addr *

sys/dev/bxe/bxe.c

18740

bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)

sys/dev/bxe/bxe.c

18798

const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc);

sys/dev/bxe/bxe.c

18894

uint32_t reg_addr;

sys/dev/bxe/bxe.c

19058

reg_addr = (cmd_offset +(i * 4));

sys/dev/bxe/bxe.c

19059

reg_val = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

19061

reg_addr, reg_val);

sys/dev/bxe/bxe.c

7056

uint32_t reg_addr;

sys/dev/bxe/bxe.c

7146

reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);

sys/dev/bxe/bxe.c

7148

reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);

sys/dev/bxe/bxe.c

7153

(sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);

sys/dev/bxe/bxe.c

7154

REG_WR(sc, reg_addr, asserted);

sys/dev/bxe/bxe.c

8198

uint32_t reg_addr;

sys/dev/bxe/bxe.c

8258

reg_addr = (HC_REG_COMMAND_REG + port*32 +

sys/dev/bxe/bxe.c

8261

reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);

sys/dev/bxe/bxe.c

8267

(sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);

sys/dev/bxe/bxe.c

8268

REG_WR(sc, reg_addr, val);

sys/dev/bxe/bxe.c

8274

reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :

sys/dev/bxe/bxe.c

8279

aeu_mask = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

8286

REG_WR(sc, reg_addr, aeu_mask);

sys/dev/bxe/bxe_dump.h

1912

static const struct reg_addr idle_reg_addrs[] = {

sys/dev/bxe/bxe_dump.h

78

static const struct reg_addr page_read_regs_e2[] = {

sys/dev/bxe/bxe_dump.h

87

static const struct reg_addr page_read_regs_e3[] = {

sys/dev/bxe/bxe_dump.h

91

static const struct reg_addr reg_addrs[] = {

sys/dev/bxe/bxe_elink.h

46

extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr);

sys/dev/bxe/bxe_elink.h

47

extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val);

sys/dev/bxe/ecore_init.h

256

uint32_t reg_addr, reg_bit_map, vnic;

sys/dev/bxe/ecore_init.h

277

reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);

sys/dev/bxe/ecore_init.h

278

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

279

REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));

sys/dev/bxe/ecore_init.h

282

reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);

sys/dev/bxe/ecore_init.h

283

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

284

REG_WR(sc, reg_addr, reg_bit_map | q_bit_map);

sys/dev/bxe/ecore_init.h

289

reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);

sys/dev/bxe/ecore_init.h

290

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

295

REG_WR(sc, reg_addr, reg_bit_map);

sys/dev/cxgb/common/cxgb_ael1002.c

105

err = mdio_write(phy, rv->mmd_addr, rv->reg_addr,

sys/dev/cxgb/common/cxgb_ael1002.c

109

rv->reg_addr, rv->clear_bits,

sys/dev/cxgb/common/cxgb_ael1002.c

92

unsigned short reg_addr;

sys/dev/cxgb/common/cxgb_common.h

149

int reg_addr, unsigned int *val);

sys/dev/cxgb/common/cxgb_common.h

151

int reg_addr, unsigned int val);

sys/dev/cxgb/common/cxgb_common.h

584

int reg_addr, unsigned int *val);

sys/dev/cxgb/common/cxgb_common.h

586

int reg_addr, unsigned int val);

sys/dev/cxgb/common/cxgb_common.h

626

#define XGM_REG(reg_addr, idx) \

sys/dev/cxgb/common/cxgb_common.h

627

((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))

sys/dev/cxgb/common/cxgb_common.h

630

unsigned int reg_addr;

sys/dev/cxgb/common/cxgb_common.h

839

int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,

sys/dev/cxgb/common/cxgb_common.h

841

int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,

sys/dev/cxgb/common/cxgb_t3_hw.c

262

int reg_addr, unsigned int *valp)

sys/dev/cxgb/common/cxgb_t3_hw.c

265

u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);

sys/dev/cxgb/common/cxgb_t3_hw.c

282

int reg_addr, unsigned int val)

sys/dev/cxgb/common/cxgb_t3_hw.c

285

u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);

sys/dev/cxgb/common/cxgb_t3_hw.c

309

int reg_addr, unsigned int *valp)

sys/dev/cxgb/common/cxgb_t3_hw.c

317

t3_write_reg(adapter, A_MI1_DATA, reg_addr);

sys/dev/cxgb/common/cxgb_t3_hw.c

332

int reg_addr, unsigned int val)

sys/dev/cxgb/common/cxgb_t3_hw.c

340

t3_write_reg(adapter, A_MI1_DATA, reg_addr);

sys/dev/cxgb/common/cxgb_t3_hw.c

85

t3_write_reg(adapter, p->reg_addr + offset, p->val);

sys/dev/cxgb/common/cxgb_vsc7323.c

140

if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr,

sys/dev/cxgb/common/cxgb_vsc7323.c

169

if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr,

sys/dev/cxgb/common/cxgb_vsc7323.c

174

if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr,

sys/dev/cxgb/cxgb_adapter.h

429

t3_read_reg(adapter_t *adapter, uint32_t reg_addr)

sys/dev/cxgb/cxgb_adapter.h

431

return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr));

sys/dev/cxgb/cxgb_adapter.h

435

t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)

sys/dev/cxgb/cxgb_adapter.h

437

bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val);

sys/dev/cxgbe/common/t4_hw.c

7484

static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,

sys/dev/cxgbe/common/t4_hw.c

7491

switch (reg_addr) {

sys/dev/cxgbe/common/t4_hw.c

7513

t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,

sys/dev/cxgbe/common/t4_hw.c

7516

t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,

sys/dev/cxgbe/common/t4_regs.h

107

#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

110

#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

113

#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

116

#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

119

#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

122

#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

125

#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

131

#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

134

#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)

sys/dev/cxgbe/common/t4_regs.h

137

#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

140

#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

254

#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

263

#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)

sys/dev/cxgbe/common/t4_regs.h

266

#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

270

#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

273

#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

276

#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

279

#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

282

#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

288

#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

291

#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

297

#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

300

#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

303

#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

306

#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

309

#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

345

#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

sys/dev/cxgbe/common/t4_regs.h

348

#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

sys/dev/cxgbe/common/t4_regs.h

351

#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

354

#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

357

#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

360

#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

363

#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

366

#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

369

#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

37

#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

384

#define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

387

#define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

390

#define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

40

#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

43

#define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

46

#define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

483

#define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)

sys/dev/cxgbe/common/t4_regs.h

486

#define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

489

#define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

49

#define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

499

#define T7_MYPORT_REG(reg_addr) (T7_MYPORT_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

502

#define T7_PORT0_REG(reg_addr) (T7_PORT0_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

505

#define T7_PORT1_REG(reg_addr) (T7_PORT1_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

508

#define T7_PORT2_REG(reg_addr) (T7_PORT2_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

511

#define T7_PORT3_REG(reg_addr) (T7_PORT3_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

517

#define PCIE_MEM_ACCESS_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

52

#define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

520

#define PCIE_T7_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

523

#define PCIE_T5_ARM_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

526

#define PCIE_JBOF_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

529

#define PCIE_EMUADRRMAP_REG(reg_addr, idx) ((reg_addr) + (idx) * 32)

sys/dev/cxgbe/common/t4_regs.h

55

#define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

58

#define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

589

#define TLS_TX_CH_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)

sys/dev/cxgbe/common/t4_regs.h

592

#define TLS_TX_CH_IND_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)

sys/dev/cxgbe/common/t4_regs.h

595

#define ARM_CPU_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)

sys/dev/cxgbe/common/t4_regs.h

598

#define ARM_CCIM_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

601

#define ARM_CCIS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)

sys/dev/cxgbe/common/t4_regs.h

61

#define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

613

#define ARM_MSG_REG(reg_addr, idx) ((reg_addr) + (idx) * 48)

sys/dev/cxgbe/common/t4_regs.h

619

#define MC_CE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

622

#define MC_UE_ERR_DATA_T7_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

625

#define MC_P_BIST_USER_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

628

#define HMA_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

631

#define GCACHE_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)

sys/dev/cxgbe/common/t4_regs.h

652

#define CIM_CTL_SLV_REG(reg_addr, idx) ((reg_addr) + (idx) * 1024)

sys/dev/cxgbe/common/t4_regs.h

68

#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

71

#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

74

#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

77

#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

80

#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

83

#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

86

#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

89

#define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

92

#define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))

sys/dev/cxgbe/common/t4_regs.h

95

#define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))

sys/dev/cxgbe/cudbg/cudbg_lib.c

4261

u32 reg_addr, reg_data, reg_local_offset, reg_offset_range;

sys/dev/cxgbe/cudbg/cudbg_lib.c

4322

reg_addr = t5_pcie_cdbg_array[0][0];

sys/dev/cxgbe/cudbg/cudbg_lib.c

4327

t4_read_indirect(padap, reg_addr, reg_data, sp, reg_offset_range,

sys/dev/cxgbe/cudbg/cudbg_lib.c

4334

reg_addr = t5_pcie_cdbg_array[0][0];

sys/dev/cxgbe/cudbg/cudbg_lib.c

4339

t4_read_indirect(padap, reg_addr, reg_data, sp,

sys/dev/e1000/e1000_ich8lan.c

2287

u16 word_addr, reg_data, reg_addr, phy_page = 0;

sys/dev/e1000/e1000_ich8lan.c

2379

1, &reg_addr);

sys/dev/e1000/e1000_ich8lan.c

2384

if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {

sys/dev/e1000/e1000_ich8lan.c

2389

reg_addr &= PHY_REG_MASK;

sys/dev/e1000/e1000_ich8lan.c

2390

reg_addr |= phy_page;

sys/dev/e1000/e1000_ich8lan.c

2392

ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,

sys/dev/ixgbe/ixgbe_api.c

1321

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_api.c

1324

return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.c

1337

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_api.c

1340

return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.c

575

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_api.c

581

return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.c

594

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_api.c

600

return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,

sys/dev/ixgbe/ixgbe_api.h

215

s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_api.h

217

s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_api.h

71

s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_api.h

73

s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_phy.c

597

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_phy.c

603

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

634

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

679

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_phy.c

690

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/ixgbe/ixgbe_phy.c

705

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_phy.c

714

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

743

command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_phy.c

779

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_phy.c

788

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/ixgbe/ixgbe_phy.h

166

s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_phy.h

168

s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,

sys/dev/ixgbe/ixgbe_phy.h

170

s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_phy.h

172

s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

1130

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

1145

command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_x550.c

1176

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

1191

command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |

sys/dev/ixgbe/ixgbe_x550.c

4318

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

4329

status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);

sys/dev/ixgbe/ixgbe_x550.c

4346

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

4355

status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,

sys/dev/ixgbe/ixgbe_x550.c

520

static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

523

UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);

sys/dev/ixgbe/ixgbe_x550.c

527

static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.c

530

UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);

sys/dev/ixgbe/ixgbe_x550.h

100

s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.h

102

s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.h

64

s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixgbe/ixgbe_x550.h

66

s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,

sys/dev/ixl/i40e_common.c

3417

u32 reg_addr, u64 *reg_val,

sys/dev/ixl/i40e_common.c

3430

cmd_resp->address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_common.c

3452

u32 reg_addr, u64 reg_val,

sys/dev/ixl/i40e_common.c

3462

cmd->address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_common.c

7177

u32 reg_addr, u32 *reg_val,

sys/dev/ixl/i40e_common.c

7190

cmd_resp->address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_common.c

7205

u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)

sys/dev/ixl/i40e_common.c

7217

status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);

sys/dev/ixl/i40e_common.c

7227

val = rd32(hw, reg_addr);

sys/dev/ixl/i40e_common.c

7243

u32 reg_addr, u32 reg_val,

sys/dev/ixl/i40e_common.c

7253

cmd->address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_common.c

7267

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)

sys/dev/ixl/i40e_common.c

7278

status = i40e_aq_rx_ctl_write_register(hw, reg_addr,

sys/dev/ixl/i40e_common.c

7289

wr32(hw, reg_addr, reg_val);

sys/dev/ixl/i40e_common.c

7336

u32 reg_addr, u32 reg_val,

sys/dev/ixl/i40e_common.c

7349

cmd->reg_address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_common.c

7382

u32 reg_addr, u32 *reg_val,

sys/dev/ixl/i40e_common.c

7395

cmd->reg_address = CPU_TO_LE32(reg_addr);

sys/dev/ixl/i40e_prototype.h

125

u32 reg_addr, u64 reg_val,

sys/dev/ixl/i40e_prototype.h

128

u32 reg_addr, u64 *reg_val,

sys/dev/ixl/i40e_prototype.h

576

u32 reg_addr, u32 *reg_val,

sys/dev/ixl/i40e_prototype.h

578

u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);

sys/dev/ixl/i40e_prototype.h

580

u32 reg_addr, u32 reg_val,

sys/dev/ixl/i40e_prototype.h

582

void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);

sys/dev/ixl/i40e_prototype.h

587

u32 reg_addr, u32 reg_val,

sys/dev/ixl/i40e_prototype.h

593

u32 reg_addr, u32 *reg_val,

sys/dev/qat/include/common/icp_qat_uclo.h

293

unsigned int reg_addr;

sys/dev/qat/include/common/icp_qat_uclo.h

326

unsigned int reg_addr;

sys/dev/qat/qat_common/qat_hal.c

1453

unsigned short reg_addr;

sys/dev/qat/qat_common/qat_hal.c

1459

reg_addr = qat_hal_get_reg_addr(reg_type, reg_num);

sys/dev/qat/qat_common/qat_hal.c

1460

if (reg_addr == BAD_REGADDR) {

sys/dev/qat/qat_common/qat_hal.c

1461

pr_err("QAT: bad regaddr=0x%x\n", reg_addr);

sys/dev/qat/qat_common/qat_hal.c

1466

insts = 0xA070000000ull | (reg_addr & 0x3ff);

sys/dev/qat/qat_common/qat_hal.c

1469

insts = (uint64_t)0xA030000000ull | ((reg_addr & 0x3ff) << 10);

sys/dev/qat/qat_common/qat_hal.c

1699

unsigned int reg_addr;

sys/dev/qat/qat_common/qat_hal.c

1717

reg_addr = reg_num + (ctx << 0x5);

sys/dev/qat/qat_common/qat_hal.c

1721

SET_AE_XFER(handle, ae, reg_addr, val);

sys/dev/qat/qat_common/qat_hal.c

1725

SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val);

sys/dev/qat/qat_common/qat_hal.c

317

unsigned short reg_addr;

sys/dev/qat/qat_common/qat_hal.c

322

reg_addr = 0x80 | (reg_num & 0x7f);

sys/dev/qat/qat_common/qat_hal.c

326

reg_addr = reg_num & 0x1f;

sys/dev/qat/qat_common/qat_hal.c

331

reg_addr = 0x180 | (reg_num & 0x1f);

sys/dev/qat/qat_common/qat_hal.c

334

reg_addr = 0x140 | ((reg_num & 0x3) << 1);

sys/dev/qat/qat_common/qat_hal.c

339

reg_addr = 0x1c0 | (reg_num & 0x1f);

sys/dev/qat/qat_common/qat_hal.c

342

reg_addr = 0x100 | ((reg_num & 0x3) << 1);

sys/dev/qat/qat_common/qat_hal.c

345

reg_addr = 0x280 | (reg_num & 0x1f);

sys/dev/qat/qat_common/qat_hal.c

348

reg_addr = 0x200;

sys/dev/qat/qat_common/qat_hal.c

351

reg_addr = 0x220;

sys/dev/qat/qat_common/qat_hal.c

354

reg_addr = 0x2c0;

sys/dev/qat/qat_common/qat_hal.c

357

reg_addr = 0x2e0;

sys/dev/qat/qat_common/qat_hal.c

360

reg_addr = 0x300 | (reg_num & 0xff);

sys/dev/qat/qat_common/qat_hal.c

363

reg_addr = BAD_REGADDR;

sys/dev/qat/qat_common/qat_hal.c

366

return reg_addr;

sys/dev/qat/qat_common/qat_uclo.c

1000

(unsigned short)init_regsym->reg_addr,

sys/dev/qat/qat_common/qat_uclo.c

1015

(unsigned short)init_regsym->reg_addr,

sys/dev/qat/qat_common/qat_uclo.c

929

unsigned short reg_addr,