pll_type
enum pll_type type;
enum pll_type type;
enum pll_type type;
enum pll_type type;
caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
uint8_t pll_type; /**< PLL type */
caps->pll_type, CC_TFS(jtag_master));
uint32_t pll_type, uint32_t n, uint32_t m)
KASSERT(bhnd_pwrctl_si_clkreg_m(cid, pll_type, NULL) != 0,
rate = bhnd_pwrctl_clock_rate(pll_type, n, m);
if (pll_type == CHIPC_PLL_TYPE3)
uint8_t pll_type, uint32_t *fixed_hz)
switch (pll_type) {
uint32_t pll_type, uint32_t n, uint32_t m)
KASSERT(bhnd_pwrctl_cpu_clkreg_m(cid, pll_type, NULL) != 0,
return (bhnd_pwrctl_clock_rate(pll_type, n, m));
bhnd_pwrctl_clock_rate(uint32_t pll_type, uint32_t n, uint32_t m)
switch (pll_type) {
printf("unsupported PLL type %u\n", pll_type);
if (pll_type == CHIPC_PLL_TYPE3 || pll_type == CHIPC_PLL_TYPE7) {
switch (pll_type) {
if (pll_type == CHIPC_PLL_TYPE1 || pll_type == CHIPC_PLL_TYPE3)
panic("unhandled PLL type %u\n", pll_type);
creg = bhnd_pwrctl_si_clkreg_m(cid, ccaps->pll_type, &rate);
return (bhnd_pwrctl_si_clock_rate(cid, ccaps->pll_type, n, m));
uint8_t pll_type, uint32_t *fixed_hz)
switch (pll_type) {
uint32_t bhnd_pwrctl_clock_rate(uint32_t pll_type, uint32_t n,
uint8_t pll_type, uint32_t *fixed_hz);
uint32_t pll_type, uint32_t n, uint32_t m);
uint8_t pll_type, uint32_t *fixed_hz);
uint32_t pll_type, uint32_t n, uint32_t m);