sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1024

struct pll_sc *sc;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

1057

struct pll_sc *sc;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

410

sizeof(struct pll_sc), clknode_class);

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

413

pll_enable(struct pll_sc *sc)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

426

pll_disable(struct pll_sc *sc)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

439

pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

456

reg_to_pdiv(struct pll_sc *sc, uint32_t reg)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

489

get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

502

set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

515

is_locked(struct pll_sc *sc)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

539

wait_for_lock(struct pll_sc *sc)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

556

plle_enable(struct pll_sc *sc)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

672

struct pll_sc *sc;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

691

struct pll_sc *sc;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

701

pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

765

plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

777

pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

803

plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

872

pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

884

pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

958

struct pll_sc *sc;

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

999

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1026

plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1095

pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1112

pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1222

pllx_init(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1250

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1304

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1334

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

1376

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

595

sizeof(struct pll_sc), clknode_class);

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

598

pll_enable(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

612

pll_disable(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

625

pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

646

reg_to_pdiv(struct pll_sc *sc, uint32_t reg)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

682

get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

695

set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

708

is_locked(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

732

wait_for_lock(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

749

plle_enable(struct pll_sc *sc)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

870

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

889

struct pll_sc *sc;

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

899

pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

963

plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

975

pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

987

pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

999

plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)