Symbol: mnp_bits
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
1074
sc->mnp_bits = clkdef->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
113
struct mnp_bits mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
225
.mnp_bits = {8, 8, 1, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
238
.mnp_bits = {8, 8, 4, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
251
.mnp_bits = {8, 8, 4, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
262
.mnp_bits = {2, 8, 3, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
273
.mnp_bits = {2, 8, 3, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
286
.mnp_bits = {8, 8, 4, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
296
.mnp_bits = {5, 10, 3, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
306
.mnp_bits = {5, 10, 3, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
317
.mnp_bits = {5, 10, 1, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
327
.mnp_bits = {5, 11, 3, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
340
.mnp_bits = {8, 8, 4, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
353
.mnp_bits = {8, 8, 4, 16},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
363
.mnp_bits = {8, 8, 4, 24},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
376
.mnp_bits = {8, 8, 4, 20},
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
397
struct mnp_bits mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
492
struct mnp_bits *mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
494
mnp_bits = &sc->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
496
*m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
497
*n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
498
*p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
505
struct mnp_bits *mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
507
mnp_bits = &sc->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
508
val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
509
val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
510
val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
705
struct mnp_bits *mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
708
mnp_bits = &sc->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
709
if (m >= (1 << mnp_bits->m_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
711
if (n >= (1 << mnp_bits->n_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
713
if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
733
reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
734
reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
735
reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
736
mnp_bits->p_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
809
struct mnp_bits *mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
813
mnp_bits = &sc->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
827
for (m = 1; m < (1 << mnp_bits->m_width); m++) {
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
833
if (n >= (1 << mnp_bits->n_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
888
struct mnp_bits *mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
891
mnp_bits = &sc->mnp_bits;
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
898
if (m >= (1 << mnp_bits->m_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
900
if (n >= (1 << mnp_bits->n_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
902
if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
920
reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
921
reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
922
reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
923
mnp_bits->p_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1032
struct mnp_bits *mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1036
mnp_bits = &sc->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1050
for (m = 1; m < (1 << mnp_bits->m_width); m++) {
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1056
if (n >= (1 << mnp_bits->n_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1114
struct mnp_bits *mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1120
mnp_bits = &sc->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1136
if (m >= (1 << mnp_bits->m_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1138
if (n >= (1 << mnp_bits->n_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1140
if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1154
reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1155
mnp_bits->p_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1191
reg = set_masked(reg, n, mnp_bits->n_shift,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1192
mnp_bits->n_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1209
reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1210
mnp_bits->p_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
139
struct mnp_bits mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
1392
sc->mnp_bits = clkdef->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
280
.mnp_bits = {8, 8, 5, 0, 8, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
292
.mnp_bits = {8, 8, 5, 0, 8, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
304
.mnp_bits = {8, 8, 5, 0, 8, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
315
.mnp_bits = {8, 8, 5, 0, 10, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
326
.mnp_bits = {8, 8, 5, 0, 10, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
337
.mnp_bits = {8, 8, 5, 0, 10, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
350
.mnp_bits = {8, 8, 5, 0, 8, 19},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
366
.mnp_bits = {8, 8, 5, 0, 10, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
378
.mnp_bits = {8, 8, 5, 0, 8, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
389
.mnp_bits = {8, 8, 5, 0, 8, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
402
.mnp_bits = {8, 8, 5, 0, 8, 16},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
414
.mnp_bits = {8, 8, 3, 0, 11, 20},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
427
.mnp_bits = {8, 8, 5, 0, 8, 19},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
440
.mnp_bits = {8, 8, 5, 0, 8, 16},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
450
.mnp_bits = {8, 8, 5, 0, 8, 24},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
463
.mnp_bits = {8, 8, 5, 0, 8, 19},
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
582
struct mnp_bits mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
685
struct mnp_bits *mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
687
mnp_bits = &sc->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
689
*m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
690
*n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
691
*p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
698
struct mnp_bits *mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
700
mnp_bits = &sc->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
701
val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
702
val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
703
val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
903
struct mnp_bits *mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
906
mnp_bits = &sc->mnp_bits;
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
907
if (m >= (1 << mnp_bits->m_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
909
if (n >= (1 << mnp_bits->n_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
911
if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
931
reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
932
reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
933
reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
934
mnp_bits->p_width);