igu_sb_id
bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
int igu_sb_id;
for (igu_sb_id = 0;
igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
igu_sb_id++) {
val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
sc->igu_dsb_id = igu_sb_id;
sc->igu_base_sb = igu_sb_id;
uint8_t igu_sb_id,
igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
int igu_sb_id,
hc_sm->igu_sb_id = igu_sb_id;
int igu_sb_id)
bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
fp->igu_sb_id;
fp->fw_sb_id, fp->igu_sb_id);
idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
sp_sb_data.igu_sb_id = igu_sp_sb_index;
void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
uint8_t igu_sb_id,
uint8_t igu_sb_id,
bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
} else if (igu_sb_id != sc->igu_dsb_id) {
bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
uint8_t igu_sb_id; /* status block number in HW */
uint8_t igu_sb_id /* sb_id within the IGU */;
uint8_t igu_sb_id /* sb_id within the IGU */;
uint8_t igu_sb_id /* sb_id within the IGU */;
uint8_t igu_sb_id /* sb_id within the IGU */;
int i, igu_sb_id;
for (igu_sb_id = 0;
igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
igu_sb_id++) {
p_block = &p_igu_info->entry[igu_sb_id];
STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
u16 igu_sb_id, u32 pi_index,
sb_offset = igu_sb_id * PIS_PER_SB_E4;
_ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
dma_addr_t sb_phys, u16 igu_sb_id,
igu_sb_id * sizeof(u64), 2,
igu_sb_id * sizeof(u64), 2,
CAU_REG_SB_ADDR_MEMORY_RT_OFFSET+igu_sb_id*2,
CAU_REG_SB_VAR_MEMORY_RT_OFFSET+igu_sb_id*2,
_ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
igu_sb_id, TX_PI(i),
sb_info->igu_sb_id, 0, 0);
u16 igu_sb_id;
igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
if (igu_sb_id == ECORE_SB_INVALID_IDX)
"Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
"SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
return igu_sb_id;
sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
p_block = &p_info->entry[sb_info->igu_sb_id];
(sb_info->igu_sb_id << 3);
((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
p_block = &p_info->entry[sb_info->igu_sb_id];
return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
u16 igu_sb_id,
u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
sb_bit = 1 << (igu_sb_id % 32);
sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
val, igu_sb_id);
u16 igu_sb_id, u16 opaque, bool b_set)
p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
igu_sb_id, p_block->function_id, p_block->is_pf,
ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
((igu_sb_id / 32) * 4));
if (val & (1 << (igu_sb_id % 32)))
igu_sb_id);
CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
u16 igu_sb_id = 0;
for (igu_sb_id = 0;
igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
igu_sb_id++) {
p_block = &p_info->entry[igu_sb_id];
ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
u16 igu_sb_id;
for (igu_sb_id = p_info->igu_dsb_id;
igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
igu_sb_id++) {
p_block = &p_info->entry[igu_sb_id];
sizeof(u32) * igu_sb_id);
sizeof(u32) * igu_sb_id,
igu_sb_id, p_block->function_id,
u16 igu_sb_id)
IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
p_block->igu_sb_id = igu_sb_id;
u16 igu_sb_id;
for (igu_sb_id = 0;
igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
igu_sb_id++) {
ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
p_block = &p_igu_info->entry[igu_sb_id];
p_igu_info->igu_dsb_id = igu_sb_id;
igu_sb_id, p_block->function_id,
u16 igu_sb_id = 0, vf_num = 0;
igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
if (igu_sb_id == ECORE_SB_INVALID_IDX)
for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
igu_sb_id++) {
p_block = &p_info->entry[igu_sb_id];
if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
igu_sb_id, vf_num,
igu_sb_id, p_block->function_id,
u16 sbid = p_sb->igu_sb_id;
u16 igu_sb_id;
u16 igu_sb_id;
p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
u16 igu_sb_id, sb_id;
igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
OSAL_CPU_TO_LE16(igu_sb_id);
sizeof(u32) * p_block->igu_sb_id, val);
p_block->igu_sb_id * sizeof(u64), 2,
sb_dummy.igu_sb_id = req->hw_sb;
sb_dummy.igu_sb_id = req->hw_sb;
vf->igu_sbs[qid] = p_block->igu_sb_id;