descriptor
struct dsc$descriptor AscTimeDesc = { 0, DSC$K_DTYPE_T, DSC$K_CLASS_S, NULL };
i386_get_ldt(int start, union descriptor *descs, int num)
i386_set_ldt(int start, union descriptor *descs, int num)
for (c = 0; c != dev->descriptor.bNumConfigurations; c++) {
if (dev->descriptor.bNumConfigurations == 0) {
size = dev->descriptor.bNumConfigurations *
for (x = 0; x != dev->descriptor.bNumConfigurations; x++) {
if (i == dev->descriptor.bNumConfigurations) {
udev->descriptor.bLength = sizeof(udev->descriptor);
udev->descriptor.bDescriptorType = ddesc->bDescriptorType;
udev->descriptor.bcdUSB = ddesc->bcdUSB;
udev->descriptor.bDeviceClass = ddesc->bDeviceClass;
udev->descriptor.bDeviceSubClass = ddesc->bDeviceSubClass;
udev->descriptor.bDeviceProtocol = ddesc->bDeviceProtocol;
udev->descriptor.bMaxPacketSize0 = ddesc->bMaxPacketSize0;
udev->descriptor.idVendor = ddesc->idVendor;
udev->descriptor.idProduct = ddesc->idProduct;
udev->descriptor.bcdDevice = ddesc->bcdDevice;
udev->descriptor.iManufacturer = ddesc->iManufacturer;
udev->descriptor.iProduct = ddesc->iProduct;
udev->descriptor.iSerialNumber = ddesc->iSerialNumber;
udev->descriptor.bNumConfigurations =
if (udev->descriptor.bNumConfigurations > USB_MAXCONFIG) {
udev->descriptor.bNumConfigurations = USB_MAXCONFIG;
struct usb_device_descriptor descriptor;
uint8_t descriptor[];
bcopy(&udev->ddesc, &udev->descriptor,
sizeof(udev->descriptor));
uint32_t rx_desc_vlan_stripping, uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rpo_descdvl_strip_adr(descriptor),
uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, tdm_descden_adr(descriptor), tdm_descden_msk,
tdm_tx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
return AQ_READ_REG_BIT(aq_hw, tdm_descdhd_adr(descriptor),
uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, tdm_descdlen_adr(descriptor), tdm_descdlen_msk,
uint32_t tx_desc_wr_wb_threshold, uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, tdm_descdwrb_thresh_adr(descriptor),
uint32_t rx_desc_data_buff_size, uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descddata_size_adr(descriptor),
uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descden_adr(descriptor), rdm_descden_msk,
uint32_t rx_desc_head_buff_size, uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descdhdr_size_adr(descriptor),
uint32_t rx_desc_head_splitting, uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descdhdr_split_adr(descriptor),
rdm_rx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
return AQ_READ_REG_BIT(aq_hw, rdm_descdhd_adr(descriptor),
uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descdlen_adr(descriptor), rdm_descdlen_msk,
uint32_t descriptor)
AQ_WRITE_REG_BIT(aq_hw, rdm_descdreset_adr(descriptor),
uint32_t rx_dma_desc_base_addrlsw, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrlsw_adr(descriptor),
uint32_t rx_dma_desc_base_addrmsw, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, rx_dma_desc_base_addrmsw_adr(descriptor),
reg_rx_dma_desc_status_get(struct aq_hw *aq_hw, uint32_t descriptor)
return AQ_READ_REG(aq_hw, rx_dma_desc_stat_adr(descriptor));
uint32_t rx_dma_desc_tail_ptr, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor),
reg_rx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
return AQ_READ_REG(aq_hw, rx_dma_desc_tail_ptr_adr(descriptor));
uint32_t tx_dma_desc_base_addrlsw, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrlsw_adr(descriptor),
uint32_t tx_dma_desc_base_addrmsw, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, tx_dma_desc_base_addrmsw_adr(descriptor),
uint32_t tx_dma_desc_tail_ptr, uint32_t descriptor)
AQ_WRITE_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor),
reg_tx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
return AQ_READ_REG(aq_hw, tx_dma_desc_tail_ptr_adr(descriptor));
uint32_t rx_desc_data_buff_size, uint32_t descriptor);
uint32_t descriptor);
uint32_t rx_desc_head_splitting, uint32_t descriptor);
uint32_t rdm_rx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
uint32_t descriptor);
uint32_t rx_desc_head_buff_size, uint32_t descriptor);
uint32_t descriptor);
uint32_t rx_dma_desc_base_addrlsw, uint32_t descriptor);
uint32_t rx_dma_desc_base_addrmsw, uint32_t descriptor);
uint32_t reg_rx_dma_desc_status_get(struct aq_hw *aq_hw, uint32_t descriptor);
uint32_t rx_dma_desc_tail_ptr, uint32_t descriptor);
uint32_t reg_rx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
uint32_t tx_dma_desc_base_addrlsw, uint32_t descriptor);
uint32_t tx_dma_desc_base_addrmsw, uint32_t descriptor);
uint32_t tx_dma_desc_tail_ptr, uint32_t descriptor);
uint32_t reg_tx_dma_desc_tail_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
uint32_t rx_desc_vlan_stripping, uint32_t descriptor);
uint32_t descriptor);
uint32_t tdm_tx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor);
uint32_t descriptor);
uint32_t tx_desc_wr_wb_threshold, uint32_t descriptor);
#define rpo_descdvl_strip_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
#define tdm_descden_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
#define tdm_descdhd_adr(descriptor) (0x00007c0c + (descriptor) * 0x40)
#define tdm_descdlen_adr(descriptor) (0x00007c08 + (descriptor) * 0x40)
#define rdm_descddata_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
#define tdm_descdwrb_thresh_adr(descriptor) (0x00007c18 + (descriptor) * 0x40)
#define tdm_desc_den_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
#define tdm_desc_dhd_adr(descriptor) (0x00007C0C + (descriptor) * 0x40)
#define tdm_desc_dlen_adr(descriptor) (0x00007C08 + (descriptor) * 0x40)
#define tdm_desc_dwrb_thresh_adr(descriptor) \
(0x00007C18 + (descriptor) * 0x40)
#define rdm_descden_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
#define rdm_descdhdr_size_adr(descriptor) (0x00005b18 + (descriptor) * 0x20)
#define rdm_descdhdr_split_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
#define tx_dma_desc_base_addrmsw_adr(descriptor) \
(0x00007c04u + (descriptor) * 0x40)
#define rdm_descdhd_adr(descriptor) (0x00005b0c + (descriptor) * 0x20)
#define rdm_descdlen_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
#define rdm_descdreset_adr(descriptor) (0x00005b08 + (descriptor) * 0x20)
#define rx_dma_desc_base_addrlsw_adr(descriptor) \
(0x00005b00u + (descriptor) * 0x20)
#define rx_dma_desc_base_addrmsw_adr(descriptor) \
(0x00005b04u + (descriptor) * 0x20)
#define rx_dma_desc_stat_adr(descriptor) (0x00005b14u + (descriptor) * 0x20)
#define rx_dma_desc_tail_ptr_adr(descriptor) (0x00005b10u + (descriptor) * 0x20)
#define tx_dma_desc_base_addrlsw_adr(descriptor) \
(0x00007c00u + (descriptor) * 0x40)
#define tx_dma_desc_tail_ptr_adr(descriptor) (0x00007c10u + (descriptor) * 0x40)
struct gve_device_descriptor *descriptor,
char *desc_end = (char *)descriptor + be16toh(descriptor->total_length);
const int num_options = be16toh(descriptor->num_device_options);
dev_opt = (void *)(descriptor + 1);
gve_parse_device_option(priv, descriptor, dev_opt,
agsaSgl_t descriptor[MAX_ESGL_ENTRIES];
agSgl = &(agEsgl->descriptor[i]);
sglSplitVirtualAddr = &(agEsgl->descriptor[satIOContext->SplitIdx]);
agSgl = &(agEsgl->descriptor[0]);
agSgl = &(agEsgl->descriptor[i]);
agSgl = &(agEsgl->descriptor[splitIdx]);
agSgl = &(agEsgl->descriptor[i]);
pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = 0;
CLEAR_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = PagePhysAddrLower;
pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = PagePhysAddrUpper;
pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = PageSizeInBytes; /* sizeof (agsaEsgl_t)*/
SET_ESGL_EXTEND(pEsglPageInfo->agEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgLower = page_to_fill->physAddressLower;
PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].sgUpper = page_to_fill->physAddressUpper;
PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].len = numSgElements;
SET_ESGL_EXTEND(PrevagEsgl->descriptor[MAX_ESGL_ENTRIES-1].extReserved);
struct usb_device_descriptor descriptor;
uint8_t descriptor;
reg->descriptor = raw.descriptor;
union descriptor *p_gdt;
union descriptor desc;
gdt = pmap_trm_alloc(sizeof(union descriptor) * NGDT * mp_ncpus,
bcopy(gdt0, gdt, sizeof(union descriptor) * NGDT);
ldt = pmap_trm_alloc(sizeof(union descriptor) * NLDT,
union descriptor gdt0[NGDT]; /* initial global descriptor table */
union descriptor *gdt = gdt0; /* global descriptor table */
union descriptor *ldt; /* local descriptor table */
.ssd_limit = sizeof(union descriptor) * NLDT - 1,
.ssd_limit = (512 * sizeof(union descriptor)-1),
union descriptor *lp;
lp = malloc(kargs.largs.num * sizeof(union descriptor),
kargs.largs.num * sizeof(union descriptor));
new_ldt->ldt_base = pmap_trm_alloc(len * sizeof(union descriptor),
gdt_segs[GUSERLDT_SEL].ssd_limit = len * sizeof(union descriptor) - 1;
len * sizeof(union descriptor));
bcopy(ldt, new_ldt->ldt_base, sizeof(union descriptor) * NLDT);
sizeof(union descriptor));
data = malloc(num * sizeof(union descriptor), M_TEMP, M_WAITOK);
&((union descriptor *)(pldt->ldt_base))[uap->start] :
&ldt[uap->start], data, num * sizeof(union descriptor));
error = copyout(data, uap->descs, num * sizeof(union descriptor));
union descriptor *descs)
union descriptor *dp;
dp = &((union descriptor *)(pldt->ldt_base))[NLDT];
union descriptor *descs)
union descriptor *descs);
new_ldt->ldt_len * sizeof(union descriptor));
sizeof(union descriptor));
extern union descriptor *gdt;
extern union descriptor *ldt;
union descriptor desc;
ldt.num = uap->bytecount / sizeof(union descriptor);
td->td_retval[0] *= sizeof(union descriptor);
union descriptor;
int i386_get_ldt(int, union descriptor *, int);
int i386_set_ldt(int, union descriptor *, int);
union descriptor;
int i386_set_ldt(struct thread *, struct i386_ldt_args *, union descriptor *);
union descriptor *descs;