sys/arm64/coresight/coresight_fdt.c

113

pcell_t cpu_reg;

sys/arm64/coresight/coresight_fdt.c

117

if (OF_getencprop(cpu_node, "reg", (void *)&cpu_reg,

sys/arm64/coresight/coresight_fdt.c

118

sizeof(cpu_reg)) > 0) {

sys/arm64/coresight/coresight_fdt.c

119

pdata->cpu = cpu_reg;

sys/dev/bce/if_bce.c

3969

bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,

sys/dev/bce/if_bce.c

3976

bce_halt_cpu(sc, cpu_reg);

sys/dev/bce/if_bce.c

3979

offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);

sys/dev/bce/if_bce.c

3989

offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);

sys/dev/bce/if_bce.c

3999

offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);

sys/dev/bce/if_bce.c

4009

offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);

sys/dev/bce/if_bce.c

4019

offset = cpu_reg->spad_base +

sys/dev/bce/if_bce.c

4020

(fw->rodata_addr - cpu_reg->mips_view_base);

sys/dev/bce/if_bce.c

4030

REG_WR_IND(sc, cpu_reg->inst, 0);

sys/dev/bce/if_bce.c

4031

REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);

sys/dev/bce/if_bce.c

4045

bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)

sys/dev/bce/if_bce.c

4052

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/bce/if_bce.c

4053

val &= ~cpu_reg->mode_value_halt;

sys/dev/bce/if_bce.c

4054

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/bce/if_bce.c

4055

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/bce/if_bce.c

4067

bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)

sys/dev/bce/if_bce.c

4074

val = REG_RD_IND(sc, cpu_reg->mode);

sys/dev/bce/if_bce.c

4075

val |= cpu_reg->mode_value_halt;

sys/dev/bce/if_bce.c

4076

REG_WR_IND(sc, cpu_reg->mode, val);

sys/dev/bce/if_bce.c

4077

REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);

sys/dev/bce/if_bce.c

4091

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4095

cpu_reg.mode = BCE_RXP_CPU_MODE;

sys/dev/bce/if_bce.c

4096

cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4097

cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4098

cpu_reg.state = BCE_RXP_CPU_STATE;

sys/dev/bce/if_bce.c

4099

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4100

cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4101

cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4102

cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4103

cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4104

cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4105

cpu_reg.spad_base = BCE_RXP_SCRATCH;

sys/dev/bce/if_bce.c

4106

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

4109

bce_start_cpu(sc, &cpu_reg);

sys/dev/bce/if_bce.c

4123

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4128

cpu_reg.mode = BCE_RXP_CPU_MODE;

sys/dev/bce/if_bce.c

4129

cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4130

cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4131

cpu_reg.state = BCE_RXP_CPU_STATE;

sys/dev/bce/if_bce.c

4132

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4133

cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4134

cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4135

cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4136

cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4137

cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4138

cpu_reg.spad_base = BCE_RXP_SCRATCH;

sys/dev/bce/if_bce.c

4139

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

420

struct cpu_reg *, struct fw_info *);

sys/dev/bce/if_bce.c

4204

bce_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/bce/if_bce.c

421

static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);

sys/dev/bce/if_bce.c

422

static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);

sys/dev/bce/if_bce.c

4220

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4225

cpu_reg.mode = BCE_TXP_CPU_MODE;

sys/dev/bce/if_bce.c

4226

cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4227

cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4228

cpu_reg.state = BCE_TXP_CPU_STATE;

sys/dev/bce/if_bce.c

4229

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4230

cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4231

cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4232

cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4233

cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4234

cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4235

cpu_reg.spad_base = BCE_TXP_SCRATCH;

sys/dev/bce/if_bce.c

4236

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

4301

bce_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/bce/if_bce.c

4302

bce_start_cpu(sc, &cpu_reg);

sys/dev/bce/if_bce.c

4316

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4321

cpu_reg.mode = BCE_TPAT_CPU_MODE;

sys/dev/bce/if_bce.c

4322

cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4323

cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4324

cpu_reg.state = BCE_TPAT_CPU_STATE;

sys/dev/bce/if_bce.c

4325

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4326

cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4327

cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4328

cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4329

cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4330

cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4331

cpu_reg.spad_base = BCE_TPAT_SCRATCH;

sys/dev/bce/if_bce.c

4332

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

4397

bce_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/bce/if_bce.c

4398

bce_start_cpu(sc, &cpu_reg);

sys/dev/bce/if_bce.c

4412

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4417

cpu_reg.mode = BCE_CP_CPU_MODE;

sys/dev/bce/if_bce.c

4418

cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4419

cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4420

cpu_reg.state = BCE_CP_CPU_STATE;

sys/dev/bce/if_bce.c

4421

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4422

cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4423

cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4424

cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4425

cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4426

cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4427

cpu_reg.spad_base = BCE_CP_SCRATCH;

sys/dev/bce/if_bce.c

4428

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

4493

bce_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/bce/if_bce.c

4494

bce_start_cpu(sc, &cpu_reg);

sys/dev/bce/if_bce.c

4508

struct cpu_reg cpu_reg;

sys/dev/bce/if_bce.c

4513

cpu_reg.mode = BCE_COM_CPU_MODE;

sys/dev/bce/if_bce.c

4514

cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;

sys/dev/bce/if_bce.c

4515

cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;

sys/dev/bce/if_bce.c

4516

cpu_reg.state = BCE_COM_CPU_STATE;

sys/dev/bce/if_bce.c

4517

cpu_reg.state_value_clear = 0xffffff;

sys/dev/bce/if_bce.c

4518

cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;

sys/dev/bce/if_bce.c

4519

cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;

sys/dev/bce/if_bce.c

4520

cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;

sys/dev/bce/if_bce.c

4521

cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;

sys/dev/bce/if_bce.c

4522

cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;

sys/dev/bce/if_bce.c

4523

cpu_reg.spad_base = BCE_COM_SCRATCH;

sys/dev/bce/if_bce.c

4524

cpu_reg.mips_view_base = 0x8000000;

sys/dev/bce/if_bce.c

4589

bce_load_cpu_fw(sc, &cpu_reg, &fw);

sys/dev/bce/if_bce.c

4590

bce_start_cpu(sc, &cpu_reg);

sys/riscv/riscv/mp_machdep.c

348

cpu_reg[id][0] = reg[0];

sys/riscv/riscv/mp_machdep.c

350

cpu_reg[id][1] = reg[1];

sys/riscv/riscv/mp_machdep.c

92

static uint32_t cpu_reg[MAXCPU][2];