cycle
int64_t cycle;
cycle = bar->b_cycle;
} while (cycle == bar->b_cycle);
new_thread->cycle++;
_thr_umtx_wake(&new_thread->cycle, INT_MAX, 0);
curthread->cycle++;
_thr_umtx_wake(&curthread->cycle, INT_MAX, 0);
uint32_t cycle;
thread->cycle++;
_thr_umtx_wake(&thread->cycle, 1, 0);
uint32_t cycle;
curthread->cycle++;
cycle = curthread->cycle;
_thr_umtx_wake(&curthread->cycle, INT_MAX, 0);
_thr_umtx_wait_uint(&curthread->cycle, cycle, NULL, 0);
tmp = thread->cycle;
_thr_umtx_wait_uint(&thread->cycle, tmp, NULL, 0);
uint32_t cycle;
event->etr.cycle++;
uint64_t cycle;
int sec, cycle, cycle_match;
cycle = cycle_now & 0x1fff;
cycle = cycle + CYCLE_DELAY;
if (cycle >= 8000) {
cycle -= 8000;
cycle = roundup2(cycle, CYCLE_MOD);
if (cycle >= 8000) {
if (cycle == 8000)
cycle = 0;
cycle = CYCLE_MOD;
cycle_match = ((sec << 13) | cycle) & 0x7ffff;
#define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
(cycle), \
#define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
(cycle), \
#define INCREMENT_QUEUE_GET(index, cycle, entry_count, bit_toggle) \
(cycle) = (cycle) ^ (bit_toggle); \
min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
int cycle; /* minimum cycle time [ns] */
#define rdcycle() csr_read64(cycle)
DECLARE_CSR(cycle, CSR_CYCLE)
int cycle;
cycle = 0;
cycle += 1;
cyclenlp = &cyclenl[cycle];
cyclenlp -> cycleno = cycle; /* internal number of cycle on */
printf( " is the head of cycle %d\n" , cycle );
memberp -> cycleno = cycle;
if ( arcp -> arc_parentp -> cycleno == cycle ) {
int cycle;
for ( cycle = 1 ; cycle <= ncycle ; cycle += 1 ) {
cyclenlp = &cyclenl[ cycle ];
cycle {
int system=-1, pad_acc, cycle_acc, cycle, f_frac;
cycle = 1;
cycle_acc = frame_cycle[system].d * cycle;
ciph->fdf.dv.cyc = htons(cycle << 12 | f_frac);
cycle ++;
cycle ++;