Symbol: csr
crypto/openssl/apps/cmp.c
1763
X509_REQ *csr = NULL;
crypto/openssl/apps/cmp.c
1980
csr = load_csr_autofmt(opt_csr, FORMAT_UNDEF, NULL, "PKCS#10 CSR");
crypto/openssl/apps/cmp.c
1981
if (csr == NULL)
crypto/openssl/apps/cmp.c
1983
if (!OSSL_CMP_CTX_set1_p10CSR(ctx, csr))
crypto/openssl/apps/cmp.c
1990
X509V3_set_ctx(&ext_ctx, NULL, NULL, csr, NULL, X509V3_CTX_REPLACE);
crypto/openssl/apps/cmp.c
2006
X509_REQ_free(csr);
crypto/openssl/apps/cmp.c
2077
X509_REQ_free(csr);
crypto/openssl/apps/lib/apps.c
517
X509_REQ *csr;
crypto/openssl/apps/lib/apps.c
520
csr = load_csr(infile, format, desc);
crypto/openssl/apps/lib/apps.c
525
csr = load_csr(infile, FORMAT_PEM, NULL /* desc */);
crypto/openssl/apps/lib/apps.c
527
if (csr == NULL) {
crypto/openssl/apps/lib/apps.c
529
csr = load_csr(infile, FORMAT_ASN1, NULL /* desc */);
crypto/openssl/apps/lib/apps.c
531
if (csr == NULL) {
crypto/openssl/apps/lib/apps.c
536
if (csr != NULL) {
crypto/openssl/apps/lib/apps.c
537
EVP_PKEY *pkey = X509_REQ_get0_pubkey(csr);
crypto/openssl/apps/lib/apps.c
538
int ret = do_X509_REQ_verify(csr, pkey, vfyopts);
crypto/openssl/apps/lib/apps.c
544
return csr;
crypto/openssl/apps/lib/apps.c
546
return csr;
crypto/openssl/include/openssl/cmp.h
583
int OSSL_CMP_CTX_set1_p10CSR(OSSL_CMP_CTX *ctx, const X509_REQ *csr);
crypto/openssl/test/cmp_client_test.c
371
X509_REQ *csr = NULL;
crypto/openssl/test/cmp_client_test.c
378
if (!TEST_ptr(csr = load_csr_der(pkcs10_f, libctx))
crypto/openssl/test/cmp_client_test.c
379
|| !TEST_true(OSSL_CMP_CTX_set1_p10CSR(ctx, csr))
crypto/openssl/test/cmp_client_test.c
385
X509_REQ_free(csr);
crypto/openssl/test/testutil/load.c
100
csr = X509_REQ_new_ex(libctx, NULL);
crypto/openssl/test/testutil/load.c
101
if (TEST_ptr(csr))
crypto/openssl/test/testutil/load.c
102
(void)TEST_ptr(d2i_X509_REQ_bio(bio, &csr));
crypto/openssl/test/testutil/load.c
104
return csr;
crypto/openssl/test/testutil/load.c
94
X509_REQ *csr = NULL;
sbin/ifconfig/ifieee80211.c
850
struct ieee80211_chanswitch_req csr;
sbin/ifconfig/ifieee80211.c
852
getchannel(ctx, &csr.csa_chan, val);
sbin/ifconfig/ifieee80211.c
853
csr.csa_mode = 1;
sbin/ifconfig/ifieee80211.c
854
csr.csa_count = 5;
sbin/ifconfig/ifieee80211.c
855
set80211(ctx, IEEE80211_IOC_CHANSWITCH, 0, sizeof(csr), &csr);
sys/amd64/amd64/fpu.c
75
#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
sys/arm/freescale/vybrid/vf_edma.h
167
uint16_t csr;
sys/arm/ti/ti_sdma.c
217
uint32_t csr;
sys/arm/ti/ti_sdma.c
236
csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
sys/arm/ti/ti_sdma.c
237
if (csr == 0) {
sys/arm/ti/ti_sdma.c
251
if (csr & DMA4_CSR_DROP)
sys/arm/ti/ti_sdma.c
255
if (csr & DMA4_CSR_SECURE_ERR)
sys/arm/ti/ti_sdma.c
258
if (csr & DMA4_CSR_MISALIGNED_ADRS_ERR)
sys/arm/ti/ti_sdma.c
261
if (csr & DMA4_CSR_TRANS_ERR) {
sys/arm/ti/ti_sdma.c
278
channel->callback(ch, csr, channel->callback_data);
sys/arm/ti/ti_sdma.c
582
uint32_t csr;
sys/arm/ti/ti_sdma.c
597
csr = ti_sdma_read_4(sc, DMA4_CSR(ch));
sys/arm/ti/ti_sdma.c
600
*status = csr;
sys/cam/scsi/scsi_ch.c
197
struct changer_element_status_request *csr);
sys/dev/firewire/firewire.c
1514
uint32_t *csr;
sys/dev/firewire/firewire.c
1521
csr = dfwdev->csrrom;
sys/dev/firewire/firewire.c
1525
err = fw_explore_read_quads(dfwdev, CSRROMOFF, &csr[0], 1);
sys/dev/firewire/firewire.c
1530
hdr = (struct csrhdr *)&csr[0];
sys/dev/firewire/firewire.c
1541
err = fw_explore_read_quads(dfwdev, CSRROMOFF + 0x04, &csr[1], 4);
sys/dev/firewire/firewire.c
1546
binfo = (struct bus_info *)&csr[1];
sys/dev/firewire/firewire.c
1632
if (bcmp(&csr[0], &fwdev->csrrom[0], sizeof(uint32_t) * 5) == 0) {
sys/dev/firewire/firewire.c
1643
bcopy(&csr[0], &fwdev->csrrom[0], sizeof(uint32_t) * 5);
sys/dev/iicbus/rtc/nxprtc.c
446
} csr;
sys/dev/iicbus/rtc/nxprtc.c
451
if ((err = nxprtc_readfrom(sc->dev, PCF85xx_R_CS1, &csr,
sys/dev/iicbus/rtc/nxprtc.c
452
sizeof(csr), WAITFLAGS)) != 0){
sys/dev/iicbus/rtc/nxprtc.c
463
if ((csr.cs3 & PCF8523_M_CS3_PM) == PCF8523_B_CS3_PM_NOBAT ||
sys/dev/iicbus/rtc/nxprtc.c
464
(csr.cs1 & PCF85xx_B_CS1_STOP) || (csr.sec & PCF85xx_B_SECOND_OS)) {
sys/dev/iicbus/rtc/nxprtc.c
529
if (csr.cs1 & PCF2129_B_CS1_12HR)
sys/dev/iicbus/rtc/nxprtc.c
547
if (csr.cs1 & PCF8523_B_CS1_12HR)
sys/dev/iicbus/rtc/nxprtc.c
619
} csr;
sys/dev/iicbus/rtc/nxprtc.c
623
if ((err = nxprtc_readfrom(sc->dev, PCF85xx_R_CS1, &csr,
sys/dev/iicbus/rtc/nxprtc.c
624
sizeof(csr), WAITFLAGS)) != 0){
sys/dev/iicbus/rtc/nxprtc.c
635
if ((csr.cs1 & PCF85xx_B_CS1_STOP) || (csr.sec & PCF85xx_B_SECOND_OS)) {
sys/dev/iwn/if_iwn.c
9165
static char *iwn_get_csr_string(int csr)
sys/dev/iwn/if_iwn.c
9167
switch (csr) {
sys/dev/mii/lxtphy.c
194
int bmcr, bmsr, csr;
sys/dev/mii/lxtphy.c
204
csr = PHY_READ(sc, MII_LXTPHY_CSR);
sys/dev/mii/lxtphy.c
205
if (csr & CSR_LINK)
sys/dev/mii/lxtphy.c
225
if (csr & CSR_SPEED)
sys/dev/mii/lxtphy.c
229
if (csr & CSR_DUPLEX)
sys/dev/oce/oce_hw.c
448
ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);
sys/dev/oce/oce_hw.c
450
OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
sys/dev/oce/oce_hw.c
57
post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
sys/dev/oce/oce_hw.c
62
OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
sys/dev/oce/oce_hw.c
72
post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));
sys/dev/ppc/ppc.c
704
int csr = SMC66x_CSR; /* initial value is 0x3F0 */
sys/dev/ppc/ppc.c
708
#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
sys/dev/ppc/ppc.c
714
outb(csr, SMC665_iCODE);
sys/dev/ppc/ppc.c
715
outb(csr, SMC665_iCODE);
sys/dev/ppc/ppc.c
718
outb(csr, 0xd);
sys/dev/ppc/ppc.c
726
outb(csr, SMC666_iCODE);
sys/dev/ppc/ppc.c
727
outb(csr, SMC666_iCODE);
sys/dev/ppc/ppc.c
730
outb(csr, 0xd);
sys/dev/ppc/ppc.c
737
csr = SMC666_CSR;
sys/dev/ppc/ppc.c
745
outb(csr, 0xaa); /* end config mode */
sys/dev/ppc/ppc.c
750
outb(csr, 0x1);
sys/dev/ppc/ppc.c
755
outb(csr, 0xaa); /* end config mode */
sys/dev/ppc/ppc.c
767
outb(csr, 0x1);
sys/dev/ppc/ppc.c
771
outb(csr, 0x4);
sys/dev/ppc/ppc.c
776
outb(csr, 0x1);
sys/dev/ppc/ppc.c
791
outb(csr, 0x4);
sys/dev/ppc/ppc.c
845
outb(csr, 0x4);
sys/dev/ppc/ppc.c
871
outb(csr, 0xa);
sys/dev/ppc/ppc.c
882
outb(csr, 0x4);
sys/dev/ppc/ppc.c
895
outb(csr, 0xaa); /* end config mode */
sys/dev/qat/include/adf_dev_err.h
74
struct resource *csr,
sys/dev/qat/include/common/adf_accel_devices.h
539
adf_csr_fetch_and_and(struct resource *csr, size_t offs, unsigned long mask)
sys/dev/qat/include/common/adf_accel_devices.h
541
unsigned int val = ADF_CSR_RD(csr, offs);
sys/dev/qat/include/common/adf_accel_devices.h
544
ADF_CSR_WR(csr, offs, val);
sys/dev/qat/include/common/adf_accel_devices.h
548
adf_csr_fetch_and_or(struct resource *csr, size_t offs, unsigned long mask)
sys/dev/qat/include/common/adf_accel_devices.h
550
unsigned int val = ADF_CSR_RD(csr, offs);
sys/dev/qat/include/common/adf_accel_devices.h
553
ADF_CSR_WR(csr, offs, val);
sys/dev/qat/include/common/adf_accel_devices.h
558
struct resource *csr,
sys/dev/qat/include/common/adf_accel_devices.h
564
adf_csr_fetch_and_and(csr, offs, mask);
sys/dev/qat/include/common/adf_accel_devices.h
567
adf_csr_fetch_and_or(csr, offs, mask);
sys/dev/qat/include/common/icp_qat_hal.h
144
#define CAP_CSR_ADDR(csr) (csr + handle->hal_cap_g_ctl_csr_addr_v)
sys/dev/qat/include/common/icp_qat_hal.h
145
#define SET_CAP_CSR(handle, csr, val) \
sys/dev/qat/include/common/icp_qat_hal.h
146
ADF_CSR_WR(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr), val)
sys/dev/qat/include/common/icp_qat_hal.h
147
#define GET_CAP_CSR(handle, csr) \
sys/dev/qat/include/common/icp_qat_hal.h
148
ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
sys/dev/qat/include/common/icp_qat_hal.h
149
#define SET_GLB_CSR(handle, csr, val) \
sys/dev/qat/include/common/icp_qat_hal.h
153
SET_CAP_CSR((handle), (csr), (val)) : \
sys/dev/qat/include/common/icp_qat_hal.h
154
SET_CAP_CSR((handle), (csr) + GLOBAL_CSR, val); \
sys/dev/qat/include/common/icp_qat_hal.h
156
#define GET_GLB_CSR(handle, csr) \
sys/dev/qat/include/common/icp_qat_hal.h
160
GET_CAP_CSR((handle), (csr)) : \
sys/dev/qat/include/common/icp_qat_hal.h
161
GET_CAP_CSR((handle), (csr) + GLOBAL_CSR); \
sys/dev/qat/include/common/icp_qat_hal.h
163
#define SET_FCU_CSR(handle, csr, val) \
sys/dev/qat/include/common/icp_qat_hal.h
166
typeof(csr) csr_ = (csr); \
sys/dev/qat/include/common/icp_qat_hal.h
179
#define GET_FCU_CSR(handle, csr) \
sys/dev/qat/include/common/icp_qat_hal.h
182
typeof(csr) csr_ = (csr); \
sys/dev/qat/include/common/icp_qat_hal.h
192
#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))
sys/dev/qat/include/common/icp_qat_hal.h
193
#define SET_AE_CSR(handle, ae, csr, val) \
sys/dev/qat/include/common/icp_qat_hal.h
194
ADF_CSR_WR(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr), val)
sys/dev/qat/include/common/icp_qat_hal.h
195
#define GET_AE_CSR(handle, ae, csr) \
sys/dev/qat/include/common/icp_qat_hal.h
196
ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr))
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
105
csr.abd,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
110
csr.lllbd,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
149
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr)
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
154
csr.scb_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
159
csr.rmb_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
164
csr.som_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
169
csr.skip_hash_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
174
csr.scb_unload_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
180
csr.disable_token_fusion_ctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
185
csr.lbms,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
190
csr.scb_mode_reset,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
195
csr.lazy,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
200
csr.nice,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
236
icp_qat_hw_decomp_20_config_csr_lower_t csr)
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
241
csr.hbs,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
246
csr.lbms,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
251
csr.algo,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
256
csr.mmctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
262
csr.lbc,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
294
icp_qat_hw_decomp_20_config_csr_upper_t csr)
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
300
csr.sdc,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
305
csr.res4,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
58
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr)
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
63
csr.algo,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
68
csr.sd,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
74
csr.edmm,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
79
csr.hbs,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
84
csr.mmctrl,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
89
csr.hash_col,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
94
csr.hash_update,
sys/dev/qat/qat_api/firmware/include/icp_qat_hw_20_comp.h
99
csr.skip_ctrl,
sys/dev/qat/qat_common/adf_dev_err.c
178
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_common/adf_dev_err.c
184
val = ADF_CSR_RD(csr, adf_err_regs[i].offs);
sys/dev/qat/qat_common/adf_dev_err.c
196
val = adf_accel_err_regs[i].read(csr, accel);
sys/dev/qat/qat_common/adf_dev_err.c
224
struct resource *csr,
sys/dev/qat/qat_common/adf_dev_err.c
227
u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset);
sys/dev/qat/qat_common/adf_dev_err.c
264
ADF_CSR_WR(csr, slice_hang_offset, slice_hang);
sys/dev/qat/qat_common/adf_dev_err.c
280
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_common/adf_dev_err.c
281
u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3);
sys/dev/qat/qat_common/adf_dev_err.c
282
u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5);
sys/dev/qat/qat_common/adf_dev_err.c
306
if (ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)) &
sys/dev/qat/qat_common/adf_dev_err.c
311
csr,
sys/dev/qat/qat_common/adf_freebsd_admin.c
461
struct resource *csr = NULL;
sys/dev/qat/qat_common/adf_freebsd_admin.c
472
csr = pmisc->virt_addr;
sys/dev/qat/qat_common/adf_freebsd_admin.c
571
ADF_CSR_WR(csr, adminmsg_u, reg_val >> 32);
sys/dev/qat/qat_common/adf_freebsd_admin.c
572
ADF_CSR_WR(csr, adminmsg_l, reg_val);
sys/dev/qat/qat_common/adf_freebsd_admin.c
574
admin->mailbox_addr = csr;
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
146
struct resource *csr = bank->csr_addr;
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
152
head = csr_ops->read_csr_ring_head(csr,
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
155
tail = csr_ops->read_csr_ring_tail(csr,
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
158
empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
24
struct resource *csr = ring->bank->csr_addr;
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
36
head = csr_ops->read_csr_ring_head(csr,
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
39
tail = csr_ops->read_csr_ring_tail(csr,
sys/dev/qat/qat_common/adf_freebsd_transport_debug.c
42
empty = csr_ops->read_csr_e_stat(csr, bank->bank_number);
sys/dev/qat/qat_common/adf_gen4_hw_data.c
154
reset_ring_pair(struct resource *csr, u32 bank_number)
sys/dev/qat/qat_common/adf_gen4_hw_data.c
166
ADF_CSR_WR(csr,
sys/dev/qat/qat_common/adf_gen4_hw_data.c
172
val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number));
sys/dev/qat/qat_common/adf_gen4_hw_data.c
182
ADF_CSR_WR(csr,
sys/dev/qat/qat_common/adf_gen4_hw_data.c
193
struct resource *csr;
sys/dev/qat/qat_common/adf_gen4_hw_data.c
199
csr = (&GET_BARS(accel_dev)[etr_bar_id])->virt_addr;
sys/dev/qat/qat_common/adf_gen4_hw_data.c
201
ret = reset_ring_pair(csr, bank_number);
sys/dev/qat/qat_common/adf_hw_arbiter.c
162
struct resource *csr = csr_addr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
169
arbenable = csr_ops->read_csr_ring_srv_arb_en(csr, bank_nr);
sys/dev/qat/qat_common/adf_hw_arbiter.c
171
csr_ops->write_csr_ring_srv_arb_en(csr, bank_nr, arbenable);
sys/dev/qat/qat_common/adf_hw_arbiter.c
181
struct resource *csr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
187
csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
193
WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, i, 0);
sys/dev/qat/qat_common/adf_hw_arbiter.c
198
WRITE_CSR_ARB_WRK_2_SER_MAP(csr,
sys/dev/qat/qat_common/adf_hw_arbiter.c
207
csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
sys/dev/qat/qat_common/adf_hw_arbiter.c
214
struct resource *csr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
220
csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
225
csr_ops->write_csr_ring_srv_arb_en(csr, i, 0);
sys/dev/qat/qat_common/adf_hw_arbiter.c
53
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
63
WRITE_CSR_ARB_SARCONFIG(csr, info.arbiter_offset, arb, arb_cfg);
sys/dev/qat/qat_common/adf_hw_arbiter.c
73
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_common/adf_hw_arbiter.c
88
WRITE_CSR_ARB_WRK_2_SER_MAP(csr,
sys/dev/qat/qat_common/adf_init.c
220
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_common/adf_init.c
255
ADF_CSR_WR(csr, ADF_SSMWDT(i), timer_val);
sys/dev/qat/qat_common/adf_init.c
257
ADF_CSR_WR(csr, ADF_SSMWDTPKE(i), timer_val_pke);
sys/dev/qat/qat_common/qat_hal.c
112
unsigned int csr,
sys/dev/qat/qat_common/qat_hal.c
118
*value = GET_AE_CSR(handle, ae, csr);
sys/dev/qat/qat_common/qat_hal.c
130
unsigned int csr,
sys/dev/qat/qat_common/qat_hal.c
136
SET_AE_CSR(handle, ae, csr, value);
sys/dev/qat/qat_common/qat_hal.c
166
unsigned int csr = (1 << ACS_ABO_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
174
qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr);
sys/dev/qat/qat_common/qat_hal.c
184
if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS)))
sys/dev/qat/qat_common/qat_hal.c
208
unsigned int csr, new_csr;
sys/dev/qat/qat_common/qat_hal.c
216
qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);
sys/dev/qat/qat_common/qat_hal.c
217
csr = IGNORE_W1C_MASK & csr;
sys/dev/qat/qat_common/qat_hal.c
218
new_csr = (mode == 4) ? SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
219
CLR_BIT(csr, CE_INUSE_CONTEXTS_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
229
unsigned int csr, new_csr;
sys/dev/qat/qat_common/qat_hal.c
236
qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);
sys/dev/qat/qat_common/qat_hal.c
237
csr &= IGNORE_W1C_MASK;
sys/dev/qat/qat_common/qat_hal.c
239
new_csr = (mode) ? SET_BIT(csr, CE_NN_MODE_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
240
CLR_BIT(csr, CE_NN_MODE_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
242
if (new_csr != csr)
sys/dev/qat/qat_common/qat_hal.c
254
unsigned int csr, new_csr;
sys/dev/qat/qat_common/qat_hal.c
256
qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);
sys/dev/qat/qat_common/qat_hal.c
257
csr &= IGNORE_W1C_MASK;
sys/dev/qat/qat_common/qat_hal.c
260
new_csr = (mode) ? SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
261
CLR_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
264
new_csr = (mode) ? SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
265
CLR_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
268
new_csr = (mode) ? SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
269
CLR_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
272
new_csr = (mode) ? SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
273
CLR_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
280
if (new_csr != csr)
sys/dev/qat/qat_common/qat_hal.c
290
unsigned int csr, new_csr;
sys/dev/qat/qat_common/qat_hal.c
292
qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr);
sys/dev/qat/qat_common/qat_hal.c
293
csr &= IGNORE_W1C_MASK;
sys/dev/qat/qat_common/qat_hal.c
294
new_csr = (mode) ? SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
295
CLR_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
296
if (new_csr != csr)
sys/dev/qat/qat_common/qat_hal.c
305
unsigned int csr, new_csr;
sys/dev/qat/qat_common/qat_hal.c
307
qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr);
sys/dev/qat/qat_common/qat_hal.c
308
new_csr = (mode) ? SET_BIT(csr, MMC_SHARE_CS_BITPOS) :
sys/dev/qat/qat_common/qat_hal.c
309
CLR_BIT(csr, MMC_SHARE_CS_BITPOS);
sys/dev/qat/qat_common/qat_hal.c
310
if (new_csr != csr)
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
178
adf_enable_error_interrupts(struct resource *csr)
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
180
ADF_CSR_WR(csr, ADF_ERRMSK0, ADF_200XX_ERRMSK0_CERR); /* ME0-ME3 */
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
181
ADF_CSR_WR(csr, ADF_ERRMSK1, ADF_200XX_ERRMSK1_CERR); /* ME4-ME5 */
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
182
ADF_CSR_WR(csr, ADF_ERRMSK5, ADF_200XX_ERRMSK5_CERR); /* SSM2 */
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
185
adf_csr_fetch_and_and(csr, ADF_ERRMSK3, ADF_200XX_VF2PF1_16);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
188
ADF_CSR_WR(csr, ADF_200XX_RICPPINTCTL, ADF_200XX_RICPP_EN);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
191
ADF_CSR_WR(csr, ADF_200XX_TICPPINTCTL, ADF_200XX_TICPP_EN);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
194
ADF_CSR_WR(csr, ADF_200XX_CPP_CFC_ERR_CTRL, ADF_200XX_CPP_CFC_UE);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
201
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
204
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
208
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
212
ADF_CSR_WR(csr, ADF_ERRMSK3, ADF_200XX_ERRMSK3_UERR);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
214
ADF_CSR_WR(csr, ADF_ERRMSK5, ADF_200XX_ERRMSK5_UERR);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
221
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
223
u32 errsou0 = ADF_CSR_RD(csr, ADF_ERRSOU0) & ADF_200XX_ERRMSK0_UERR;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
224
u32 errsou1 = ADF_CSR_RD(csr, ADF_ERRSOU1) & ADF_200XX_ERRMSK1_UERR;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
225
u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3) & ADF_200XX_ERRMSK3_UERR;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
226
u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5) & ADF_200XX_ERRMSK5_UERR;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
232
adf_enable_mmp_error_correction(struct resource *csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
243
adf_csr_fetch_and_and(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
254
adf_csr_fetch_and_or(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
261
adf_csr_fetch_and_or(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
271
adf_csr_fetch_and_and(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
278
adf_csr_fetch_and_and(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
285
adf_csr_fetch_and_or(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
290
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
301
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
310
val = ADF_CSR_RD(csr, ADF_200XX_AE_CTX_ENABLES(i));
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
312
ADF_CSR_WR(csr, ADF_200XX_AE_CTX_ENABLES(i), val);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
313
val = ADF_CSR_RD(csr, ADF_200XX_AE_MISC_CONTROL(i));
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
315
ADF_CSR_WR(csr, ADF_200XX_AE_MISC_CONTROL(i), val);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
323
val = ADF_CSR_RD(csr, ADF_200XX_UERRSSMSH(i));
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
325
ADF_CSR_WR(csr, ADF_200XX_UERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
326
val = ADF_CSR_RD(csr, ADF_200XX_CERRSSMSH(i));
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
328
ADF_CSR_WR(csr, ADF_200XX_CERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
329
val = ADF_CSR_RD(csr, ADF_PPERR(i));
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
331
ADF_CSR_WR(csr, ADF_PPERR(i), val);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
334
adf_enable_error_interrupts(csr);
sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c
335
adf_enable_mmp_error_correction(csr, hw_device);
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
202
struct resource *csr;
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
205
csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
207
ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
919
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
922
ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY);
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
945
u32 csr;
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
951
csr = ADF_CSR_RD(addr, ADF_4XXX_ERRMSK2);
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
952
csr |= ADF_4XXX_PM_SOU;
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
953
ADF_CSR_WR(addr, ADF_4XXX_ERRMSK2, csr);
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
181
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
190
val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
192
ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val);
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
193
val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i));
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
195
ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val);
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
203
val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
205
ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
206
val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c
208
ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
1959
struct resource *csr =
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
1997
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
209
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
228
ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTL_OFFSET(accel), ssm_wdt_low);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
229
ADF_CSR_WR(csr, ADF_C4XXX_SSMWDTH_OFFSET(accel), ssm_wdt_high);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
230
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
233
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
252
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
259
u32 errsou10 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU10);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
269
fw_irq_source = ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
271
ADF_CSR_RD(csr, ADF_C4XXX_IAINTSTATSSM(accel_num));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
284
adf_csr_fetch_and_and(csr, slice_hang_offset, ~0);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
289
csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
299
csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
306
adf_csr_fetch_and_and(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
317
struct resource *csr =
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
320
u32 errsou11 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU11);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
321
u32 doorbell_int = ADF_CSR_RD(csr, ADF_C4XXX_ETH_DOORBELL_INT);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
337
eth_doorbell_reg[i] = ADF_CSR_RD(csr, data_reg);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
351
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
424
struct resource *csr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
429
csr = (&GET_BARS(accel_dev)[ADF_C4XXX_PMISC_BAR])->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
435
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
444
struct resource *csr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
449
csr = (&GET_BARS(accel_dev)[ADF_C4XXX_PMISC_BAR])->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
454
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
470
struct resource *csr, *aram_csr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
475
csr = (&GET_BARS(accel_dev)[ADF_C4XXX_PMISC_BAR])->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
484
ADF_CSR_WR(csr, ADF_C4XXX_GET_INTMASKSSM_OFFSET(accel), 0);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
487
ADF_CSR_WR(csr, ADF_C4XXX_GET_SPPPARERRMSK_OFFSET(accel), 0);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
490
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
496
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK4, ADF_C4XXX_VF2PF0_31);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
497
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK5, ADF_C4XXX_VF2PF32_63);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
498
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK6, ADF_C4XXX_VF2PF64_95);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
499
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK7, ADF_C4XXX_VF2PF96_127);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
502
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK8, ADF_C4XXX_ERRMSK8_COERR);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
503
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
508
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK9, ADF_C4XXX_ERRMSK9_IRQ_MASK);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
511
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
516
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
521
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
526
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
529
ADF_CSR_WR(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
534
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK10, ADF_C4XXX_ERRMSK10_SSM_ERR);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
537
ADF_CSR_WR(csr, ADF_C4XXX_ERRMSK11, ADF_C4XXX_ERRMSK11_ERR);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
540
ADF_CSR_WR(csr, ADF_C4XXX_RICPPINTCTL, ADF_C4XXX_RICPP_EN);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
543
ADF_CSR_WR(csr, ADF_C4XXX_TICPPINTCTL, ADF_C4XXX_TICPP_EN);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
546
ADF_CSR_WR(csr, ADF_C4XXX_CPP_CFC_ERR_CTRL, ADF_C4XXX_CPP_CFC_UE);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
559
adf_enable_mmp_error_correction(struct resource *csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
587
adf_csr_fetch_and_and(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
593
csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
598
csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
605
adf_csr_fetch_and_or(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
638
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
648
val = ADF_CSR_RD(csr, ADF_C4XXX_AE_CTX_ENABLES(i));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
650
ADF_CSR_WR(csr, ADF_C4XXX_AE_CTX_ENABLES(i), val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
651
val = ADF_CSR_RD(csr, ADF_C4XXX_AE_MISC_CONTROL(i));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
653
ADF_CSR_WR(csr, ADF_C4XXX_AE_MISC_CONTROL(i), val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
661
val = ADF_CSR_RD(csr, ADF_C4XXX_UERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
663
ADF_CSR_WR(csr, ADF_C4XXX_UERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
664
val = ADF_CSR_RD(csr, ADF_C4XXX_CERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
666
ADF_CSR_WR(csr, ADF_C4XXX_CERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c
670
adf_enable_mmp_error_correction(csr, hw_device);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.h
393
#define ADF_C4XXX_CLEAR_CSR_BIT(csr, bit_num) ((csr) &= ~(BIT(bit_num)))
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
102
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
111
WRITE_CSR_WQM(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
125
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
136
WRITE_CSR_WQM(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
170
struct resource *csr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
176
csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
180
WRITE_CSR_WQM(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
192
WRITE_CSR_WQM(csr, ADF_C4XXX_WRKTHD2PARTMAP, i, 0);
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
64
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
73
WRITE_CSR_WQM(csr,
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
82
struct resource *csr = accel_dev->transport->banks[0].csr_addr;
sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_res_part.c
93
WRITE_CSR_WQM(csr,
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
185
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
194
val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
196
ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val);
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
197
val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i));
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
199
ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val);
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
207
val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
209
ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
210
val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i));
sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c
212
ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
198
struct resource *csr = misc_bar->virt_addr;
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
207
val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
209
ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
210
val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
212
ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val);
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
220
val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
222
ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
223
val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));
sys/dev/qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c
225
ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val);
sys/dev/usb/controller/musb_otg.c
1046
csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
sys/dev/usb/controller/musb_otg.c
1047
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1073
uint8_t csr, csrh;
sys/dev/usb/controller/musb_otg.c
1091
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1092
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1094
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
sys/dev/usb/controller/musb_otg.c
1101
if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
sys/dev/usb/controller/musb_otg.c
1102
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
1106
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1107
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
1111
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1115
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
sys/dev/usb/controller/musb_otg.c
1116
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1132
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
sys/dev/usb/controller/musb_otg.c
1136
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
sys/dev/usb/controller/musb_otg.c
1243
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
1258
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1260
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1262
if (csr & MUSB2_MASK_CSR0L_DATAEND) {
sys/dev/usb/controller/musb_otg.c
1279
uint8_t csr, csrh;
sys/dev/usb/controller/musb_otg.c
1322
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1324
DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1326
if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
sys/dev/usb/controller/musb_otg.c
1333
if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
sys/dev/usb/controller/musb_otg.c
1334
csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
sys/dev/usb/controller/musb_otg.c
1336
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1338
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
sys/dev/usb/controller/musb_otg.c
1339
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1344
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
sys/dev/usb/controller/musb_otg.c
1349
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1365
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
1383
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1384
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1387
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
sys/dev/usb/controller/musb_otg.c
1391
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
sys/dev/usb/controller/musb_otg.c
1396
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1433
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
1455
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
1457
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1460
if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
sys/dev/usb/controller/musb_otg.c
1467
if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
sys/dev/usb/controller/musb_otg.c
1581
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
1602
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1604
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1606
if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
sys/dev/usb/controller/musb_otg.c
1611
if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
sys/dev/usb/controller/musb_otg.c
1708
uint8_t csr, csrh;
sys/dev/usb/controller/musb_otg.c
1732
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
1733
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1780
if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
sys/dev/usb/controller/musb_otg.c
1782
if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
sys/dev/usb/controller/musb_otg.c
1783
csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
sys/dev/usb/controller/musb_otg.c
1784
MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1786
csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
sys/dev/usb/controller/musb_otg.c
1787
MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1793
if (csr & MUSB2_MASK_CSRL_RXERROR) {
sys/dev/usb/controller/musb_otg.c
1798
if (csr & MUSB2_MASK_CSRL_RXSTALL) {
sys/dev/usb/controller/musb_otg.c
1808
if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
sys/dev/usb/controller/musb_otg.c
1930
uint8_t csr, csrh;
sys/dev/usb/controller/musb_otg.c
1948
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1949
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
1951
if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
sys/dev/usb/controller/musb_otg.c
1960
if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
sys/dev/usb/controller/musb_otg.c
1964
if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
1965
csr |= MUSB2_MASK_CSRL_TXFFLUSH;
sys/dev/usb/controller/musb_otg.c
1966
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1967
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1968
if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
1969
csr |= MUSB2_MASK_CSRL_TXFFLUSH;
sys/dev/usb/controller/musb_otg.c
1970
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1971
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
1975
csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
sys/dev/usb/controller/musb_otg.c
1976
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
1989
if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
sys/dev/usb/controller/musb_otg.c
1993
if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
sys/dev/usb/controller/musb_otg.c
2866
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
2914
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
2915
if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
2918
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
2919
if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
2922
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
2929
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
2944
if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
sys/dev/usb/controller/musb_otg.c
2946
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
2973
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
2974
if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
sys/dev/usb/controller/musb_otg.c
2977
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
2978
if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
sys/dev/usb/controller/musb_otg.c
2981
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
2988
csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
sys/dev/usb/controller/musb_otg.c
3003
if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
sys/dev/usb/controller/musb_otg.c
403
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
421
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
423
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
429
if (csr & MUSB2_MASK_CSR0L_DATAEND) {
sys/dev/usb/controller/musb_otg.c
437
if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
sys/dev/usb/controller/musb_otg.c
441
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
445
if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
sys/dev/usb/controller/musb_otg.c
450
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
458
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
sys/dev/usb/controller/musb_otg.c
529
uint8_t csr, csrh;
sys/dev/usb/controller/musb_otg.c
547
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
548
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
551
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
sys/dev/usb/controller/musb_otg.c
555
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
sys/dev/usb/controller/musb_otg.c
560
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
564
if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
sys/dev/usb/controller/musb_otg.c
567
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
571
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
572
if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
sys/dev/usb/controller/musb_otg.c
576
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
580
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
sys/dev/usb/controller/musb_otg.c
581
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
592
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
sys/dev/usb/controller/musb_otg.c
638
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
653
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
655
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
659
if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
sys/dev/usb/controller/musb_otg.c
675
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
sys/dev/usb/controller/musb_otg.c
779
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
793
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
795
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
797
if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
sys/dev/usb/controller/musb_otg.c
806
if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
sys/dev/usb/controller/musb_otg.c
895
uint8_t csr;
sys/dev/usb/controller/musb_otg.c
914
csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
sys/dev/usb/controller/musb_otg.c
916
DPRINTFN(4, "csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
936
if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
sys/dev/usb/controller/musb_otg.c
937
csr &= ~MUSB2_MASK_CSR0L_REQPKT;
sys/dev/usb/controller/musb_otg.c
938
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
940
csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
sys/dev/usb/controller/musb_otg.c
941
MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
sys/dev/usb/controller/musb_otg.c
947
if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
sys/dev/usb/controller/musb_otg.c
952
DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
sys/dev/usb/controller/musb_otg.c
961
if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
sys/dev/wpi/if_wpi_debug.h
101
static const char *wpi_get_csr_string(size_t csr)
sys/dev/wpi/if_wpi_debug.h
103
switch (csr) {
sys/dev/wpi/if_wpi_debug.h
120
KASSERT(0, ("Unknown CSR: %d\n", csr));
sys/i386/i386/npx.c
89
#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
sys/net80211/ieee80211_ioctl.c
2539
struct ieee80211_chanswitch_req csr;
sys/net80211/ieee80211_ioctl.c
2543
if (ireq->i_len != sizeof(csr))
sys/net80211/ieee80211_ioctl.c
2545
error = copyin(ireq->i_data, &csr, sizeof(csr));
sys/net80211/ieee80211_ioctl.c
2553
csr.csa_chan.ic_freq, csr.csa_chan.ic_flags);
sys/net80211/ieee80211_ioctl.c
2558
ieee80211_csa_startswitch(ic, c, csr.csa_mode, csr.csa_count);
sys/net80211/ieee80211_ioctl.c
2559
else if (csr.csa_count == 0)
sys/powerpc/booke/machdep_e500.c
102
if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
sys/powerpc/booke/machdep_e500.c
107
csr = mfspr(SPR_L2CSR0);
sys/powerpc/booke/machdep_e500.c
108
if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
sys/powerpc/booke/machdep_e500.c
110
(csr & L2CSR0_L2E) ? "en" : "dis");
sys/powerpc/booke/machdep_e500.c
117
uint32_t csr;
sys/powerpc/booke/machdep_e500.c
120
csr = mfspr(SPR_BUCSR);
sys/powerpc/booke/machdep_e500.c
121
if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
sys/powerpc/booke/machdep_e500.c
123
(csr & BUCSR_BPEN) ? "en" : "dis");
sys/powerpc/booke/machdep_e500.c
56
uint32_t csr;
sys/powerpc/booke/machdep_e500.c
59
csr = mfspr(SPR_L1CSR0);
sys/powerpc/booke/machdep_e500.c
60
if ((csr & L1CSR0_DCE) == 0) {
sys/powerpc/booke/machdep_e500.c
65
csr = mfspr(SPR_L1CSR0);
sys/powerpc/booke/machdep_e500.c
66
if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
sys/powerpc/booke/machdep_e500.c
68
(csr & L1CSR0_DCE) ? "en" : "dis");
sys/powerpc/booke/machdep_e500.c
71
csr = mfspr(SPR_L1CSR1);
sys/powerpc/booke/machdep_e500.c
72
if ((csr & L1CSR1_ICE) == 0) {
sys/powerpc/booke/machdep_e500.c
77
csr = mfspr(SPR_L1CSR1);
sys/powerpc/booke/machdep_e500.c
78
if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
sys/powerpc/booke/machdep_e500.c
80
(csr & L1CSR1_ICE) ? "en" : "dis");
sys/powerpc/booke/machdep_e500.c
86
uint32_t csr;
sys/powerpc/booke/machdep_e500.c
91
csr = mfspr(SPR_L2CSR0);
sys/powerpc/booke/mp_cpudep.c
53
uint32_t msr, csr;
sys/powerpc/booke/mp_cpudep.c
57
csr = mfspr(SPR_L1CSR0);
sys/powerpc/booke/mp_cpudep.c
58
if ((csr & L1CSR0_DCE) == 0) {
sys/powerpc/booke/mp_cpudep.c
63
csr = mfspr(SPR_L1CSR1);
sys/powerpc/booke/mp_cpudep.c
64
if ((csr & L1CSR1_ICE) == 0) {
sys/powerpc/mpc85xx/mpc85xx.c
294
uint32_t csr, size, ver;
sys/powerpc/mpc85xx/mpc85xx.c
300
csr = ccsr_read4(OCP85XX_CPC_CSR0);
sys/powerpc/mpc85xx/mpc85xx.c
301
if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
sys/powerpc/mpc85xx/mpc85xx.c
306
csr = ccsr_read4(OCP85XX_CPC_CSR0);
sys/powerpc/mpc85xx/mpc85xx.c
308
(csr & OCP85XX_CPC_CSR0_CE) == 0) {
sys/powerpc/mpc85xx/mpc85xx.c
311
size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
sys/riscv/include/riscvreg.h
229
#define csr_swap(csr, val) \
sys/riscv/include/riscvreg.h
232
__asm __volatile("csrrwi %0, " #csr ", %1" \
sys/riscv/include/riscvreg.h
235
__asm __volatile("csrrw %0, " #csr ", %1" \
sys/riscv/include/riscvreg.h
240
#define csr_write(csr, val) \
sys/riscv/include/riscvreg.h
242
__asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
sys/riscv/include/riscvreg.h
244
__asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
sys/riscv/include/riscvreg.h
247
#define csr_set(csr, val) \
sys/riscv/include/riscvreg.h
249
__asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
sys/riscv/include/riscvreg.h
251
__asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
sys/riscv/include/riscvreg.h
254
#define csr_clear(csr, val) \
sys/riscv/include/riscvreg.h
256
__asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
sys/riscv/include/riscvreg.h
258
__asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
sys/riscv/include/riscvreg.h
261
#define csr_read(csr) \
sys/riscv/include/riscvreg.h
263
__asm __volatile("csrr %0, " #csr : "=r" (val)); \
sys/riscv/include/riscvreg.h
268
#define csr_read64(csr) \
sys/riscv/include/riscvreg.h
272
"csrr t0, " #csr "h\n" \
sys/riscv/include/riscvreg.h
273
"csrr %0, " #csr "\n" \
sys/riscv/include/riscvreg.h
274
"csrr %1, " #csr "h\n" \
sys/riscv/include/riscvreg.h
283
#define csr_read64(csr) ((uint64_t)csr_read(csr))