bus_read_2
data = le16toh(bus_read_2(sc->base.base.res, offset));
return (bus_read_2(sc->sc_res[MEMRES], offs));
return (bus_read_2(sc->mem_res, off));
#define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg);
#define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg)
bus_read_2(sc->mem_res, slot->bd_offset + 14)
return (bus_read_2(sc->sc_mem_res, off));
val = bus_read_2(sc->apb_mem_res, base + reg);
bus_read_2((sc)->mem[0], (reg))
bus_read_2((_sc)->age_res[0], (reg))
bus_read_2((res), (offset))
bus_read_2((_sc)->alc_res[0], (reg))
bus_read_2((_sc)->ale_res[0], (reg))
(bus_read_2(amdpm->res, register))
bus_read_2((res), (offset))
bus_read_2((_pdata)->xpcs_res, (_off))
bus_read_2((_pdata)->sir0_res, _reg)
bus_read_2((_pdata)->sir1_res, _reg)
bus_read_2((_pdata)->rxtx_res, _reg)
bus_read_2((r)->res, (o)) : \
return (bus_read_2(r, res_offset));
return (bus_read_2(r, r_offset));
(bus_read_2((mac)->mac_sc->sc_mem_res, (o)))
romsig = bus_read_2(res,
pcidata = imagebase + bus_read_2(res,
imagesize = bus_read_2(res,
bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg))
return (bus_read_2(sc->mem_res, off));
#define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg)
#define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
bus_read_2((sc)->tco_res, (off))
bus_read_2((ida)->regs, port)
#define RD2(sc, off) (bus_read_2((sc)->mem_res, (off)))
temp = bus_read_2(sc->tbar, regoff);
val = bus_read_2(sc->tbar, PCHTHERM_REG_TSPM);
val = bus_read_2(sc->tbar, PCHTHERM_REG_TL2);
val = bus_read_2(sc->tbar, PCHTHERM_REG_PHLC);
val |= bus_read_2(sc->tbar, PCHTHERM_REG_PHL);
bus_read_2(sc->tbar, PCHTHERM_REG_TAHV) != 0) {
bus_read_2(sc->tbar, PCHTHERM_REG_TALV) != 0) {
#define ips_read_2(sc,offset) bus_read_2(sc->iores, offset)
#define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off))
bus_read_2((sc)->regs, reg)
#define MLX_V4_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V4_STATUS)
#define MLX_V5_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V5_STATUS)
#define MLX_V3_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V3_STATUS)
bus_read_2((sc)->msk_res[0], (reg))
bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
bus_read_2((res), (offset))
return (bus_read_2(sc->dbi_res, reg));
data = bus_read_2(res, reg);
data = le16toh(bus_read_2(sc->res, offset));
pbi->pbi_value = bus_read_2(res, offset);
pci_read_config(dev, ofs, 2) : bus_read_2(r->r_d.res, ofs);
return bus_read_2(sc->mem_res, off);
return (bus_read_2(sc->mem_res[slot->num], off));
return bus_read_2(sc->mem_res[slot->num], off);
hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2);
return (bus_read_2(sc->mem_res, off));
#define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)
bus_read_2((res), (offset))
#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
bus_read_2((sc)->sk_res[0], (reg))
KASSERT((bus_read_2(sc->smc_reg, BSR) &
while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
return (bus_read_2(sc->smc_reg, offset));
val = bus_read_2(reg, BSR);
val = bus_read_2(reg, BSR);
val = bus_read_2(reg, BAR);
val = bus_read_2(reg, REV);
bus_read_2((sc)->ste_res, reg)
bus_read_2((_sc)->sc_res[0], (reg))
#define INW_OFF(o) bus_read_2(np->io_res, (o))
#define INW_OFF(o) bus_read_2(np->mmio_res, (o))
bus_read_2(sc->vge_res, reg)
bus_read_2((sc)->res[0], (o))
le16toh(bus_read_2((sc)->vtpci_res, (o)))
bus_read_2((sc)->vtpci_res, (o))
bus_read_2(&sc->vtpci_common_res_map.vtrm_map, off));
return (bus_read_2(&sc->vtpci_device_res_map.vtrm_map, off));
return (bus_read_2(sc->vmd_regs_res[0], offset));
#define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg)
bus_read_2((_sc)->vte_res, (reg))
return (bus_read_2(sc->sc_mem, CPLD_MEM_DATA));
return (bus_read_2(sc->sc_mem, sc->sc_offset + offset));
data = le16toh(bus_read_2(sc->cfg_mem_res, offset));
int32_t bus_read_2(int rid, long ofs);
{ "read_2", bus_read_2, METH_VARARGS, "Read a 2-byte data item." },