sys/arm/freescale/imx/imx6_audmux.c

105

WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);

sys/arm/freescale/imx/imx6_audmux.c

109

WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);

sys/arm/freescale/imx/imx6_sdma.c

115

WRITE4(sc, SDMAARM_HSTART, (1 << i));

sys/arm/freescale/imx/imx6_sdma.c

140

WRITE4(sc, SDMAARM_HSTART, (1 << chn));

sys/arm/freescale/imx/imx6_sdma.c

152

WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));

sys/arm/freescale/imx/imx6_sdma.c

219

WRITE4(sc, SDMAARM_EVTOVR, reg);

sys/arm/freescale/imx/imx6_sdma.c

227

WRITE4(sc, SDMAARM_HOSTOVR, reg);

sys/arm/freescale/imx/imx6_sdma.c

235

WRITE4(sc, SDMAARM_DSPOVR, reg);

sys/arm/freescale/imx/imx6_sdma.c

263

WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);

sys/arm/freescale/imx/imx6_sdma.c

264

WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn));

sys/arm/freescale/imx/imx6_sdma.c

327

WRITE4(sc, SDMAARM_HSTART, 1);

sys/arm/freescale/imx/imx6_sdma.c

344

WRITE4(sc, SDMAARM_INTR, ret);

sys/arm/freescale/imx/imx6_sdma.c

392

WRITE4(sc, SDMAARM_MC0PTR, 0);

sys/arm/freescale/imx/imx6_sdma.c

406

WRITE4(sc, SDMAARM_CHNENBL(i), 0);

sys/arm/freescale/imx/imx6_sdma.c

410

WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0);

sys/arm/freescale/imx/imx6_sdma.c

421

WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);

sys/arm/freescale/imx/imx6_sdma.c

426

WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050);

sys/arm/freescale/imx/imx6_sdma.c

428

WRITE4(sc, SDMAARM_CONFIG, 0);

sys/arm/freescale/imx/imx6_sdma.c

429

WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys);

sys/arm/freescale/imx/imx6_sdma.c

430

WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM);

sys/arm/freescale/imx/imx6_sdma.c

431

WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);

sys/arm/freescale/imx/imx6_sdma.c

439

WRITE4(sc, SDMAARM_HSTART, 1);

sys/arm/freescale/imx/imx6_sdma.c

453

WRITE4(sc, SDMAARM_INTR, ret);

sys/arm/freescale/imx/imx6_sdma.c

460

WRITE4(sc, SDMAARM_ONCE_ENB, 0);

sys/arm/freescale/imx/imx6_sdma.c

97

WRITE4(sc, SDMAARM_INTR, pending);

sys/arm/freescale/imx/imx6_ssi.c

531

WRITE4(sc, SSI_SIER, reg);

sys/arm/freescale/imx/imx6_ssi.c

548

WRITE4(sc, SSI_SIER, reg);

sys/arm/freescale/imx/imx6_ssi.c

685

WRITE4(sc, SSI_STCCR, reg);

sys/arm/freescale/imx/imx6_ssi.c

690

WRITE4(sc, SSI_SFCSR, reg);

sys/arm/freescale/imx/imx6_ssi.c

703

WRITE4(sc, SSI_STCR, reg);

sys/arm/freescale/imx/imx6_ssi.c

710

WRITE4(sc, SSI_SCR, reg);

sys/arm/freescale/imx/imx_gpio.c

311

WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq));

sys/arm/freescale/imx/imx_gpio.c

383

WRITE4(sc, reg, wrk);

sys/arm/freescale/imx/imx_gpio.c

385

WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));

sys/arm/freescale/imx/imx_gpio.c

437

WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));

sys/arm/freescale/imx/imx_gpio.c

451

WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));

sys/arm/freescale/imx/imx_gpio.c

708

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

731

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

76

WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))

sys/arm/freescale/imx/imx_gpio.c

772

WRITE4(sc, IMX_GPIO_DR_REG,

sys/arm/freescale/imx/imx_gpio.c

774

WRITE4(sc, IMX_GPIO_OE_REG,

sys/arm/freescale/imx/imx_gpio.c

78

WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))

sys/arm/freescale/imx/imx_gpio.c

836

WRITE4(sc, IMX_GPIO_IMR_REG, 0);

sys/arm/freescale/imx/imx_gpt.c

191

WRITE4(sc, IMX_GPT_CR, 0);

sys/arm/freescale/imx/imx_gpt.c

192

WRITE4(sc, IMX_GPT_IR, 0);

sys/arm/freescale/imx/imx_gpt.c

202

WRITE4(sc, IMX_GPT_CR, ctlreg);

sys/arm/freescale/imx/imx_gpt.c

212

WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);

sys/arm/freescale/imx/imx_gpt.c

225

WRITE4(sc, IMX_GPT_PR, prescale);

sys/arm/freescale/imx/imx_gpt.c

228

WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);

sys/arm/freescale/imx/imx_gpt.c

231

WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);

sys/arm/freescale/imx/imx_gpt.c

255

WRITE4(sc, IMX_GPT_OCR3, 0);

sys/arm/freescale/imx/imx_gpt.c

295

WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);

sys/arm/freescale/imx/imx_gpt.c

298

WRITE4(sc, IMX_GPT_IR, sc->ir_reg);

sys/arm/freescale/imx/imx_gpt.c

304

WRITE4(sc, IMX_GPT_IR, sc->ir_reg);

sys/arm/freescale/imx/imx_gpt.c

310

WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);

sys/arm/freescale/imx/imx_gpt.c

328

WRITE4(sc, IMX_GPT_IR, sc->ir_reg);

sys/arm/freescale/imx/imx_gpt.c

329

WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3);

sys/arm/freescale/imx/imx_gpt.c

351

WRITE4(sc, IMX_GPT_SR, status);

sys/arm/freescale/imx/imx_gpt.c

365

WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) +

sys/arm/freescale/imx/imx_gpt.c

55

WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))

sys/arm/freescale/imx/imx_gpt.c

57

WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))

sys/arm/freescale/vybrid/vf_adc.c

171

WRITE4(sc, ADC_HC0, reg);

sys/arm/freescale/vybrid/vf_adc.c

208

WRITE4(sc, ADC_CFG, reg);

sys/arm/freescale/vybrid/vf_adc.c

213

WRITE4(sc, ADC_GC, reg);

sys/arm/freescale/vybrid/vf_adc.c

218

WRITE4(sc, ADC_HC0, reg);

sys/arm/freescale/vybrid/vf_anadig.c

140

WRITE4(sc, pll_ctrl, reg);

sys/arm/freescale/vybrid/vf_anadig.c

148

WRITE4(sc, pll_ctrl, reg);

sys/arm/freescale/vybrid/vf_anadig.c

168

WRITE4(sc, ANADIG_PLL4_CTRL, reg);

sys/arm/freescale/vybrid/vf_anadig.c

169

WRITE4(sc, ANADIG_PLL4_NUM, mfn);

sys/arm/freescale/vybrid/vf_anadig.c

170

WRITE4(sc, ANADIG_PLL4_DENOM, mfd);

sys/arm/freescale/vybrid/vf_anadig.c

208

WRITE4(sc, ANADIG_REG_3P0, reg);

sys/arm/freescale/vybrid/vf_anadig.c

213

WRITE4(sc, USB_MISC(0), reg);

sys/arm/freescale/vybrid/vf_anadig.c

217

WRITE4(sc, USB_MISC(1), reg);

sys/arm/freescale/vybrid/vf_ccm.c

380

WRITE4(sc, clk->sel_reg, reg);

sys/arm/freescale/vybrid/vf_ccm.c

387

WRITE4(sc, clk->reg, reg);

sys/arm/freescale/vybrid/vf_ccm.c

461

WRITE4(sc, CCM_CCR, reg);

sys/arm/freescale/vybrid/vf_ccm.c

475

WRITE4(sc, CCM_CCGR(i), 0xffffffff);

sys/arm/freescale/vybrid/vf_dcu4.c

229

WRITE4(sc, DCU_INT_STATUS, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

294

WRITE4(sc, DCU_DISP_SIZE, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

299

WRITE4(sc, DCU_HSYN_PARA, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

304

WRITE4(sc, DCU_VSYN_PARA, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

306

WRITE4(sc, DCU_BGND, 0);

sys/arm/freescale/vybrid/vf_dcu4.c

307

WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);

sys/arm/freescale/vybrid/vf_dcu4.c

310

WRITE4(sc, DCU_SYNPOL, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

316

WRITE4(sc, DCU_THRESHOLD, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

319

WRITE4(sc, DCU_INT_MASK, 0xffffffff);

sys/arm/freescale/vybrid/vf_dcu4.c

323

WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

324

WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

325

WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

326

WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

327

WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

328

WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

329

WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

330

WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

331

WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

336

WRITE4(sc, DCU_CTRLDESCLn_1(0), reg);

sys/arm/freescale/vybrid/vf_dcu4.c

337

WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

338

WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase);

sys/arm/freescale/vybrid/vf_dcu4.c

342

WRITE4(sc, DCU_CTRLDESCLn_4(0), reg);

sys/arm/freescale/vybrid/vf_dcu4.c

343

WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff);

sys/arm/freescale/vybrid/vf_dcu4.c

344

WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

345

WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

346

WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

347

WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0);

sys/arm/freescale/vybrid/vf_dcu4.c

354

WRITE4(sc, DCU_DCU_MODE, reg);

sys/arm/freescale/vybrid/vf_dcu4.c

355

WRITE4(sc, DCU_UPDATE_MODE, READREG);

sys/arm/freescale/vybrid/vf_edma.c

200

WRITE4(sc, DMA_ERQ, reg);

sys/arm/freescale/vybrid/vf_edma.c

247

WRITE4(sc, DMA_ERQ, reg);

sys/arm/freescale/vybrid/vf_edma.c

252

WRITE4(sc, DMA_EEI, reg);

sys/arm/freescale/vybrid/vf_gpio.c

283

WRITE4(sc, GPIO_PTOR(i), (1 << (i % 32)));

sys/arm/freescale/vybrid/vf_gpio.c

306

WRITE4(sc, GPIO_PCOR(pin->gp_pin),

sys/arm/freescale/vybrid/vf_gpio.c

351

WRITE4(sc, GPIO_PSOR(i), (1 << (i % 32)));

sys/arm/freescale/vybrid/vf_gpio.c

353

WRITE4(sc, GPIO_PCOR(i), (1 << (i % 32)));

sys/arm/freescale/vybrid/vf_iomuxc.c

159

WRITE4(sc, IOMUXC(pin), pin_cfg);

sys/arm/freescale/vybrid/vf_port.c

119

WRITE4(sc, PORT_PCR(i), reg);

sys/arm/freescale/vybrid/vf_port.c

176

WRITE4(sc, PORT_PCR(pnum), reg);

sys/arm/freescale/vybrid/vf_sai.c

358

WRITE4(sc, I2S_TCR2, reg);

sys/arm/freescale/vybrid/vf_sai.c

623

WRITE4(sc, I2S_TCSR, reg);

sys/arm/freescale/vybrid/vf_sai.c

627

WRITE4(sc, I2S_TCR3, reg);

sys/arm/freescale/vybrid/vf_sai.c

630

WRITE4(sc, I2S_TCR1, reg);

sys/arm/freescale/vybrid/vf_sai.c

636

WRITE4(sc, I2S_TCR2, reg);

sys/arm/freescale/vybrid/vf_sai.c

642

WRITE4(sc, I2S_TCR3, reg);

sys/arm/freescale/vybrid/vf_sai.c

651

WRITE4(sc, I2S_TCR4, reg);

sys/arm/freescale/vybrid/vf_sai.c

660

WRITE4(sc, I2S_TCR5, reg);

sys/arm/freescale/vybrid/vf_sai.c

666

WRITE4(sc, I2S_TCSR, reg);

sys/arm/freescale/vybrid/vf_spi.c

166

WRITE4(sc, SPI_MCR, reg);

sys/arm/freescale/vybrid/vf_spi.c

170

WRITE4(sc, SPI_RSER, reg);

sys/arm/freescale/vybrid/vf_spi.c

174

WRITE4(sc, SPI_MCR, reg);

sys/arm/freescale/vybrid/vf_spi.c

192

WRITE4(sc, SPI_CTAR0, reg);

sys/arm/freescale/vybrid/vf_spi.c

197

WRITE4(sc, SPI_CTAR0, reg);

sys/arm/freescale/vybrid/vf_spi.c

223

WRITE4(sc, SPI_PUSHR, wreg);

sys/arm/freescale/vybrid/vf_spi.c

234

WRITE4(sc, SPI_SR, reg);

sys/arm/freescale/vybrid/vf_src.c

93

WRITE4(src_sc, SRC_SCR, SW_RST);

sys/arm/freescale/vybrid/vf_tcon.c

78

WRITE4(tcon_sc, TCON0_CTRL1, TCON_BYPASS);

sys/arm/ti/clk/ti_clk_clkctrl.c

114

WRITE4(clk, sc->register_offset, val);

sys/arm/ti/clk/ti_clk_clkctrl.c

153

WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);

sys/arm/ti/clk/ti_clk_clkctrl.c

155

WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);

sys/arm/ti/clk/ti_clk_dpll.c

209

WRITE4(clk, sc->ti_clkmode_offset, DPLL_EN_MN_BYPASS_MODE);

sys/arm/ti/clk/ti_clk_dpll.c

233

WRITE4(clk, sc->ti_clksel_offset, val);

sys/arm/ti/clk/ti_clk_dpll.c

242

WRITE4(clk, sc->ti_clkmode_offset, DPLL_EN_LOCK_MODE);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

107

WRITE4(clk, sc->offset, val);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

126

WRITE4(clk, sc->offset, val);

sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c

95

WRITE4(clk, sc->offset + CFG0, cfg0);

sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c

104

WRITE4(clk, sc->offset + CFG0, cfg0);

sys/dev/agp/agp_amd.c

249

WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);

sys/dev/agp/agp_amd.c

284

WRITE4(AGP_AMD751_ATTBASE, 0);

sys/dev/agp/agp_amd.c

367

WRITE4(AGP_AMD751_TLBCTRL, 1);

sys/dev/agp/agp_ati.c

228

WRITE4(ATI_GART_FEATURE_ID, 0x00060000);

sys/dev/agp/agp_ati.c

233

WRITE4(ATI_GART_BASE, sc->ag_pdir);

sys/dev/agp/agp_ati.c

254

WRITE4(ATI_GART_BASE, 0);

sys/dev/agp/agp_ati.c

341

WRITE4(ATI_GART_CACHE_CNTRL, 1);

sys/dev/clk/allwinner/aw_clk_frac.c

116

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_frac.c

138

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_frac.c

267

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_frac.c

288

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_frac.c

292

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_m.c

106

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_m.c

127

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_m.c

213

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_mipi.c

106

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_mipi.c

175

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_mipi.c

188

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_mipi.c

192

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

111

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

132

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

205

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

212

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

220

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

226

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

233

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

293

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

301

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nm.c

107

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nm.c

128

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nm.c

246

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nmm.c

184

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_nmm.c

94

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_np.c

173

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_np.c

93

WRITE4(clk, sc->offset, val);

sys/dev/clk/allwinner/aw_clk_prediv_mux.c

100

WRITE4(clk, sc->offset, val);

sys/dev/clk/rockchip/rk_clk_armclk.c

111

WRITE4(clk, sc->muxdiv_offset, val);

sys/dev/clk/rockchip/rk_clk_armclk.c

196

WRITE4(clk, sc->muxdiv_offset, val);

sys/dev/clk/rockchip/rk_clk_composite.c

160

WRITE4(clk, sc->muxdiv_offset, val);

sys/dev/clk/rockchip/rk_clk_composite.c

285

WRITE4(clk, sc->muxdiv_offset, val);

sys/dev/clk/rockchip/rk_clk_pll.c

150

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

231

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

234

WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET |

sys/dev/clk/rockchip/rk_clk_pll.c

246

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

256

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

261

WRITE4(clk, sc->base_offset + 0x8, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

264

WRITE4(clk, sc->base_offset + 12,

sys/dev/clk/rockchip/rk_clk_pll.c

290

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

454

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

461

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

471

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

478

WRITE4(clk, sc->base_offset + 0x8, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

493

WRITE4(clk, sc->mode_reg, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

694

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

699

WRITE4(clk, sc->base_offset, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

707

WRITE4(clk, sc->base_offset + 0x4, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

713

WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK);

sys/dev/clk/rockchip/rk_clk_pll.c

718

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

731

WRITE4(clk, sc->base_offset + 0xC, reg);

sys/dev/clk/rockchip/rk_clk_pll.c

89

WRITE4(clk, sc->gate_offset, val);

sys/dev/clk/starfive/jh7110_clk.c

147

WRITE4(sc, sc_clk->offset, reg);

sys/dev/clk/starfive/jh7110_clk.c

175

WRITE4(sc, sc_clk->offset, reg);

sys/dev/clk/starfive/jh7110_clk.c

232

WRITE4(sc, sc_clk->offset, divisor);

sys/dev/clk/starfive/jh7110_clk.c

74

WRITE4(sc, offset, regvalue);

sys/dev/dwc/dwc1000_core.c

103

WRITE4(sc, GMII_ADDRESS, mii);

sys/dev/dwc/dwc1000_core.c

130

WRITE4(sc, GMII_DATA, val);

sys/dev/dwc/dwc1000_core.c

131

WRITE4(sc, GMII_ADDRESS, mii);

sys/dev/dwc/dwc1000_core.c

192

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

201

WRITE4(sc, FLOW_CONTROL, reg);

sys/dev/dwc/dwc1000_core.c

217

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

231

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

245

WRITE4(sc, MAC_CONFIGURATION, reg);

sys/dev/dwc/dwc1000_core.c

342

WRITE4(sc, MAC_ADDRESS_LOW(0), lo);

sys/dev/dwc/dwc1000_core.c

343

WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);

sys/dev/dwc/dwc1000_core.c

344

WRITE4(sc, MAC_FRAME_FILTER, ffval);

sys/dev/dwc/dwc1000_core.c

346

WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);

sys/dev/dwc/dwc1000_core.c

347

WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);

sys/dev/dwc/dwc1000_core.c

350

WRITE4(sc, HASH_TABLE_REG(i), ctx.hash[i]);

sys/dev/dwc/dwc1000_core.c

399

WRITE4(sc, MMC_CONTROL, reg);

sys/dev/dwc/dwc1000_core.c

446

WRITE4(sc, INTERRUPT_ENABLE, 0);

sys/dev/dwc/dwc1000_dma.c

498

WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);

sys/dev/dwc/dwc1000_dma.c

549

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

551

WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);

sys/dev/dwc/dwc1000_dma.c

556

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

572

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

577

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

582

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

593

WRITE4(sc, BUS_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

631

WRITE4(sc, BUS_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

642

WRITE4(sc, OPERATION_MODE, reg);

sys/dev/dwc/dwc1000_dma.c

719

WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);

sys/dev/dwc/dwc1000_dma.c

795

WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);

sys/dev/dwc/dwc1000_dma.c

880

WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);

sys/dev/flash/cqspi.c

159

WRITE4(sc, CQSPI_IRQSTAT, pending);

sys/dev/flash/cqspi.c

260

WRITE4(sc, CQSPI_FLASHCMDADDR, addr);

sys/dev/flash/cqspi.c

264

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

267

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

282

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

284

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

313

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

316

WRITE4(sc, CQSPI_FLASHCMD, reg);

sys/dev/flash/cqspi.c

429

WRITE4(sc, CQSPI_DMAPER, reg);

sys/dev/flash/cqspi.c

431

WRITE4(sc, CQSPI_INDWRWATER, 64);

sys/dev/flash/cqspi.c

432

WRITE4(sc, CQSPI_INDWR, INDRD_IND_OPS_DONE_STATUS);

sys/dev/flash/cqspi.c

433

WRITE4(sc, CQSPI_INDWR, 0);

sys/dev/flash/cqspi.c

435

WRITE4(sc, CQSPI_INDWRCNT, count);

sys/dev/flash/cqspi.c

436

WRITE4(sc, CQSPI_INDWRSTADDR, offset);

sys/dev/flash/cqspi.c

442

WRITE4(sc, CQSPI_DEVWR, reg);

sys/dev/flash/cqspi.c

447

WRITE4(sc, CQSPI_DEVRD, reg);

sys/dev/flash/cqspi.c

455

WRITE4(sc, CQSPI_INDWR, INDRD_START);

sys/dev/flash/cqspi.c

481

WRITE4(sc, CQSPI_DMAPER, reg);

sys/dev/flash/cqspi.c

483

WRITE4(sc, CQSPI_INDRDWATER, 64);

sys/dev/flash/cqspi.c

484

WRITE4(sc, CQSPI_INDRD, INDRD_IND_OPS_DONE_STATUS);

sys/dev/flash/cqspi.c

485

WRITE4(sc, CQSPI_INDRD, 0);

sys/dev/flash/cqspi.c

487

WRITE4(sc, CQSPI_INDRDCNT, count);

sys/dev/flash/cqspi.c

488

WRITE4(sc, CQSPI_INDRDSTADDR, offset);

sys/dev/flash/cqspi.c

496

WRITE4(sc, CQSPI_DEVRD, reg);

sys/dev/flash/cqspi.c

498

WRITE4(sc, CQSPI_MODEBIT, 0xff);

sys/dev/flash/cqspi.c

499

WRITE4(sc, CQSPI_IRQMASK, 0);

sys/dev/flash/cqspi.c

507

WRITE4(sc, CQSPI_INDRD, INDRD_START);

sys/dev/flash/cqspi.c

553

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/flash/cqspi.c

558

WRITE4(sc, CQSPI_DEVSZ, reg);

sys/dev/flash/cqspi.c

560

WRITE4(sc, CQSPI_SRAMPART, sc->fifo_depth/2);

sys/dev/flash/cqspi.c

569

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/flash/cqspi.c

575

WRITE4(sc, CQSPI_DELAY, reg);

sys/dev/flash/cqspi.c

580

WRITE4(sc, CQSPI_RDDATACAP, reg);

sys/dev/flash/cqspi.c

585

WRITE4(sc, CQSPI_CFG, reg);

sys/dev/gpio/dwgpio/dwgpio.c

312

WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);

sys/dev/gpio/dwgpio/dwgpio.c

343

WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg);

sys/dev/gpio/dwgpio/dwgpio.c

391

WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg);

sys/dev/mmc/host/dwmmc.c

1001

WRITE4(sc, SDMMC_BMOD, reg);

sys/dev/mmc/host/dwmmc.c

1004

WRITE4(sc, SDMMC_PLDMND, 1);

sys/dev/mmc/host/dwmmc.c

1022

WRITE4(sc, SDMMC_FIFOTH, reg);

sys/dev/mmc/host/dwmmc.c

1052

WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR);

sys/dev/mmc/host/dwmmc.c

1075

WRITE4(sc, SDMMC_DATA, *p++);

sys/dev/mmc/host/dwmmc.c

1079

WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR);

sys/dev/mmc/host/dwmmc.c

1145

WRITE4(sc, SDMMC_TMOUT, 0xffffffff);

sys/dev/mmc/host/dwmmc.c

1148

WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size);

sys/dev/mmc/host/dwmmc.c

1149

WRITE4(sc, SDMMC_BYTCNT, cmd->data->len);

sys/dev/mmc/host/dwmmc.c

1153

WRITE4(sc, SDMMC_BYTCNT, data->len);

sys/dev/mmc/host/dwmmc.c

1156

WRITE4(sc, SDMMC_BLKSIZ, blksz);

sys/dev/mmc/host/dwmmc.c

1169

WRITE4(sc, SDMMC_CMDARG, cmd->arg);

sys/dev/mmc/host/dwmmc.c

1171

WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START);

sys/dev/mmc/host/dwmmc.c

216

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc.c

420

WRITE4(sc, SDMMC_RINTSTS, reg);

sys/dev/mmc/host/dwmmc.c

435

WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |

sys/dev/mmc/host/dwmmc.c

437

WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);

sys/dev/mmc/host/dwmmc.c

716

WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);

sys/dev/mmc/host/dwmmc.c

719

WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);

sys/dev/mmc/host/dwmmc.c

720

WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |

sys/dev/mmc/host/dwmmc.c

726

WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);

sys/dev/mmc/host/dwmmc.c

727

WRITE4(sc, SDMMC_INTMASK, 0);

sys/dev/mmc/host/dwmmc.c

730

WRITE4(sc, SDMMC_TMOUT, 0xffffffff);

sys/dev/mmc/host/dwmmc.c

733

WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);

sys/dev/mmc/host/dwmmc.c

734

WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE |

sys/dev/mmc/host/dwmmc.c

741

WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);

sys/dev/mmc/host/dwmmc.c

813

WRITE4(sc, SDMMC_CLKENA, 0);

sys/dev/mmc/host/dwmmc.c

814

WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |

sys/dev/mmc/host/dwmmc.c

828

WRITE4(sc, SDMMC_CLKENA, 0);

sys/dev/mmc/host/dwmmc.c

829

WRITE4(sc, SDMMC_CLKSRC, 0);

sys/dev/mmc/host/dwmmc.c

833

WRITE4(sc, SDMMC_CLKDIV, div);

sys/dev/mmc/host/dwmmc.c

834

WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |

sys/dev/mmc/host/dwmmc.c

845

WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP));

sys/dev/mmc/host/dwmmc.c

846

WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA |

sys/dev/mmc/host/dwmmc.c

878

WRITE4(sc, SDMMC_PWREN, 0);

sys/dev/mmc/host/dwmmc.c

881

WRITE4(sc, SDMMC_PWREN, 1);

sys/dev/mmc/host/dwmmc.c

888

WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);

sys/dev/mmc/host/dwmmc.c

890

WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);

sys/dev/mmc/host/dwmmc.c

892

WRITE4(sc, SDMMC_CTYPE, 0);

sys/dev/mmc/host/dwmmc.c

896

WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);

sys/dev/mmc/host/dwmmc.c

907

WRITE4(sc, SDMMC_UHS_REG, reg);

sys/dev/mmc/host/dwmmc.c

947

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc.c

952

WRITE4(sc, SDMMC_BMOD, reg);

sys/dev/mmc/host/dwmmc.c

968

WRITE4(sc, SDMMC_INTMASK, reg);

sys/dev/mmc/host/dwmmc.c

991

WRITE4(sc, SDMMC_FIFOTH, reg);

sys/dev/mmc/host/dwmmc.c

996

WRITE4(sc, SDMMC_CTRL, reg);

sys/dev/mmc/host/dwmmc_samsung.c

101

WRITE4(sc, EMMCP_MPSBEGIN0, 0);

sys/dev/mmc/host/dwmmc_samsung.c

102

WRITE4(sc, EMMCP_SEND0, 0);

sys/dev/mmc/host/dwmmc_samsung.c

103

WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |

sys/dev/rtsx/rtsx.c

1341

WRITE4(sc, RTSX_HAIMR, arg);

sys/dev/rtsx/rtsx.c

1397

WRITE4(sc, RTSX_HAIMR, arg);

sys/dev/rtsx/rtsx.c

2274

WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer);

sys/dev/rtsx/rtsx.c

2275

WRITE4(sc, RTSX_HCBCTLR,

sys/dev/rtsx/rtsx.c

2286

WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);

sys/dev/rtsx/rtsx.c

2289

WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);

sys/dev/rtsx/rtsx.c

2895

WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer);

sys/dev/rtsx/rtsx.c

2896

WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) |

sys/dev/rtsx/rtsx.c

3788

WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);

sys/dev/rtsx/rtsx.c

563

WRITE4(sc, RTSX_BIPR, status);

sys/dev/rtsx/rtsx.c

890

WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);

sys/dev/xdma/controller/pl330.c

170

WRITE4(sc, INTCLR, pending);

sys/dev/xdma/controller/pl330.c

550

WRITE4(sc, DBGINST0, reg);

sys/dev/xdma/controller/pl330.c

552

WRITE4(sc, DBGINST1, reg);

sys/dev/xdma/controller/pl330.c

554

WRITE4(sc, INTCLR, 0xffffffff);

sys/dev/xdma/controller/pl330.c

555

WRITE4(sc, INTEN, (1 << chan->index));

sys/dev/xdma/controller/pl330.c

561

WRITE4(sc, DBGCMD, 0);

sys/dev/xilinx/axi_quad_spi.c

146

WRITE4(sc, SPI_SRR, SRR_RESET);

sys/dev/xilinx/axi_quad_spi.c

151

WRITE4(sc, SPI_CR, reg);

sys/dev/xilinx/axi_quad_spi.c

152

WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */

sys/dev/xilinx/axi_quad_spi.c

155

WRITE4(sc, SPI_CR, reg);

sys/dev/xilinx/axi_quad_spi.c

170

WRITE4(sc, SPI_DTR, out_buf[i]);

sys/dev/xilinx/axi_quad_spi.c

205

WRITE4(sc, SPI_SSR, reg);

sys/dev/xilinx/axi_quad_spi.c

216

WRITE4(sc, SPI_SSR, reg);