SHIFT24
#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24
bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
((bc & BC_MASK) << SHIFT24) |
bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
((bc & BC_MASK) << SHIFT24) |
*pBC = (bit8)((msgHeader_tmp >> SHIFT24) & BC_MASK);
SA_DBG3(("mpiMsgConsume: SKIP_ENTRIES_IOMB BC=%d\n", (msgHeader_tmp >> SHIFT24) & BC_MASK));
circularQ->consumerIdx = (circularQ->consumerIdx + ((msgHeader_tmp >> SHIFT24) & BC_MASK)) % circularQ->numElements;
bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
((bc & BC_MASK) << SHIFT24) |
sDTypeRate = agDeviceInfo->devType_S_Rate << SHIFT24;
regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD;
regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA;
hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC;
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_RAAE_IMG_GET;
ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len );
SA_DBG1(("siHDAMode_V: write ILAHDAC_RAAE_IMG_DONE to MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_RAAE_IMG_DONE << SHIFT24) | userFwImg->aap1Len));
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET;
ossaHwRegWriteExt(agRoot, PCIBAR0,MSGU_HOST_SCRATCH_PAD_3 ,(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen );
SA_DBG2(("siHDAMode_V: MSGU_HOST_SCRATCH_PAD_3 0x%X\n",(ILAHDAC_IOP_IMG_DONE << SHIFT24) | userFwImg->iopLen));
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register) & 0xff000000 ) >> SHIFT24 ) == ILAHDA_IOP_IMG_GET;
(queueConfig->tgtDeviceRemovedEventQueue << SHIFT24);
(queueConfig->sasHwEventQueue[3] << SHIFT24);
(queueConfig->sasHwEventQueue[7] << SHIFT24);
(queueConfig->sataNCQErrorEventQueue[3] << SHIFT24);
(queueConfig->sataNCQErrorEventQueue[7] << SHIFT24);
outQueueCfg.interruptVecCntDelay = ((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24);
((config->outboundQueues[qIdx].interruptVector & INT_VEC_BITS ) << SHIFT24);
ExpSignature = ('P') | ('M' << SHIFT8) | ('C' << SHIFT16) | ('S' << SHIFT24);
AnalogtableSize >>= SHIFT24;
((( controllerStatus->fatalErrorInfo.errorInfo3 >> SHIFT16) & 0xFF) << SHIFT24) );/* bit 24 31 */
SA_DBG1(("saGetControllerStatus: bootStatus Encryption Engine Stat 0x%x\n", ((controllerStatus->bootStatus & 0xFF000000 ) >> SHIFT24) ));
UDTR5_UDTR2 = (( diag->udrtArray[5] << SHIFT24) | (diag->udrtArray[4] << SHIFT16) | (diag->udrtArray[3] << SHIFT8) | diag->udrtArray[2]);
UDT5_UDT2 = (( diag->udtArray[5] << SHIFT24) | (diag->udtArray[4] << SHIFT16) | (diag->udtArray[3] << SHIFT8) | diag->udtArray[2]);
UDTR1_UDT0 = (( diag->udrtArray[1] << SHIFT24) | (diag->udrtArray[0] << SHIFT16) | (diag->udtArray[1] << SHIFT8) | diag->udtArray[0]);
((portId & PORTID_MASK) | (maxDevs << SHIFT8) | (flags << SHIFT24)));
DW4 = (action << SHIFT24) | \
NVMDInfo->dataOffsetAddress | (NVMDInfo->directLen << SHIFT24));
NVMDInfo->dataOffsetAddress | (NVMDInfo->directLen << SHIFT24));
dw8 = agDifEncOffload->dif.udrtArray[1] << SHIFT24 |
dw9 = agDifEncOffload->dif.udtArray[5] << SHIFT24 |
dw10 = agDifEncOffload->dif.udrtArray[5] << SHIFT24 |
bc = (((msgHeader->Header) >> SHIFT24) & BC_MASK);
status = (LREventPhyIdPortId & STATUS_BITS) >> SHIFT24;
commonDevInfo.devType_S_Rate = (bit8)((ARSrateSMPTimeOutPortID >> SHIFT24) & 0x3f);
(bit8)((dTypeSrateSMPTOPortID >> SHIFT24) & LINK_RATE_BITS);
(bit8)((dTypeSrateSMPTOPortID >> SHIFT24) & LINK_RATE_BITS);
((frameTypeHssa >> SHIFT24) & FRAME_TYPE) |
((frameTypeHssa >> SHIFT24) & FRAME_TYPE) |
SA_DBG1(("mpiGetNVMDataRsp: OSSA_SUCCESS, IR=0, DataLen=%d\n", ((DlenStatus & NVMD_LEN) >> SHIFT24)));
for (i = 0; i < (((DlenStatus & NVMD_LEN) >> SHIFT24)/4); i++)
((DlenStatus & NVMD_LEN) >> SHIFT24), (agsaFrameHandle_t *)safe_type_pun);
phyportid |= ((eventSource->param & 0x000000FF) << SHIFT24);
(kekIndex << SHIFT24) | (dekTableSelect << SHIFT8) | DEK_MGMT_SUBOP_UPDATE);
(newKekIndex << SHIFT24) | (wrapperKekIndex << SHIFT16) | blobFormat << SHIFT14 | (flags << SHIFT8) | KEK_MGMT_SUBOP_UPDATE);
(1 << SHIFT24) | (1 << SHIFT16) | (1 << SHIFT8) | KEK_MGMT_SUBOP_KEYCARDUPDATE);
(((agSATAReq->option & SATA_FIS_MASK) << SHIFT24) |
(((agSATAReq->option & SATA_FIS_MASK) << SHIFT24) |
UDT5_UDT4_UDT3_UDT2 = (pIRequest->dif.udtArray[5] << SHIFT24 |
UDTR1_UDTR0_UDT1_UDT0 |= (pIRequest->dif.udrtArray[1] << SHIFT24 |
UDTR5_UDTR4_UDTR3_UDTR2 = (pIRequest->dif.udrtArray[5] << SHIFT24 |
UDT5_UDT4_UDT3_UDT2 = (pTRequest->dif.udtArray[5] << SHIFT24 |
UDTR1_UDTR0_UDT1_UDT0 |= (pTRequest->dif.udrtArray[1] << SHIFT24 |
UDTR5_UDTR4_UDTR3_UDTR2 = (pTRequest->dif.udrtArray[5] << SHIFT24 |
DirDW4 |= ((pIndRequest->sspInitiatorReqLen >> 2) & 0xFF) << SHIFT24;
#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */